1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
25 //===----------------------------------------------------------------------===//
26 // Integer Result Promotion
27 //===----------------------------------------------------------------------===//
29 /// PromoteIntegerResult - This method is called when a result of a node is
30 /// found to be in need of promotion to a larger type. At this point, the node
31 /// may also have invalid operands or may have other results that need
32 /// expansion, we just know that (at least) one result needs promotion.
33 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
35 SDValue Res = SDValue();
37 // See if the target wants to custom expand this node.
38 if (CustomLowerResults(N, N->getValueType(ResNo), true))
41 switch (N->getOpcode()) {
44 cerr << "PromoteIntegerResult #" << ResNo << ": ";
45 N->dump(&DAG); cerr << "\n";
47 assert(0 && "Do not know how to promote this operator!");
49 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
50 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
51 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
52 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
53 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
54 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
55 case ISD::CONVERT_RNDSAT:
56 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
57 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
58 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
59 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
60 case ISD::EXTRACT_VECTOR_ELT:
61 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
62 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
63 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
64 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
65 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
66 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
67 case ISD::SIGN_EXTEND_INREG:
68 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
69 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
70 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
71 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
72 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
73 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
75 case ISD::SIGN_EXTEND:
76 case ISD::ZERO_EXTEND:
77 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
80 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
87 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
90 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
93 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
96 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
98 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
100 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
102 case ISD::ATOMIC_LOAD_ADD:
103 case ISD::ATOMIC_LOAD_SUB:
104 case ISD::ATOMIC_LOAD_AND:
105 case ISD::ATOMIC_LOAD_OR:
106 case ISD::ATOMIC_LOAD_XOR:
107 case ISD::ATOMIC_LOAD_NAND:
108 case ISD::ATOMIC_LOAD_MIN:
109 case ISD::ATOMIC_LOAD_MAX:
110 case ISD::ATOMIC_LOAD_UMIN:
111 case ISD::ATOMIC_LOAD_UMAX:
112 case ISD::ATOMIC_SWAP:
113 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
115 case ISD::ATOMIC_CMP_SWAP:
116 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
119 // If the result is null then the sub-method took care of registering it.
121 SetPromotedInteger(SDValue(N, ResNo), Res);
124 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
125 // Sign-extend the new bits, and continue the assertion.
126 SDValue Op = SExtPromotedInteger(N->getOperand(0));
127 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
128 Op.getValueType(), Op, N->getOperand(1));
131 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
132 // Zero the new bits, and continue the assertion.
133 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
134 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
135 Op.getValueType(), Op, N->getOperand(1));
138 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
139 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
140 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
142 N->getChain(), N->getBasePtr(),
143 Op2, N->getSrcValue(), N->getAlignment());
144 // Legalized the chain result - switch anything that used the old chain to
146 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
150 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
151 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
152 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
153 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
154 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
155 Op2, Op3, N->getSrcValue(), N->getAlignment());
156 // Legalized the chain result - switch anything that used the old chain to
158 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
162 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
163 SDValue InOp = N->getOperand(0);
164 MVT InVT = InOp.getValueType();
165 MVT NInVT = TLI.getTypeToTransformTo(InVT);
166 MVT OutVT = N->getValueType(0);
167 MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
168 DebugLoc dl = N->getDebugLoc();
170 switch (getTypeAction(InVT)) {
172 assert(false && "Unknown type action!");
177 if (NOutVT.bitsEq(NInVT))
178 // The input promotes to the same size. Convert the promoted value.
179 return DAG.getNode(ISD::BIT_CONVERT, dl,
180 NOutVT, GetPromotedInteger(InOp));
183 // Promote the integer operand by hand.
184 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
188 case ScalarizeVector:
189 // Convert the element to an integer and promote it by hand.
190 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
191 BitConvertToInteger(GetScalarizedVector(InOp)));
193 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
194 // pieces of the input into integers and reassemble in the final type.
196 GetSplitVector(N->getOperand(0), Lo, Hi);
197 Lo = BitConvertToInteger(Lo);
198 Hi = BitConvertToInteger(Hi);
200 if (TLI.isBigEndian())
203 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
204 MVT::getIntegerVT(NOutVT.getSizeInBits()),
205 JoinIntegers(Lo, Hi));
206 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
209 if (OutVT.bitsEq(NInVT))
210 // The input is widened to the same size. Convert to the widened value.
211 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
214 // Otherwise, lower the bit-convert to a store/load from the stack.
215 // Create the stack frame object. Make sure it is aligned for both
216 // the source and destination types.
217 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT);
218 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
219 const Value *SV = PseudoSourceValue::getFixedStack(FI);
221 // Emit a store to the stack slot.
222 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0);
224 // Result is an extending load from the stack slot.
225 return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, SV, 0, OutVT);
228 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
229 SDValue Op = GetPromotedInteger(N->getOperand(0));
230 MVT OVT = N->getValueType(0);
231 MVT NVT = Op.getValueType();
232 DebugLoc dl = N->getDebugLoc();
234 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
235 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
236 DAG.getConstant(DiffBits, TLI.getPointerTy()));
239 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
240 // The pair element type may be legal, or may not promote to the same type as
241 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
242 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
243 TLI.getTypeToTransformTo(N->getValueType(0)),
244 JoinIntegers(N->getOperand(0), N->getOperand(1)));
247 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
248 MVT VT = N->getValueType(0);
249 // FIXME there is no actual debug info here
250 DebugLoc dl = N->getDebugLoc();
251 // Zero extend things like i1, sign extend everything else. It shouldn't
252 // matter in theory which one we pick, but this tends to give better code?
253 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
254 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT),
256 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
260 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
261 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
262 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
263 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
264 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
265 "can only promote integers");
266 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
267 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
268 N->getOperand(1), N->getOperand(2),
269 N->getOperand(3), N->getOperand(4), CvtCode);
272 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
273 // Zero extend to the promoted type and do the count there.
274 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
275 DebugLoc dl = N->getDebugLoc();
276 MVT OVT = N->getValueType(0);
277 MVT NVT = Op.getValueType();
278 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
279 // Subtract off the extra leading bits in the bigger type.
280 return DAG.getNode(ISD::SUB, dl, NVT, Op,
281 DAG.getConstant(NVT.getSizeInBits() -
282 OVT.getSizeInBits(), NVT));
285 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
286 // Zero extend to the promoted type and do the count there.
287 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
288 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
291 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
292 SDValue Op = GetPromotedInteger(N->getOperand(0));
293 MVT OVT = N->getValueType(0);
294 MVT NVT = Op.getValueType();
295 DebugLoc dl = N->getDebugLoc();
296 // The count is the same in the promoted type except if the original
297 // value was zero. This can be handled by setting the bit just off
298 // the top of the original type.
299 APInt TopBit(NVT.getSizeInBits(), 0);
300 TopBit.set(OVT.getSizeInBits());
301 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
302 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
305 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
306 MVT OldVT = N->getValueType(0);
307 SDValue OldVec = N->getOperand(0);
308 if (getTypeAction(OldVec.getValueType()) == WidenVector)
309 OldVec = GetWidenedVector(N->getOperand(0));
310 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
311 DebugLoc dl = N->getDebugLoc();
314 assert(!isTypeLegal(OldVec.getValueType()) &&
315 "Legal one-element vector of a type needing promotion!");
316 // It is tempting to follow GetScalarizedVector by a call to
317 // GetPromotedInteger, but this would be wrong because the
318 // scalarized value may not yet have been processed.
319 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT),
320 GetScalarizedVector(OldVec));
323 // Convert to a vector half as long with an element type of twice the width,
324 // for example <4 x i16> -> <2 x i32>.
325 assert(!(OldElts & 1) && "Odd length vectors not supported!");
326 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
327 assert(OldVT.isSimple() && NewVT.isSimple());
329 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
330 MVT::getVectorVT(NewVT, OldElts / 2),
333 // Extract the element at OldIdx / 2 from the new vector.
334 SDValue OldIdx = N->getOperand(1);
335 SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx,
336 DAG.getConstant(1, TLI.getPointerTy()));
337 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx);
339 // Select the appropriate half of the element: Lo if OldIdx was even,
342 SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt,
343 DAG.getConstant(OldVT.getSizeInBits(),
344 TLI.getPointerTy()));
345 if (TLI.isBigEndian())
348 // Extend to the promoted type.
349 SDValue Odd = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, OldIdx);
350 SDValue Res = DAG.getNode(ISD::SELECT, dl, NewVT, Odd, Hi, Lo);
351 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), Res);
354 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
355 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
356 unsigned NewOpc = N->getOpcode();
357 DebugLoc dl = N->getDebugLoc();
359 // If we're promoting a UINT to a larger size, check to see if the new node
360 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
361 // we can use that instead. This allows us to generate better code for
362 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
363 // legal, such as PowerPC.
364 if (N->getOpcode() == ISD::FP_TO_UINT &&
365 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
366 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
367 NewOpc = ISD::FP_TO_SINT;
369 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
371 // Assert that the converted value fits in the original type. If it doesn't
372 // (eg: because the value being converted is too big), then the result of the
373 // original operation was undefined anyway, so the assert is still correct.
374 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
375 ISD::AssertZext : ISD::AssertSext, dl,
376 NVT, Res, DAG.getValueType(N->getValueType(0)));
379 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
380 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
381 DebugLoc dl = N->getDebugLoc();
383 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
384 SDValue Res = GetPromotedInteger(N->getOperand(0));
385 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
387 // If the result and operand types are the same after promotion, simplify
388 // to an in-register extension.
389 if (NVT == Res.getValueType()) {
390 // The high bits are not guaranteed to be anything. Insert an extend.
391 if (N->getOpcode() == ISD::SIGN_EXTEND)
392 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
393 DAG.getValueType(N->getOperand(0).getValueType()));
394 if (N->getOpcode() == ISD::ZERO_EXTEND)
395 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
396 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
401 // Otherwise, just extend the original operand all the way to the larger type.
402 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
405 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
406 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
407 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
408 ISD::LoadExtType ExtType =
409 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
410 DebugLoc dl = N->getDebugLoc();
411 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
412 N->getSrcValue(), N->getSrcValueOffset(),
413 N->getMemoryVT(), N->isVolatile(),
416 // Legalized the chain result - switch anything that used the old chain to
418 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
422 /// Promote the overflow flag of an overflowing arithmetic node.
423 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
424 // Simply change the return type of the boolean result.
425 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
426 MVT ValueVTs[] = { N->getValueType(0), NVT };
427 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
428 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
429 DAG.getVTList(ValueVTs, 2), Ops, 2);
431 // Modified the sum result - switch anything that used the old sum to use
433 ReplaceValueWith(SDValue(N, 0), Res);
435 return SDValue(Res.getNode(), 1);
438 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
440 return PromoteIntRes_Overflow(N);
442 // The operation overflowed iff the result in the larger type is not the
443 // sign extension of its truncation to the original type.
444 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
445 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
446 MVT OVT = N->getOperand(0).getValueType();
447 MVT NVT = LHS.getValueType();
448 DebugLoc dl = N->getDebugLoc();
450 // Do the arithmetic in the larger type.
451 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
452 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
454 // Calculate the overflow flag: sign extend the arithmetic result from
455 // the original type.
456 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
457 DAG.getValueType(OVT));
458 // Overflowed if and only if this is not equal to Res.
459 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
461 // Use the calculated overflow everywhere.
462 ReplaceValueWith(SDValue(N, 1), Ofl);
467 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
468 // Sign extend the input.
469 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
470 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
471 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
472 LHS.getValueType(), LHS, RHS);
475 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
476 SDValue LHS = GetPromotedInteger(N->getOperand(1));
477 SDValue RHS = GetPromotedInteger(N->getOperand(2));
478 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
479 LHS.getValueType(), N->getOperand(0),LHS,RHS);
482 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
483 SDValue LHS = GetPromotedInteger(N->getOperand(2));
484 SDValue RHS = GetPromotedInteger(N->getOperand(3));
485 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
486 LHS.getValueType(), N->getOperand(0),
487 N->getOperand(1), LHS, RHS, N->getOperand(4));
490 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
491 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
492 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
493 DebugLoc dl = N->getDebugLoc();
495 // Get the SETCC result using the canonical SETCC type.
496 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
497 N->getOperand(1), N->getOperand(2));
499 // Convert to the expected type.
500 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
501 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
502 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
505 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
506 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
507 TLI.getTypeToTransformTo(N->getValueType(0)),
508 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
511 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
512 SDValue Op = GetPromotedInteger(N->getOperand(0));
513 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
514 Op.getValueType(), Op, N->getOperand(1));
517 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
518 // The input may have strange things in the top bits of the registers, but
519 // these operations don't care. They may have weird bits going out, but
520 // that too is okay if they are integer operations.
521 SDValue LHS = GetPromotedInteger(N->getOperand(0));
522 SDValue RHS = GetPromotedInteger(N->getOperand(1));
523 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
524 LHS.getValueType(), LHS, RHS);
527 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
528 // The input value must be properly sign extended.
529 SDValue Res = SExtPromotedInteger(N->getOperand(0));
530 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
531 Res.getValueType(), Res, N->getOperand(1));
534 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
535 // The input value must be properly zero extended.
536 MVT VT = N->getValueType(0);
537 MVT NVT = TLI.getTypeToTransformTo(VT);
538 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
539 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
542 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
543 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
546 switch (getTypeAction(N->getOperand(0).getValueType())) {
547 default: assert(0 && "Unknown type action!");
550 Res = N->getOperand(0);
553 Res = GetPromotedInteger(N->getOperand(0));
557 // Truncate to NVT instead of VT
558 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
561 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
563 return PromoteIntRes_Overflow(N);
565 // The operation overflowed iff the result in the larger type is not the
566 // zero extension of its truncation to the original type.
567 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
568 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
569 MVT OVT = N->getOperand(0).getValueType();
570 MVT NVT = LHS.getValueType();
571 DebugLoc dl = N->getDebugLoc();
573 // Do the arithmetic in the larger type.
574 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
575 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
577 // Calculate the overflow flag: zero extend the arithmetic result from
578 // the original type.
579 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
580 // Overflowed if and only if this is not equal to Res.
581 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
583 // Use the calculated overflow everywhere.
584 ReplaceValueWith(SDValue(N, 1), Ofl);
589 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
590 // Zero extend the input.
591 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
592 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
593 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
594 LHS.getValueType(), LHS, RHS);
597 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
598 return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0)));
601 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
602 SDValue Chain = N->getOperand(0); // Get the chain.
603 SDValue Ptr = N->getOperand(1); // Get the pointer.
604 MVT VT = N->getValueType(0);
605 DebugLoc dl = N->getDebugLoc();
607 MVT RegVT = TLI.getRegisterType(VT);
608 unsigned NumRegs = TLI.getNumRegisters(VT);
609 // The argument is passed as NumRegs registers of type RegVT.
611 SmallVector<SDValue, 8> Parts(NumRegs);
612 for (unsigned i = 0; i < NumRegs; ++i) {
613 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
614 Chain = Parts[i].getValue(1);
617 // Handle endianness of the load.
618 if (TLI.isBigEndian())
619 std::reverse(Parts.begin(), Parts.end());
621 // Assemble the parts in the promoted type.
622 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
623 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
624 for (unsigned i = 1; i < NumRegs; ++i) {
625 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
626 // Shift it to the right position and "or" it in.
627 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
628 DAG.getConstant(i * RegVT.getSizeInBits(),
629 TLI.getPointerTy()));
630 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
633 // Modified the chain result - switch anything that used the old chain to
635 ReplaceValueWith(SDValue(N, 1), Chain);
640 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
641 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
642 return PromoteIntRes_Overflow(N);
645 //===----------------------------------------------------------------------===//
646 // Integer Operand Promotion
647 //===----------------------------------------------------------------------===//
649 /// PromoteIntegerOperand - This method is called when the specified operand of
650 /// the specified node is found to need promotion. At this point, all of the
651 /// result types of the node are known to be legal, but other operands of the
652 /// node may need promotion or expansion as well as the specified one.
653 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
654 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
655 SDValue Res = SDValue();
657 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false))
660 switch (N->getOpcode()) {
663 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
664 N->dump(&DAG); cerr << "\n";
666 assert(0 && "Do not know how to promote this operator's operand!");
669 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
670 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
671 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
672 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
673 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
674 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
675 case ISD::CONVERT_RNDSAT:
676 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
677 case ISD::INSERT_VECTOR_ELT:
678 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
679 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
680 case ISD::SCALAR_TO_VECTOR:
681 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
682 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
683 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
684 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
685 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
686 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
687 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
689 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
690 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
691 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
697 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
700 // If the result is null, the sub-method took care of registering results etc.
701 if (!Res.getNode()) return false;
703 // If the result is N, the sub-method updated N in place. Tell the legalizer
705 if (Res.getNode() == N)
708 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
709 "Invalid operand expansion");
711 ReplaceValueWith(SDValue(N, 0), Res);
715 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
716 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
717 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
718 ISD::CondCode CCCode) {
719 // We have to insert explicit sign or zero extends. Note that we could
720 // insert sign extends for ALL conditions, but zero extend is cheaper on
721 // many machines (an AND instead of two shifts), so prefer it.
723 default: assert(0 && "Unknown integer comparison!");
730 // ALL of these operations will work if we either sign or zero extend
731 // the operands (including the unsigned comparisons!). Zero extend is
732 // usually a simpler/cheaper operation, so prefer it.
733 NewLHS = ZExtPromotedInteger(NewLHS);
734 NewRHS = ZExtPromotedInteger(NewRHS);
740 NewLHS = SExtPromotedInteger(NewLHS);
741 NewRHS = SExtPromotedInteger(NewRHS);
746 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
747 SDValue Op = GetPromotedInteger(N->getOperand(0));
748 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
751 SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) {
752 // This should only occur in unusual situations like bitcasting to an
753 // x86_fp80, so just turn it into a store+load
754 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
757 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
758 assert(OpNo == 2 && "Don't know how to promote this operand!");
760 SDValue LHS = N->getOperand(2);
761 SDValue RHS = N->getOperand(3);
762 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
764 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
766 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
767 N->getOperand(1), LHS, RHS, N->getOperand(4));
770 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
771 assert(OpNo == 1 && "only know how to promote condition");
773 // Promote all the way up to the canonical SetCC type.
774 MVT SVT = TLI.getSetCCResultType(MVT::Other);
775 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
777 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
778 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
782 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
783 // Since the result type is legal, the operands must promote to it.
784 MVT OVT = N->getOperand(0).getValueType();
785 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
786 SDValue Hi = GetPromotedInteger(N->getOperand(1));
787 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
788 DebugLoc dl = N->getDebugLoc();
790 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
791 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
792 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
795 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
796 // The vector type is legal but the element type is not. This implies
797 // that the vector is a power-of-two in length and that the element
798 // type does not have a strange size (eg: it is not i1).
799 MVT VecVT = N->getValueType(0);
800 unsigned NumElts = VecVT.getVectorNumElements();
801 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
803 // Promote the inserted value. The type does not need to match the
804 // vector element type. Check that any extra bits introduced will be
806 assert(N->getOperand(0).getValueType().getSizeInBits() >=
807 N->getValueType(0).getVectorElementType().getSizeInBits() &&
808 "Type of inserted value narrower than vector element type!");
810 SmallVector<SDValue, 16> NewOps;
811 for (unsigned i = 0; i < NumElts; ++i)
812 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
814 return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts);
817 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
818 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
819 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
820 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
821 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
822 "can only promote integer arguments");
823 SDValue InOp = GetPromotedInteger(N->getOperand(0));
824 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
825 N->getOperand(1), N->getOperand(2),
826 N->getOperand(3), N->getOperand(4), CvtCode);
829 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
832 // Promote the inserted value. This is valid because the type does not
833 // have to match the vector element type.
835 // Check that any extra bits introduced will be truncated away.
836 assert(N->getOperand(1).getValueType().getSizeInBits() >=
837 N->getValueType(0).getVectorElementType().getSizeInBits() &&
838 "Type of inserted value narrower than vector element type!");
839 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
840 GetPromotedInteger(N->getOperand(1)),
844 assert(OpNo == 2 && "Different operand and result vector types?");
846 // Promote the index.
847 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
848 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
849 N->getOperand(1), Idx);
852 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
854 DebugLoc dl = N->getDebugLoc();
855 NewOps[0] = N->getOperand(0);
856 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
857 SDValue Flag = GetPromotedInteger(N->getOperand(i));
858 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
860 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
861 array_lengthof(NewOps));
864 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
865 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
866 // the operand in place.
867 return DAG.UpdateNodeOperands(SDValue(N, 0),
868 GetPromotedInteger(N->getOperand(0)));
871 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
872 assert(OpNo == 0 && "Only know how to promote condition");
874 // Promote all the way up to the canonical SetCC type.
875 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
876 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
878 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
879 N->getOperand(1), N->getOperand(2));
882 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
883 assert(OpNo == 0 && "Don't know how to promote this operand!");
885 SDValue LHS = N->getOperand(0);
886 SDValue RHS = N->getOperand(1);
887 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
889 // The CC (#4) and the possible return values (#2 and #3) have legal types.
890 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
891 N->getOperand(3), N->getOperand(4));
894 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
895 assert(OpNo == 0 && "Don't know how to promote this operand!");
897 SDValue LHS = N->getOperand(0);
898 SDValue RHS = N->getOperand(1);
899 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
901 // The CC (#2) is always legal.
902 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
905 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
906 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
907 ZExtPromotedInteger(N->getOperand(1)));
910 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
911 SDValue Op = GetPromotedInteger(N->getOperand(0));
912 DebugLoc dl = N->getDebugLoc();
913 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
914 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
915 Op, DAG.getValueType(N->getOperand(0).getValueType()));
918 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
919 return DAG.UpdateNodeOperands(SDValue(N, 0),
920 SExtPromotedInteger(N->getOperand(0)));
923 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
924 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
925 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
926 int SVOffset = N->getSrcValueOffset();
927 unsigned Alignment = N->getAlignment();
928 bool isVolatile = N->isVolatile();
929 DebugLoc dl = N->getDebugLoc();
931 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
933 // Truncate the value and store the result.
934 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
935 SVOffset, N->getMemoryVT(),
936 isVolatile, Alignment);
939 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
940 SDValue Op = GetPromotedInteger(N->getOperand(0));
941 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
944 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
945 return DAG.UpdateNodeOperands(SDValue(N, 0),
946 ZExtPromotedInteger(N->getOperand(0)));
949 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
950 DebugLoc dl = N->getDebugLoc();
951 SDValue Op = GetPromotedInteger(N->getOperand(0));
952 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
953 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
957 //===----------------------------------------------------------------------===//
958 // Integer Result Expansion
959 //===----------------------------------------------------------------------===//
961 /// ExpandIntegerResult - This method is called when the specified result of the
962 /// specified node is found to need expansion. At this point, the node may also
963 /// have invalid operands or may have other results that need promotion, we just
964 /// know that (at least) one result needs expansion.
965 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
966 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
970 // See if the target wants to custom expand this node.
971 if (CustomLowerResults(N, N->getValueType(ResNo), true))
974 switch (N->getOpcode()) {
977 cerr << "ExpandIntegerResult #" << ResNo << ": ";
978 N->dump(&DAG); cerr << "\n";
980 assert(0 && "Do not know how to expand the result of this operator!");
983 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
984 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
985 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
986 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
988 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
989 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
990 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
991 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
992 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
994 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
995 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
996 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
997 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
998 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
999 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1000 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1001 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1002 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1003 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1004 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1005 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1006 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1007 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1008 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1009 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1010 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1011 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1012 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1013 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1017 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1020 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1023 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1026 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1030 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1033 // If Lo/Hi is null, the sub-method took care of registering results etc.
1035 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1038 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1039 /// and the shift amount is a constant 'Amt'. Expand the operation.
1040 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1041 SDValue &Lo, SDValue &Hi) {
1042 DebugLoc dl = N->getDebugLoc();
1043 // Expand the incoming operand to be shifted, so that we have its parts
1045 GetExpandedInteger(N->getOperand(0), InL, InH);
1047 MVT NVT = InL.getValueType();
1048 unsigned VTBits = N->getValueType(0).getSizeInBits();
1049 unsigned NVTBits = NVT.getSizeInBits();
1050 MVT ShTy = N->getOperand(1).getValueType();
1052 if (N->getOpcode() == ISD::SHL) {
1054 Lo = Hi = DAG.getConstant(0, NVT);
1055 } else if (Amt > NVTBits) {
1056 Lo = DAG.getConstant(0, NVT);
1057 Hi = DAG.getNode(ISD::SHL, dl,
1058 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1059 } else if (Amt == NVTBits) {
1060 Lo = DAG.getConstant(0, NVT);
1062 } else if (Amt == 1 &&
1063 TLI.isOperationLegalOrCustom(ISD::ADDC,
1064 TLI.getTypeToExpandTo(NVT))) {
1065 // Emit this X << 1 as X+X.
1066 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1067 SDValue LoOps[2] = { InL, InL };
1068 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1069 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1070 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1072 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1073 Hi = DAG.getNode(ISD::OR, dl, NVT,
1074 DAG.getNode(ISD::SHL, dl, NVT, InH,
1075 DAG.getConstant(Amt, ShTy)),
1076 DAG.getNode(ISD::SRL, dl, NVT, InL,
1077 DAG.getConstant(NVTBits-Amt, ShTy)));
1082 if (N->getOpcode() == ISD::SRL) {
1084 Lo = DAG.getConstant(0, NVT);
1085 Hi = DAG.getConstant(0, NVT);
1086 } else if (Amt > NVTBits) {
1087 Lo = DAG.getNode(ISD::SRL, dl,
1088 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1089 Hi = DAG.getConstant(0, NVT);
1090 } else if (Amt == NVTBits) {
1092 Hi = DAG.getConstant(0, NVT);
1094 Lo = DAG.getNode(ISD::OR, dl, NVT,
1095 DAG.getNode(ISD::SRL, dl, NVT, InL,
1096 DAG.getConstant(Amt, ShTy)),
1097 DAG.getNode(ISD::SHL, dl, NVT, InH,
1098 DAG.getConstant(NVTBits-Amt, ShTy)));
1099 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1104 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1106 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1107 DAG.getConstant(NVTBits-1, ShTy));
1108 } else if (Amt > NVTBits) {
1109 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1110 DAG.getConstant(Amt-NVTBits, ShTy));
1111 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1112 DAG.getConstant(NVTBits-1, ShTy));
1113 } else if (Amt == NVTBits) {
1115 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1116 DAG.getConstant(NVTBits-1, ShTy));
1118 Lo = DAG.getNode(ISD::OR, dl, NVT,
1119 DAG.getNode(ISD::SRL, dl, NVT, InL,
1120 DAG.getConstant(Amt, ShTy)),
1121 DAG.getNode(ISD::SHL, dl, NVT, InH,
1122 DAG.getConstant(NVTBits-Amt, ShTy)));
1123 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1127 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1128 /// this shift based on knowledge of the high bit of the shift amount. If we
1129 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1131 bool DAGTypeLegalizer::
1132 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1133 SDValue Amt = N->getOperand(1);
1134 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1135 MVT ShTy = Amt.getValueType();
1136 unsigned ShBits = ShTy.getSizeInBits();
1137 unsigned NVTBits = NVT.getSizeInBits();
1138 assert(isPowerOf2_32(NVTBits) &&
1139 "Expanded integer type size not a power of two!");
1140 DebugLoc dl = N->getDebugLoc();
1142 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1143 APInt KnownZero, KnownOne;
1144 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1146 // If we don't know anything about the high bits, exit.
1147 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1150 // Get the incoming operand to be shifted.
1152 GetExpandedInteger(N->getOperand(0), InL, InH);
1154 // If we know that any of the high bits of the shift amount are one, then we
1155 // can do this as a couple of simple shifts.
1156 if (KnownOne.intersects(HighBitMask)) {
1157 // Mask out the high bit, which we know is set.
1158 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1159 DAG.getConstant(~HighBitMask, ShTy));
1161 switch (N->getOpcode()) {
1162 default: assert(0 && "Unknown shift");
1164 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1165 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1168 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1169 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1172 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1173 DAG.getConstant(NVTBits-1, ShTy));
1174 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1180 // FIXME: This code is broken for shifts with a zero amount!
1181 // If we know that all of the high bits of the shift amount are zero, then we
1182 // can do this as a couple of simple shifts.
1183 if ((KnownZero & HighBitMask) == HighBitMask) {
1185 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1186 DAG.getConstant(NVTBits, ShTy),
1189 switch (N->getOpcode()) {
1190 default: assert(0 && "Unknown shift");
1191 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1193 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1196 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1197 Hi = DAG.getNode(ISD::OR, NVT,
1198 DAG.getNode(Op1, NVT, InH, Amt),
1199 DAG.getNode(Op2, NVT, InL, Amt2));
1207 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1209 bool DAGTypeLegalizer::
1210 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1211 SDValue Amt = N->getOperand(1);
1212 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1213 MVT ShTy = Amt.getValueType();
1214 unsigned NVTBits = NVT.getSizeInBits();
1215 assert(isPowerOf2_32(NVTBits) &&
1216 "Expanded integer type size not a power of two!");
1217 DebugLoc dl = N->getDebugLoc();
1219 // Get the incoming operand to be shifted.
1221 GetExpandedInteger(N->getOperand(0), InL, InH);
1223 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1224 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1225 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1226 Amt, NVBitsNode, ISD::SETULT);
1228 SDValue Lo1, Hi1, Lo2, Hi2;
1229 switch (N->getOpcode()) {
1230 default: assert(0 && "Unknown shift");
1233 Lo1 = DAG.getConstant(0, NVT); // Low part is zero.
1234 Hi1 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1237 Lo2 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1238 Hi2 = DAG.getNode(ISD::OR, dl, NVT,
1239 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1240 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
1242 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1243 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1247 Hi1 = DAG.getConstant(0, NVT); // Hi part is zero.
1248 Lo1 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1251 Hi2 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1252 Lo2 = DAG.getNode(ISD::OR, dl, NVT,
1253 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1254 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
1256 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1257 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1261 Hi1 = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1262 DAG.getConstant(NVTBits-1, ShTy));
1263 Lo1 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1266 Hi2 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1267 Lo2 = DAG.getNode(ISD::OR, dl, NVT,
1268 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1269 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
1271 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1272 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1279 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1280 SDValue &Lo, SDValue &Hi) {
1281 DebugLoc dl = N->getDebugLoc();
1282 // Expand the subcomponents.
1283 SDValue LHSL, LHSH, RHSL, RHSH;
1284 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1285 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1287 MVT NVT = LHSL.getValueType();
1288 SDValue LoOps[2] = { LHSL, RHSL };
1289 SDValue HiOps[3] = { LHSH, RHSH };
1291 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1292 // them. TODO: Teach operation legalization how to expand unsupported
1293 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1294 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1295 // generate a value of this type in the expanded code sequence.
1297 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1298 ISD::ADDC : ISD::SUBC,
1299 TLI.getTypeToExpandTo(NVT));
1302 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1303 if (N->getOpcode() == ISD::ADD) {
1304 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1305 HiOps[2] = Lo.getValue(1);
1306 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1308 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1309 HiOps[2] = Lo.getValue(1);
1310 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1313 if (N->getOpcode() == ISD::ADD) {
1314 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1315 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1316 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1318 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1319 DAG.getConstant(1, NVT),
1320 DAG.getConstant(0, NVT));
1321 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1323 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1324 DAG.getConstant(1, NVT), Carry1);
1325 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1327 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1328 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1330 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1331 LoOps[0], LoOps[1], ISD::SETULT);
1332 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1333 DAG.getConstant(1, NVT),
1334 DAG.getConstant(0, NVT));
1335 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1340 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1341 SDValue &Lo, SDValue &Hi) {
1342 // Expand the subcomponents.
1343 SDValue LHSL, LHSH, RHSL, RHSH;
1344 DebugLoc dl = N->getDebugLoc();
1345 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1346 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1347 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1348 SDValue LoOps[2] = { LHSL, RHSL };
1349 SDValue HiOps[3] = { LHSH, RHSH };
1351 if (N->getOpcode() == ISD::ADDC) {
1352 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1353 HiOps[2] = Lo.getValue(1);
1354 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1356 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1357 HiOps[2] = Lo.getValue(1);
1358 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1361 // Legalized the flag result - switch anything that used the old flag to
1363 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1366 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1367 SDValue &Lo, SDValue &Hi) {
1368 // Expand the subcomponents.
1369 SDValue LHSL, LHSH, RHSL, RHSH;
1370 DebugLoc dl = N->getDebugLoc();
1371 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1372 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1373 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1374 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1375 SDValue HiOps[3] = { LHSH, RHSH };
1377 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1378 HiOps[2] = Lo.getValue(1);
1379 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1381 // Legalized the flag result - switch anything that used the old flag to
1383 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1386 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1387 SDValue &Lo, SDValue &Hi) {
1388 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1389 DebugLoc dl = N->getDebugLoc();
1390 SDValue Op = N->getOperand(0);
1391 if (Op.getValueType().bitsLE(NVT)) {
1392 // The low part is any extension of the input (which degenerates to a copy).
1393 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1394 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1396 // For example, extension of an i48 to an i64. The operand type necessarily
1397 // promotes to the result type, so will end up being expanded too.
1398 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1399 "Only know how to promote this result!");
1400 SDValue Res = GetPromotedInteger(Op);
1401 assert(Res.getValueType() == N->getValueType(0) &&
1402 "Operand over promoted?");
1403 // Split the promoted operand. This will simplify when it is expanded.
1404 SplitInteger(Res, Lo, Hi);
1408 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1409 SDValue &Lo, SDValue &Hi) {
1410 DebugLoc dl = N->getDebugLoc();
1411 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1412 MVT NVT = Lo.getValueType();
1413 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1414 unsigned NVTBits = NVT.getSizeInBits();
1415 unsigned EVTBits = EVT.getSizeInBits();
1417 if (NVTBits < EVTBits) {
1418 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1419 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1421 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1422 // The high part replicates the sign bit of Lo, make it explicit.
1423 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1424 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1428 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1429 SDValue &Lo, SDValue &Hi) {
1430 DebugLoc dl = N->getDebugLoc();
1431 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1432 MVT NVT = Lo.getValueType();
1433 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1434 unsigned NVTBits = NVT.getSizeInBits();
1435 unsigned EVTBits = EVT.getSizeInBits();
1437 if (NVTBits < EVTBits) {
1438 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1439 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1441 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1442 // The high part must be zero, make it explicit.
1443 Hi = DAG.getConstant(0, NVT);
1447 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1448 SDValue &Lo, SDValue &Hi) {
1449 DebugLoc dl = N->getDebugLoc();
1450 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1451 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1452 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1455 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1456 SDValue &Lo, SDValue &Hi) {
1457 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1458 unsigned NBitWidth = NVT.getSizeInBits();
1459 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1460 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1461 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1464 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1465 SDValue &Lo, SDValue &Hi) {
1466 DebugLoc dl = N->getDebugLoc();
1467 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1468 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1469 MVT NVT = Lo.getValueType();
1471 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1472 DAG.getConstant(0, NVT), ISD::SETNE);
1474 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1475 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1477 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1478 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1479 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1480 Hi = DAG.getConstant(0, NVT);
1483 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1484 SDValue &Lo, SDValue &Hi) {
1485 DebugLoc dl = N->getDebugLoc();
1486 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1487 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1488 MVT NVT = Lo.getValueType();
1489 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1490 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1491 Hi = DAG.getConstant(0, NVT);
1494 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1495 SDValue &Lo, SDValue &Hi) {
1496 DebugLoc dl = N->getDebugLoc();
1497 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1498 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1499 MVT NVT = Lo.getValueType();
1501 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1502 DAG.getConstant(0, NVT), ISD::SETNE);
1504 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1505 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1507 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1508 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1509 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1510 Hi = DAG.getConstant(0, NVT);
1513 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1515 DebugLoc dl = N->getDebugLoc();
1516 MVT VT = N->getValueType(0);
1517 SDValue Op = N->getOperand(0);
1518 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1519 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1520 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1523 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1525 DebugLoc dl = N->getDebugLoc();
1526 MVT VT = N->getValueType(0);
1527 SDValue Op = N->getOperand(0);
1528 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1529 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1530 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1533 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1534 SDValue &Lo, SDValue &Hi) {
1535 if (ISD::isNormalLoad(N)) {
1536 ExpandRes_NormalLoad(N, Lo, Hi);
1540 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1542 MVT VT = N->getValueType(0);
1543 MVT NVT = TLI.getTypeToTransformTo(VT);
1544 SDValue Ch = N->getChain();
1545 SDValue Ptr = N->getBasePtr();
1546 ISD::LoadExtType ExtType = N->getExtensionType();
1547 int SVOffset = N->getSrcValueOffset();
1548 unsigned Alignment = N->getAlignment();
1549 bool isVolatile = N->isVolatile();
1550 DebugLoc dl = N->getDebugLoc();
1552 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1554 if (N->getMemoryVT().bitsLE(NVT)) {
1555 MVT EVT = N->getMemoryVT();
1557 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1558 EVT, isVolatile, Alignment);
1560 // Remember the chain.
1561 Ch = Lo.getValue(1);
1563 if (ExtType == ISD::SEXTLOAD) {
1564 // The high part is obtained by SRA'ing all but one of the bits of the
1566 unsigned LoSize = Lo.getValueType().getSizeInBits();
1567 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1568 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1569 } else if (ExtType == ISD::ZEXTLOAD) {
1570 // The high part is just a zero.
1571 Hi = DAG.getConstant(0, NVT);
1573 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1574 // The high part is undefined.
1575 Hi = DAG.getUNDEF(NVT);
1577 } else if (TLI.isLittleEndian()) {
1578 // Little-endian - low bits are at low addresses.
1579 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1580 isVolatile, Alignment);
1582 unsigned ExcessBits =
1583 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1584 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1586 // Increment the pointer to the other half.
1587 unsigned IncrementSize = NVT.getSizeInBits()/8;
1588 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1589 DAG.getIntPtrConstant(IncrementSize));
1590 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
1591 SVOffset+IncrementSize, NEVT,
1592 isVolatile, MinAlign(Alignment, IncrementSize));
1594 // Build a factor node to remember that this load is independent of the
1596 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1599 // Big-endian - high bits are at low addresses. Favor aligned loads at
1600 // the cost of some bit-fiddling.
1601 MVT EVT = N->getMemoryVT();
1602 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1603 unsigned IncrementSize = NVT.getSizeInBits()/8;
1604 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1606 // Load both the high bits and maybe some of the low bits.
1607 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1608 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1609 isVolatile, Alignment);
1611 // Increment the pointer to the other half.
1612 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1613 DAG.getIntPtrConstant(IncrementSize));
1614 // Load the rest of the low bits.
1615 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
1616 SVOffset+IncrementSize,
1617 MVT::getIntegerVT(ExcessBits),
1618 isVolatile, MinAlign(Alignment, IncrementSize));
1620 // Build a factor node to remember that this load is independent of the
1622 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1625 if (ExcessBits < NVT.getSizeInBits()) {
1626 // Transfer low bits from the bottom of Hi to the top of Lo.
1627 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1628 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1629 DAG.getConstant(ExcessBits,
1630 TLI.getPointerTy())));
1631 // Move high bits to the right position in Hi.
1632 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1634 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1635 TLI.getPointerTy()));
1639 // Legalized the chain result - switch anything that used the old chain to
1641 ReplaceValueWith(SDValue(N, 1), Ch);
1644 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1645 SDValue &Lo, SDValue &Hi) {
1646 DebugLoc dl = N->getDebugLoc();
1647 SDValue LL, LH, RL, RH;
1648 GetExpandedInteger(N->getOperand(0), LL, LH);
1649 GetExpandedInteger(N->getOperand(1), RL, RH);
1650 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1651 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1654 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1655 SDValue &Lo, SDValue &Hi) {
1656 MVT VT = N->getValueType(0);
1657 MVT NVT = TLI.getTypeToTransformTo(VT);
1658 DebugLoc dl = N->getDebugLoc();
1660 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1661 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1662 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1663 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1664 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1665 SDValue LL, LH, RL, RH;
1666 GetExpandedInteger(N->getOperand(0), LL, LH);
1667 GetExpandedInteger(N->getOperand(1), RL, RH);
1668 unsigned OuterBitSize = VT.getSizeInBits();
1669 unsigned InnerBitSize = NVT.getSizeInBits();
1670 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1671 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1673 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1674 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1675 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1676 // The inputs are both zero-extended.
1678 // We can emit a umul_lohi.
1679 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1680 Hi = SDValue(Lo.getNode(), 1);
1684 // We can emit a mulhu+mul.
1685 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1686 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1690 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1691 // The input values are both sign-extended.
1693 // We can emit a smul_lohi.
1694 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1695 Hi = SDValue(Lo.getNode(), 1);
1699 // We can emit a mulhs+mul.
1700 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1701 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1706 // Lo,Hi = umul LHS, RHS.
1707 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1708 DAG.getVTList(NVT, NVT), LL, RL);
1710 Hi = UMulLOHI.getValue(1);
1711 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1712 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1713 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1714 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1718 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1719 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1720 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1721 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1722 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1723 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1728 // If nothing else, we can make a libcall.
1729 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1731 LC = RTLIB::MUL_I16;
1732 else if (VT == MVT::i32)
1733 LC = RTLIB::MUL_I32;
1734 else if (VT == MVT::i64)
1735 LC = RTLIB::MUL_I64;
1736 else if (VT == MVT::i128)
1737 LC = RTLIB::MUL_I128;
1738 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1740 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1741 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1744 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1745 SDValue &Lo, SDValue &Hi) {
1746 MVT VT = N->getValueType(0);
1747 DebugLoc dl = N->getDebugLoc();
1749 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1751 LC = RTLIB::SDIV_I32;
1752 else if (VT == MVT::i64)
1753 LC = RTLIB::SDIV_I64;
1754 else if (VT == MVT::i128)
1755 LC = RTLIB::SDIV_I128;
1756 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1758 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1759 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1762 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1763 SDValue &Lo, SDValue &Hi) {
1764 MVT VT = N->getValueType(0);
1765 DebugLoc dl = N->getDebugLoc();
1767 // If we can emit an efficient shift operation, do so now. Check to see if
1768 // the RHS is a constant.
1769 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1770 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1772 // If we can determine that the high bit of the shift is zero or one, even if
1773 // the low bits are variable, emit this shift in an optimized form.
1774 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1777 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1779 if (N->getOpcode() == ISD::SHL) {
1780 PartsOpc = ISD::SHL_PARTS;
1781 } else if (N->getOpcode() == ISD::SRL) {
1782 PartsOpc = ISD::SRL_PARTS;
1784 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1785 PartsOpc = ISD::SRA_PARTS;
1788 // Next check to see if the target supports this SHL_PARTS operation or if it
1789 // will custom expand it.
1790 MVT NVT = TLI.getTypeToTransformTo(VT);
1791 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1792 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1793 Action == TargetLowering::Custom) {
1794 // Expand the subcomponents.
1796 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1798 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1799 MVT VT = LHSL.getValueType();
1800 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1801 Hi = Lo.getValue(1);
1805 // Otherwise, emit a libcall.
1806 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1808 if (N->getOpcode() == ISD::SHL) {
1809 isSigned = false; /*sign irrelevant*/
1811 LC = RTLIB::SHL_I16;
1812 else if (VT == MVT::i32)
1813 LC = RTLIB::SHL_I32;
1814 else if (VT == MVT::i64)
1815 LC = RTLIB::SHL_I64;
1816 else if (VT == MVT::i128)
1817 LC = RTLIB::SHL_I128;
1818 } else if (N->getOpcode() == ISD::SRL) {
1821 LC = RTLIB::SRL_I16;
1822 else if (VT == MVT::i32)
1823 LC = RTLIB::SRL_I32;
1824 else if (VT == MVT::i64)
1825 LC = RTLIB::SRL_I64;
1826 else if (VT == MVT::i128)
1827 LC = RTLIB::SRL_I128;
1829 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1832 LC = RTLIB::SRA_I16;
1833 else if (VT == MVT::i32)
1834 LC = RTLIB::SRA_I32;
1835 else if (VT == MVT::i64)
1836 LC = RTLIB::SRA_I64;
1837 else if (VT == MVT::i128)
1838 LC = RTLIB::SRA_I128;
1841 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
1842 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1843 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1847 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
1848 assert(0 && "Unsupported shift!");
1851 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1852 SDValue &Lo, SDValue &Hi) {
1853 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1854 DebugLoc dl = N->getDebugLoc();
1855 SDValue Op = N->getOperand(0);
1856 if (Op.getValueType().bitsLE(NVT)) {
1857 // The low part is sign extension of the input (degenerates to a copy).
1858 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1859 // The high part is obtained by SRA'ing all but one of the bits of low part.
1860 unsigned LoSize = NVT.getSizeInBits();
1861 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1862 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1864 // For example, extension of an i48 to an i64. The operand type necessarily
1865 // promotes to the result type, so will end up being expanded too.
1866 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1867 "Only know how to promote this result!");
1868 SDValue Res = GetPromotedInteger(Op);
1869 assert(Res.getValueType() == N->getValueType(0) &&
1870 "Operand over promoted?");
1871 // Split the promoted operand. This will simplify when it is expanded.
1872 SplitInteger(Res, Lo, Hi);
1873 unsigned ExcessBits =
1874 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1875 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1876 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1880 void DAGTypeLegalizer::
1881 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1882 DebugLoc dl = N->getDebugLoc();
1883 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1884 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1886 if (EVT.bitsLE(Lo.getValueType())) {
1887 // sext_inreg the low part if needed.
1888 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1891 // The high part gets the sign extension from the lo-part. This handles
1892 // things like sextinreg V:i64 from i8.
1893 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1894 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1895 TLI.getPointerTy()));
1897 // For example, extension of an i48 to an i64. Leave the low part alone,
1898 // sext_inreg the high part.
1899 unsigned ExcessBits =
1900 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1901 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1902 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1906 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1907 SDValue &Lo, SDValue &Hi) {
1908 MVT VT = N->getValueType(0);
1909 DebugLoc dl = N->getDebugLoc();
1911 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1913 LC = RTLIB::SREM_I32;
1914 else if (VT == MVT::i64)
1915 LC = RTLIB::SREM_I64;
1916 else if (VT == MVT::i128)
1917 LC = RTLIB::SREM_I128;
1918 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1920 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1921 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1924 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1925 SDValue &Lo, SDValue &Hi) {
1926 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1927 DebugLoc dl = N->getDebugLoc();
1928 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1929 Hi = DAG.getNode(ISD::SRL, dl,
1930 N->getOperand(0).getValueType(), N->getOperand(0),
1931 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1932 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1935 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1936 SDValue &Lo, SDValue &Hi) {
1937 MVT VT = N->getValueType(0);
1938 DebugLoc dl = N->getDebugLoc();
1940 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1942 LC = RTLIB::UDIV_I32;
1943 else if (VT == MVT::i64)
1944 LC = RTLIB::UDIV_I64;
1945 else if (VT == MVT::i128)
1946 LC = RTLIB::UDIV_I128;
1947 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1949 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1950 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1953 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1954 SDValue &Lo, SDValue &Hi) {
1955 MVT VT = N->getValueType(0);
1956 DebugLoc dl = N->getDebugLoc();
1958 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1960 LC = RTLIB::UREM_I32;
1961 else if (VT == MVT::i64)
1962 LC = RTLIB::UREM_I64;
1963 else if (VT == MVT::i128)
1964 LC = RTLIB::UREM_I128;
1965 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1967 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1968 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1971 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1972 SDValue &Lo, SDValue &Hi) {
1973 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1974 DebugLoc dl = N->getDebugLoc();
1975 SDValue Op = N->getOperand(0);
1976 if (Op.getValueType().bitsLE(NVT)) {
1977 // The low part is zero extension of the input (degenerates to a copy).
1978 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
1979 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1981 // For example, extension of an i48 to an i64. The operand type necessarily
1982 // promotes to the result type, so will end up being expanded too.
1983 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1984 "Only know how to promote this result!");
1985 SDValue Res = GetPromotedInteger(Op);
1986 assert(Res.getValueType() == N->getValueType(0) &&
1987 "Operand over promoted?");
1988 // Split the promoted operand. This will simplify when it is expanded.
1989 SplitInteger(Res, Lo, Hi);
1990 unsigned ExcessBits =
1991 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1992 Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits));
1997 //===----------------------------------------------------------------------===//
1998 // Integer Operand Expansion
1999 //===----------------------------------------------------------------------===//
2001 /// ExpandIntegerOperand - This method is called when the specified operand of
2002 /// the specified node is found to need expansion. At this point, all of the
2003 /// result types of the node are known to be legal, but other operands of the
2004 /// node may need promotion or expansion as well as the specified one.
2005 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2006 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
2007 SDValue Res = SDValue();
2009 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false))
2012 switch (N->getOpcode()) {
2015 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
2016 N->dump(&DAG); cerr << "\n";
2018 assert(0 && "Do not know how to expand this operator's operand!");
2021 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
2022 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2023 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2024 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2025 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2026 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2027 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2028 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2029 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2030 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2031 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2032 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2038 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2041 // If the result is null, the sub-method took care of registering results etc.
2042 if (!Res.getNode()) return false;
2044 // If the result is N, the sub-method updated N in place. Tell the legalizer
2046 if (Res.getNode() == N)
2049 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2050 "Invalid operand expansion");
2052 ReplaceValueWith(SDValue(N, 0), Res);
2056 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2057 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2058 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2060 ISD::CondCode &CCCode,
2062 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2063 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2064 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2066 MVT VT = NewLHS.getValueType();
2068 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2069 if (RHSLo == RHSHi) {
2070 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2071 if (RHSCST->isAllOnesValue()) {
2072 // Equality comparison to -1.
2073 NewLHS = DAG.getNode(ISD::AND, dl,
2074 LHSLo.getValueType(), LHSLo, LHSHi);
2081 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2082 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2083 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2084 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2088 // If this is a comparison of the sign bit, just look at the top part.
2090 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2091 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2092 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2098 // FIXME: This generated code sucks.
2099 ISD::CondCode LowCC;
2101 default: assert(0 && "Unknown integer setcc!");
2103 case ISD::SETULT: LowCC = ISD::SETULT; break;
2105 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2107 case ISD::SETULE: LowCC = ISD::SETULE; break;
2109 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2112 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2113 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2114 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2116 // NOTE: on targets without efficient SELECT of bools, we can always use
2117 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2118 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
2120 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2121 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2122 if (!Tmp1.getNode())
2123 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2124 LHSLo, RHSLo, LowCC);
2125 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2126 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2127 if (!Tmp2.getNode())
2128 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2129 TLI.getSetCCResultType(LHSHi.getValueType()),
2130 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2132 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2133 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2134 if ((Tmp1C && Tmp1C->isNullValue()) ||
2135 (Tmp2C && Tmp2C->isNullValue() &&
2136 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2137 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2138 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2139 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2140 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2141 // low part is known false, returns high part.
2142 // For LE / GE, if high part is known false, ignore the low part.
2143 // For LT / GT, if high part is known true, ignore the low part.
2149 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2150 LHSHi, RHSHi, ISD::SETEQ, false,
2151 DagCombineInfo, dl);
2152 if (!NewLHS.getNode())
2153 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2154 LHSHi, RHSHi, ISD::SETEQ);
2155 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2156 NewLHS, Tmp1, Tmp2);
2160 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2161 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2162 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2163 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2165 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2166 // against zero to select between true and false values.
2167 if (NewRHS.getNode() == 0) {
2168 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2169 CCCode = ISD::SETNE;
2172 // Update N to have the operands specified.
2173 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2174 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2178 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2179 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2180 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2181 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2183 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2184 // against zero to select between true and false values.
2185 if (NewRHS.getNode() == 0) {
2186 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2187 CCCode = ISD::SETNE;
2190 // Update N to have the operands specified.
2191 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2192 N->getOperand(2), N->getOperand(3),
2193 DAG.getCondCode(CCCode));
2196 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2197 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2198 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2199 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2201 // If ExpandSetCCOperands returned a scalar, use it.
2202 if (NewRHS.getNode() == 0) {
2203 assert(NewLHS.getValueType() == N->getValueType(0) &&
2204 "Unexpected setcc expansion!");
2208 // Otherwise, update N to have the operands specified.
2209 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2210 DAG.getCondCode(CCCode));
2213 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2214 // The value being shifted is legal, but the shift amount is too big.
2215 // It follows that either the result of the shift is undefined, or the
2216 // upper half of the shift amount is zero. Just use the lower half.
2218 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2219 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo);
2222 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2223 SDValue Op = N->getOperand(0);
2224 MVT DstVT = N->getValueType(0);
2225 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2226 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2227 "Don't know how to expand this SINT_TO_FP!");
2228 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2231 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2232 if (ISD::isNormalStore(N))
2233 return ExpandOp_NormalStore(N, OpNo);
2235 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2236 assert(OpNo == 1 && "Can only expand the stored value so far");
2238 MVT VT = N->getOperand(1).getValueType();
2239 MVT NVT = TLI.getTypeToTransformTo(VT);
2240 SDValue Ch = N->getChain();
2241 SDValue Ptr = N->getBasePtr();
2242 int SVOffset = N->getSrcValueOffset();
2243 unsigned Alignment = N->getAlignment();
2244 bool isVolatile = N->isVolatile();
2245 DebugLoc dl = N->getDebugLoc();
2248 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2250 if (N->getMemoryVT().bitsLE(NVT)) {
2251 GetExpandedInteger(N->getValue(), Lo, Hi);
2252 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2253 N->getMemoryVT(), isVolatile, Alignment);
2254 } else if (TLI.isLittleEndian()) {
2255 // Little-endian - low bits are at low addresses.
2256 GetExpandedInteger(N->getValue(), Lo, Hi);
2258 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2259 isVolatile, Alignment);
2261 unsigned ExcessBits =
2262 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2263 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2265 // Increment the pointer to the other half.
2266 unsigned IncrementSize = NVT.getSizeInBits()/8;
2267 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2268 DAG.getIntPtrConstant(IncrementSize));
2269 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2270 SVOffset+IncrementSize, NEVT,
2271 isVolatile, MinAlign(Alignment, IncrementSize));
2272 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2274 // Big-endian - high bits are at low addresses. Favor aligned stores at
2275 // the cost of some bit-fiddling.
2276 GetExpandedInteger(N->getValue(), Lo, Hi);
2278 MVT EVT = N->getMemoryVT();
2279 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2280 unsigned IncrementSize = NVT.getSizeInBits()/8;
2281 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2282 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2284 if (ExcessBits < NVT.getSizeInBits()) {
2285 // Transfer high bits from the top of Lo to the bottom of Hi.
2286 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2287 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2288 TLI.getPointerTy()));
2289 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2290 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2291 DAG.getConstant(ExcessBits,
2292 TLI.getPointerTy())));
2295 // Store both the high bits and maybe some of the low bits.
2296 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2297 SVOffset, HiVT, isVolatile, Alignment);
2299 // Increment the pointer to the other half.
2300 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2301 DAG.getIntPtrConstant(IncrementSize));
2302 // Store the lowest ExcessBits bits in the second half.
2303 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2304 SVOffset+IncrementSize,
2305 MVT::getIntegerVT(ExcessBits),
2306 isVolatile, MinAlign(Alignment, IncrementSize));
2307 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2311 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2313 GetExpandedInteger(N->getOperand(0), InL, InH);
2314 // Just truncate the low part of the source.
2315 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2318 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2319 SDValue Op = N->getOperand(0);
2320 MVT SrcVT = Op.getValueType();
2321 MVT DstVT = N->getValueType(0);
2322 DebugLoc dl = N->getDebugLoc();
2324 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2325 // Do a signed conversion then adjust the result.
2326 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2327 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2329 // The result of the signed conversion needs adjusting if the 'sign bit' of
2330 // the incoming integer was set. To handle this, we dynamically test to see
2331 // if it is set, and, if so, add a fudge factor.
2333 const uint64_t F32TwoE32 = 0x4F800000ULL;
2334 const uint64_t F32TwoE64 = 0x5F800000ULL;
2335 const uint64_t F32TwoE128 = 0x7F800000ULL;
2338 if (SrcVT == MVT::i32)
2339 FF = APInt(32, F32TwoE32);
2340 else if (SrcVT == MVT::i64)
2341 FF = APInt(32, F32TwoE64);
2342 else if (SrcVT == MVT::i128)
2343 FF = APInt(32, F32TwoE128);
2345 assert(false && "Unsupported UINT_TO_FP!");
2347 // Check whether the sign bit is set.
2349 GetExpandedInteger(Op, Lo, Hi);
2350 SDValue SignSet = DAG.getSetCC(dl,
2351 TLI.getSetCCResultType(Hi.getValueType()),
2352 Hi, DAG.getConstant(0, Hi.getValueType()),
2355 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2356 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2357 TLI.getPointerTy());
2359 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2360 SDValue Zero = DAG.getIntPtrConstant(0);
2361 SDValue Four = DAG.getIntPtrConstant(4);
2362 if (TLI.isBigEndian()) std::swap(Zero, Four);
2363 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2365 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2366 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2367 Alignment = std::min(Alignment, 4u);
2369 // Load the value out, extending it from f32 to the destination float type.
2370 // FIXME: Avoid the extend by constructing the right constant pool?
2371 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2372 FudgePtr, NULL, 0, MVT::f32,
2374 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2377 // Otherwise, use a libcall.
2378 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2379 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2380 "Don't know how to expand this UINT_TO_FP!");
2381 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);