1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in multiple registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/Constants.h"
25 //===----------------------------------------------------------------------===//
26 // Integer Result Promotion
27 //===----------------------------------------------------------------------===//
29 /// PromoteIntegerResult - This method is called when a result of a node is
30 /// found to be in need of promotion to a larger type. At this point, the node
31 /// may also have invalid operands or may have other results that need
32 /// expansion, we just know that (at least) one result needs promotion.
33 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
35 SDOperand Result = SDOperand();
37 switch (N->getOpcode()) {
40 cerr << "PromoteIntegerResult #" << ResNo << ": ";
41 N->dump(&DAG); cerr << "\n";
43 assert(0 && "Do not know how to promote this operator!");
45 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
46 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
48 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
49 case ISD::SIGN_EXTEND:
50 case ISD::ZERO_EXTEND:
51 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
52 case ISD::FP_ROUND: Result = PromoteIntRes_FP_ROUND(N); break;
54 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
55 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
56 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
57 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
65 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
68 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
71 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
73 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
74 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
77 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
78 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
80 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
81 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
82 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
84 case ISD::EXTRACT_VECTOR_ELT:
85 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N);
89 // If Result is null, the sub-method took care of registering the result.
91 SetPromotedInteger(SDOperand(N, ResNo), Result);
94 SDOperand DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
95 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
98 SDOperand DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
99 MVT VT = N->getValueType(0);
100 // Zero extend things like i1, sign extend everything else. It shouldn't
101 // matter in theory which one we pick, but this tends to give better code?
102 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
103 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
105 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
109 SDOperand DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
112 switch (getTypeAction(N->getOperand(0).getValueType())) {
113 default: assert(0 && "Unknown type action!");
116 Res = N->getOperand(0);
119 Res = GetPromotedInteger(N->getOperand(0));
123 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
124 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
125 "Truncation doesn't make sense!");
126 if (Res.getValueType() == NVT)
129 // Truncate to NVT instead of VT
130 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
133 SDOperand DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
134 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
136 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
137 SDOperand Res = GetPromotedInteger(N->getOperand(0));
138 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
139 "Extension doesn't make sense!");
141 // If the result and operand types are the same after promotion, simplify
142 // to an in-register extension.
143 if (NVT == Res.getValueType()) {
144 // The high bits are not guaranteed to be anything. Insert an extend.
145 if (N->getOpcode() == ISD::SIGN_EXTEND)
146 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
147 DAG.getValueType(N->getOperand(0).getValueType()));
148 if (N->getOpcode() == ISD::ZERO_EXTEND)
149 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
150 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
155 // Otherwise, just extend the original operand all the way to the larger type.
156 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
159 SDOperand DAGTypeLegalizer::PromoteIntRes_FP_ROUND(SDNode *N) {
160 // NOTE: Assumes input is legal.
161 if (N->getConstantOperandVal(1) == 0)
162 return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
163 N->getOperand(0), DAG.getValueType(N->getValueType(0)));
164 // If the precision discard isn't needed, just return the operand unrounded.
165 return N->getOperand(0);
168 SDOperand DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
169 unsigned NewOpc = N->getOpcode();
170 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
172 // If we're promoting a UINT to a larger size, check to see if the new node
173 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
174 // we can use that instead. This allows us to generate better code for
175 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
176 // legal, such as PowerPC.
177 if (N->getOpcode() == ISD::FP_TO_UINT) {
178 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
179 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
180 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
181 NewOpc = ISD::FP_TO_SINT;
184 return DAG.getNode(NewOpc, NVT, N->getOperand(0));
187 SDOperand DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
188 assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
189 && "SetCC type is not legal??");
190 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
191 N->getOperand(0), N->getOperand(1), N->getOperand(2));
194 SDOperand DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
195 // FIXME: Add support for indexed loads.
196 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
197 ISD::LoadExtType ExtType =
198 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
199 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
200 N->getSrcValue(), N->getSrcValueOffset(),
201 N->getMemoryVT(), N->isVolatile(),
204 // Legalized the chain result - switch anything that used the old chain to
206 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
210 SDOperand DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
211 // The pair element type may be legal, or may not promote to the same type as
212 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
213 return DAG.getNode(ISD::ANY_EXTEND,
214 TLI.getTypeToTransformTo(N->getValueType(0)),
215 JoinIntegers(N->getOperand(0), N->getOperand(1)));
218 SDOperand DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
219 SDOperand InOp = N->getOperand(0);
220 MVT InVT = InOp.getValueType();
221 MVT NInVT = TLI.getTypeToTransformTo(InVT);
222 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
224 switch (getTypeAction(InVT)) {
226 assert(false && "Unknown type action!");
231 if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
232 // The input promotes to the same size. Convert the promoted value.
233 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
236 // Promote the integer operand by hand.
237 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetPromotedFloat(InOp));
242 // Convert the element to an integer and promote it by hand.
243 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
244 BitConvertToInteger(GetScalarizedVector(InOp)));
246 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
247 // pieces of the input into integers and reassemble in the final type.
249 GetSplitVector(N->getOperand(0), Lo, Hi);
250 Lo = BitConvertToInteger(Lo);
251 Hi = BitConvertToInteger(Hi);
253 if (TLI.isBigEndian())
256 InOp = DAG.getNode(ISD::ANY_EXTEND,
257 MVT::getIntegerVT(OutVT.getSizeInBits()),
258 JoinIntegers(Lo, Hi));
259 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
262 // Otherwise, lower the bit-convert to a store/load from the stack, then
264 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
265 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val));
268 SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
269 // The input may have strange things in the top bits of the registers, but
270 // these operations don't care. They may have weird bits going out, but
271 // that too is okay if they are integer operations.
272 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
273 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
274 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
277 SDOperand DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
278 // Sign extend the input.
279 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
280 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
281 MVT VT = N->getValueType(0);
282 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
283 DAG.getValueType(VT));
284 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
285 DAG.getValueType(VT));
287 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
290 SDOperand DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
291 // Zero extend the input.
292 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
293 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
294 MVT VT = N->getValueType(0);
295 LHS = DAG.getZeroExtendInReg(LHS, VT);
296 RHS = DAG.getZeroExtendInReg(RHS, VT);
298 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
301 SDOperand DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
302 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
303 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
306 SDOperand DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
307 // The input value must be properly sign extended.
308 MVT VT = N->getValueType(0);
309 MVT NVT = TLI.getTypeToTransformTo(VT);
310 SDOperand Res = GetPromotedInteger(N->getOperand(0));
311 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
312 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
315 SDOperand DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
316 // The input value must be properly zero extended.
317 MVT VT = N->getValueType(0);
318 MVT NVT = TLI.getTypeToTransformTo(VT);
319 SDOperand Res = ZExtPromotedInteger(N->getOperand(0));
320 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
323 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
324 SDOperand LHS = GetPromotedInteger(N->getOperand(1));
325 SDOperand RHS = GetPromotedInteger(N->getOperand(2));
326 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
329 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
330 SDOperand LHS = GetPromotedInteger(N->getOperand(2));
331 SDOperand RHS = GetPromotedInteger(N->getOperand(3));
332 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
333 N->getOperand(1), LHS, RHS, N->getOperand(4));
336 SDOperand DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
337 SDOperand Op = GetPromotedInteger(N->getOperand(0));
338 MVT OVT = N->getValueType(0);
339 MVT NVT = Op.getValueType();
340 // Zero extend to the promoted type and do the count there.
341 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
342 // Subtract off the extra leading bits in the bigger type.
343 return DAG.getNode(ISD::SUB, NVT, Op,
344 DAG.getConstant(NVT.getSizeInBits() -
345 OVT.getSizeInBits(), NVT));
348 SDOperand DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
349 SDOperand Op = GetPromotedInteger(N->getOperand(0));
350 MVT OVT = N->getValueType(0);
351 MVT NVT = Op.getValueType();
352 // Zero extend to the promoted type and do the count there.
353 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
356 SDOperand DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
357 SDOperand Op = GetPromotedInteger(N->getOperand(0));
358 MVT OVT = N->getValueType(0);
359 MVT NVT = Op.getValueType();
360 // The count is the same in the promoted type except if the original
361 // value was zero. This can be handled by setting the bit just off
362 // the top of the original type.
363 Op = DAG.getNode(ISD::OR, NVT, Op,
364 // FIXME: Do this using an APINT constant.
365 DAG.getConstant(1UL << OVT.getSizeInBits(), NVT));
366 return DAG.getNode(ISD::CTTZ, NVT, Op);
369 SDOperand DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
370 MVT OldVT = N->getValueType(0);
371 SDOperand OldVec = N->getOperand(0);
372 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
375 assert(!isTypeLegal(OldVec.getValueType()) &&
376 "Legal one-element vector of a type needing promotion!");
377 // It is tempting to follow GetScalarizedVector by a call to
378 // GetPromotedInteger, but this would be wrong because the
379 // scalarized value may not yet have been processed.
380 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
381 GetScalarizedVector(OldVec));
384 // Convert to a vector half as long with an element type of twice the width,
385 // for example <4 x i16> -> <2 x i32>.
386 assert(!(OldElts & 1) && "Odd length vectors not supported!");
387 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
388 assert(OldVT.isSimple() && NewVT.isSimple());
390 SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
391 MVT::getVectorVT(NewVT, OldElts / 2),
394 // Extract the element at OldIdx / 2 from the new vector.
395 SDOperand OldIdx = N->getOperand(1);
396 SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
397 DAG.getConstant(1, TLI.getShiftAmountTy()));
398 SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
400 // Select the appropriate half of the element: Lo if OldIdx was even,
403 SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
404 DAG.getConstant(OldVT.getSizeInBits(),
405 TLI.getShiftAmountTy()));
406 if (TLI.isBigEndian())
409 SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
410 DAG.getConstant(1, TLI.getShiftAmountTy()));
411 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
414 //===----------------------------------------------------------------------===//
415 // Integer Operand Promotion
416 //===----------------------------------------------------------------------===//
418 /// PromoteIntegerOperand - This method is called when the specified operand of
419 /// the specified node is found to need promotion. At this point, all of the
420 /// result types of the node are known to be legal, but other operands of the
421 /// node may need promotion or expansion as well as the specified one.
422 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
423 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
425 switch (N->getOpcode()) {
428 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
429 N->dump(&DAG); cerr << "\n";
431 assert(0 && "Do not know how to promote this operator's operand!");
434 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
435 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
436 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
437 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
438 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break;
439 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break;
440 case ISD::SINT_TO_FP:
441 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break;
442 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
444 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
445 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
446 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
447 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
449 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
452 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
453 case ISD::INSERT_VECTOR_ELT:
454 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);
457 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
460 // If the result is null, the sub-method took care of registering results etc.
461 if (!Res.Val) return false;
462 // If the result is N, the sub-method updated N in place.
464 // Mark N as new and remark N and its operands. This allows us to correctly
465 // revisit N if it needs another step of promotion and allows us to visit
466 // any new operands to N.
471 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
472 "Invalid operand expansion");
474 ReplaceValueWith(SDOperand(N, 0), Res);
478 SDOperand DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
479 SDOperand Op = GetPromotedInteger(N->getOperand(0));
480 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
483 SDOperand DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
484 SDOperand Op = GetPromotedInteger(N->getOperand(0));
485 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
486 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
489 SDOperand DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
490 SDOperand Op = GetPromotedInteger(N->getOperand(0));
491 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
492 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
493 Op, DAG.getValueType(N->getOperand(0).getValueType()));
496 SDOperand DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
497 SDOperand Op = GetPromotedInteger(N->getOperand(0));
498 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
501 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
502 SDOperand Op = GetPromotedInteger(N->getOperand(0));
503 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
506 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
507 SDOperand Op = GetPromotedInteger(N->getOperand(0));
508 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
509 DAG.getIntPtrConstant(0));
512 SDOperand DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
513 SDOperand In = GetPromotedInteger(N->getOperand(0));
514 MVT OpVT = N->getOperand(0).getValueType();
515 if (N->getOpcode() == ISD::UINT_TO_FP)
516 In = DAG.getZeroExtendInReg(In, OpVT);
518 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
519 In, DAG.getValueType(OpVT));
521 return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
524 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
525 // Since the result type is legal, the operands must promote to it.
526 MVT OVT = N->getOperand(0).getValueType();
527 SDOperand Lo = GetPromotedInteger(N->getOperand(0));
528 SDOperand Hi = GetPromotedInteger(N->getOperand(1));
529 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
531 Lo = DAG.getZeroExtendInReg(Lo, OVT);
532 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
533 DAG.getConstant(OVT.getSizeInBits(),
534 TLI.getShiftAmountTy()));
535 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
538 SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
539 assert(OpNo == 0 && "Only know how to promote condition");
540 SDOperand Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition.
542 // The top bits of the promoted condition are not necessarily zero, ensure
543 // that the value is properly zero extended.
544 unsigned BitWidth = Cond.getValueSizeInBits();
545 if (!DAG.MaskedValueIsZero(Cond,
546 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
547 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
549 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
550 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
554 SDOperand DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
555 assert(OpNo == 1 && "only know how to promote condition");
556 SDOperand Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
558 // The top bits of the promoted condition are not necessarily zero, ensure
559 // that the value is properly zero extended.
560 unsigned BitWidth = Cond.getValueSizeInBits();
561 if (!DAG.MaskedValueIsZero(Cond,
562 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
563 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
565 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
566 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
570 SDOperand DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
571 assert(OpNo == 2 && "Don't know how to promote this operand");
573 SDOperand LHS = N->getOperand(2);
574 SDOperand RHS = N->getOperand(3);
575 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
577 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
579 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
580 N->getOperand(1), LHS, RHS, N->getOperand(4));
583 SDOperand DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
584 assert(OpNo == 0 && "Don't know how to promote this operand");
586 SDOperand LHS = N->getOperand(0);
587 SDOperand RHS = N->getOperand(1);
588 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
590 // The CC (#2) is always legal.
591 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
594 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
595 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
596 void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
597 ISD::CondCode CCCode) {
598 MVT VT = NewLHS.getValueType();
600 // Get the promoted values.
601 NewLHS = GetPromotedInteger(NewLHS);
602 NewRHS = GetPromotedInteger(NewRHS);
604 // If this is an FP compare, the operands have already been extended.
605 if (!NewLHS.getValueType().isInteger())
608 // Otherwise, we have to insert explicit sign or zero extends. Note
609 // that we could insert sign extends for ALL conditions, but zero extend
610 // is cheaper on many machines (an AND instead of two shifts), so prefer
613 default: assert(0 && "Unknown integer comparison!");
620 // ALL of these operations will work if we either sign or zero extend
621 // the operands (including the unsigned comparisons!). Zero extend is
622 // usually a simpler/cheaper operation, so prefer it.
623 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
624 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
630 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
631 DAG.getValueType(VT));
632 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
633 DAG.getValueType(VT));
638 SDOperand DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
639 // FIXME: Add support for indexed stores.
640 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
641 int SVOffset = N->getSrcValueOffset();
642 unsigned Alignment = N->getAlignment();
643 bool isVolatile = N->isVolatile();
645 SDOperand Val = GetPromotedInteger(N->getValue()); // Get promoted value.
647 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
649 // Truncate the value and store the result.
650 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
651 SVOffset, N->getMemoryVT(),
652 isVolatile, Alignment);
655 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
656 // The vector type is legal but the element type is not. This implies
657 // that the vector is a power-of-two in length and that the element
658 // type does not have a strange size (eg: it is not i1).
659 MVT VecVT = N->getValueType(0);
660 unsigned NumElts = VecVT.getVectorNumElements();
661 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
663 // Build a vector of half the length out of elements of twice the bitwidth.
664 // For example <4 x i16> -> <2 x i32>.
665 MVT OldVT = N->getOperand(0).getValueType();
666 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
667 assert(OldVT.isSimple() && NewVT.isSimple());
669 std::vector<SDOperand> NewElts;
670 NewElts.reserve(NumElts/2);
672 for (unsigned i = 0; i < NumElts; i += 2) {
673 // Combine two successive elements into one promoted element.
674 SDOperand Lo = N->getOperand(i);
675 SDOperand Hi = N->getOperand(i+1);
676 if (TLI.isBigEndian())
678 NewElts.push_back(JoinIntegers(Lo, Hi));
681 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
682 MVT::getVectorVT(NewVT, NewElts.size()),
683 &NewElts[0], NewElts.size());
685 // Convert the new vector to the old vector type.
686 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
689 SDOperand DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
692 // Promote the inserted value. This is valid because the type does not
693 // have to match the vector element type.
695 // Check that any extra bits introduced will be truncated away.
696 assert(N->getOperand(1).getValueType().getSizeInBits() >=
697 N->getValueType(0).getVectorElementType().getSizeInBits() &&
698 "Type of inserted value narrower than vector element type!");
699 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
700 GetPromotedInteger(N->getOperand(1)),
704 assert(OpNo == 2 && "Different operand and result vector types?");
706 // Promote the index.
707 SDOperand Idx = N->getOperand(2);
708 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType());
709 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
710 N->getOperand(1), Idx);
713 SDOperand DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
715 NewOps[0] = N->getOperand(0);
716 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
717 SDOperand Flag = GetPromotedInteger(N->getOperand(i));
718 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
720 return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps,
721 array_lengthof(NewOps));
725 //===----------------------------------------------------------------------===//
726 // Integer Result Expansion
727 //===----------------------------------------------------------------------===//
729 /// ExpandIntegerResult - This method is called when the specified result of the
730 /// specified node is found to need expansion. At this point, the node may also
731 /// have invalid operands or may have other results that need promotion, we just
732 /// know that (at least) one result needs expansion.
733 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
734 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
736 Lo = Hi = SDOperand();
738 // See if the target wants to custom expand this node.
739 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
740 TargetLowering::Custom) {
741 // If the target wants to, allow it to lower this itself.
742 if (SDNode *P = TLI.ExpandOperationResult(N, DAG)) {
743 // Everything that once used N now uses P. We are guaranteed that the
744 // result value types of N and the result value types of P match.
745 ReplaceNodeWith(N, P);
750 switch (N->getOpcode()) {
753 cerr << "ExpandIntegerResult #" << ResNo << ": ";
754 N->dump(&DAG); cerr << "\n";
756 assert(0&&"Do not know how to expand the result of this operator!");
759 case ISD::UNDEF: ExpandIntRes_UNDEF(N, Lo, Hi); break;
760 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
761 case ISD::BUILD_PAIR: ExpandIntRes_BUILD_PAIR(N, Lo, Hi); break;
762 case ISD::MERGE_VALUES: ExpandIntRes_MERGE_VALUES(N, Lo, Hi); break;
763 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
764 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
765 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
766 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
767 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
768 case ISD::BIT_CONVERT: ExpandIntRes_BIT_CONVERT(N, Lo, Hi); break;
769 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
770 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
771 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
772 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
776 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
777 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
779 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
781 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
783 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
784 case ISD::SELECT: ExpandIntRes_SELECT(N, Lo, Hi); break;
785 case ISD::SELECT_CC: ExpandIntRes_SELECT_CC(N, Lo, Hi); break;
786 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
787 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
788 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
789 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
790 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
793 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
795 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
796 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
797 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
799 case ISD::EXTRACT_VECTOR_ELT:
800 ExpandIntRes_EXTRACT_VECTOR_ELT(N, Lo, Hi);
804 // If Lo/Hi is null, the sub-method took care of registering results etc.
806 SetExpandedInteger(SDOperand(N, ResNo), Lo, Hi);
809 void DAGTypeLegalizer::ExpandIntRes_UNDEF(SDNode *N,
810 SDOperand &Lo, SDOperand &Hi) {
811 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
812 Lo = Hi = DAG.getNode(ISD::UNDEF, NVT);
815 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
816 SDOperand &Lo, SDOperand &Hi) {
817 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
818 unsigned NBitWidth = NVT.getSizeInBits();
819 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
820 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
821 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
824 void DAGTypeLegalizer::ExpandIntRes_BUILD_PAIR(SDNode *N,
825 SDOperand &Lo, SDOperand &Hi) {
826 // Return the operands.
827 Lo = N->getOperand(0);
828 Hi = N->getOperand(1);
831 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N,
832 SDOperand &Lo, SDOperand &Hi) {
833 // A MERGE_VALUES node can produce any number of values. We know that the
834 // first illegal one needs to be expanded into Lo/Hi.
837 // The string of legal results gets turns into the input operands, which have
839 for (i = 0; isTypeLegal(N->getValueType(i)); ++i)
840 ReplaceValueWith(SDOperand(N, i), SDOperand(N->getOperand(i)));
842 // The first illegal result must be the one that needs to be expanded.
843 GetExpandedInteger(N->getOperand(i), Lo, Hi);
845 // Legalize the rest of the results into the input operands whether they are
847 unsigned e = N->getNumValues();
848 for (++i; i != e; ++i)
849 ReplaceValueWith(SDOperand(N, i), SDOperand(N->getOperand(i)));
852 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
853 SDOperand &Lo, SDOperand &Hi) {
854 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
855 SDOperand Op = N->getOperand(0);
856 if (Op.getValueType().bitsLE(NVT)) {
857 // The low part is any extension of the input (which degenerates to a copy).
858 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
859 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
861 // For example, extension of an i48 to an i64. The operand type necessarily
862 // promotes to the result type, so will end up being expanded too.
863 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
864 "Only know how to promote this result!");
865 SDOperand Res = GetPromotedInteger(Op);
866 assert(Res.getValueType() == N->getValueType(0) &&
867 "Operand over promoted?");
868 // Split the promoted operand. This will simplify when it is expanded.
869 SplitInteger(Res, Lo, Hi);
873 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
874 SDOperand &Lo, SDOperand &Hi) {
875 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
876 SDOperand Op = N->getOperand(0);
877 if (Op.getValueType().bitsLE(NVT)) {
878 // The low part is zero extension of the input (which degenerates to a copy).
879 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
880 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
882 // For example, extension of an i48 to an i64. The operand type necessarily
883 // promotes to the result type, so will end up being expanded too.
884 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
885 "Only know how to promote this result!");
886 SDOperand Res = GetPromotedInteger(Op);
887 assert(Res.getValueType() == N->getValueType(0) &&
888 "Operand over promoted?");
889 // Split the promoted operand. This will simplify when it is expanded.
890 SplitInteger(Res, Lo, Hi);
891 unsigned ExcessBits =
892 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
893 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
897 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
898 SDOperand &Lo, SDOperand &Hi) {
899 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
900 SDOperand Op = N->getOperand(0);
901 if (Op.getValueType().bitsLE(NVT)) {
902 // The low part is sign extension of the input (which degenerates to a copy).
903 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
904 // The high part is obtained by SRA'ing all but one of the bits of low part.
905 unsigned LoSize = NVT.getSizeInBits();
906 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
907 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
909 // For example, extension of an i48 to an i64. The operand type necessarily
910 // promotes to the result type, so will end up being expanded too.
911 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
912 "Only know how to promote this result!");
913 SDOperand Res = GetPromotedInteger(Op);
914 assert(Res.getValueType() == N->getValueType(0) &&
915 "Operand over promoted?");
916 // Split the promoted operand. This will simplify when it is expanded.
917 SplitInteger(Res, Lo, Hi);
918 unsigned ExcessBits =
919 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
920 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
921 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
925 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
926 SDOperand &Lo, SDOperand &Hi) {
927 GetExpandedInteger(N->getOperand(0), Lo, Hi);
928 MVT NVT = Lo.getValueType();
929 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
930 unsigned NVTBits = NVT.getSizeInBits();
931 unsigned EVTBits = EVT.getSizeInBits();
933 if (NVTBits < EVTBits) {
934 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
935 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
937 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
938 // The high part must be zero, make it explicit.
939 Hi = DAG.getConstant(0, NVT);
943 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
944 SDOperand &Lo, SDOperand &Hi) {
945 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
946 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
947 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
948 DAG.getConstant(NVT.getSizeInBits(),
949 TLI.getShiftAmountTy()));
950 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
953 void DAGTypeLegalizer::ExpandIntRes_BIT_CONVERT(SDNode *N,
954 SDOperand &Lo, SDOperand &Hi) {
955 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
956 SDOperand InOp = N->getOperand(0);
957 MVT InVT = InOp.getValueType();
959 // Handle some special cases efficiently.
960 switch (getTypeAction(InVT)) {
962 assert(false && "Unknown type action!");
967 // Convert the integer operand instead.
968 SplitInteger(GetPromotedFloat(InOp), Lo, Hi);
969 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Lo);
970 Hi = DAG.getNode(ISD::BIT_CONVERT, NVT, Hi);
973 // Convert the expanded pieces of the input.
974 GetExpandedInteger(InOp, Lo, Hi);
975 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Lo);
976 Hi = DAG.getNode(ISD::BIT_CONVERT, NVT, Hi);
979 // Convert the expanded pieces of the input.
980 GetExpandedFloat(InOp, Lo, Hi);
981 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Lo);
982 Hi = DAG.getNode(ISD::BIT_CONVERT, NVT, Hi);
985 // Convert the split parts of the input if it was split in two.
986 GetSplitVector(InOp, Lo, Hi);
987 if (Lo.getValueType() == Hi.getValueType()) {
988 if (TLI.isBigEndian())
990 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Lo);
991 Hi = DAG.getNode(ISD::BIT_CONVERT, NVT, Hi);
996 // Convert the element instead.
997 SplitInteger(BitConvertToInteger(GetScalarizedVector(InOp)), Lo, Hi);
998 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Lo);
999 Hi = DAG.getNode(ISD::BIT_CONVERT, NVT, Hi);
1003 // Lower the bit-convert to a store/load from the stack, then expand the load.
1004 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
1005 ExpandIntRes_LOAD(cast<LoadSDNode>(Op.Val), Lo, Hi);
1008 void DAGTypeLegalizer::
1009 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
1010 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1011 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1013 if (EVT.bitsLE(Lo.getValueType())) {
1014 // sext_inreg the low part if needed.
1015 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
1018 // The high part gets the sign extension from the lo-part. This handles
1019 // things like sextinreg V:i64 from i8.
1020 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
1021 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1022 TLI.getShiftAmountTy()));
1024 // For example, extension of an i48 to an i64. Leave the low part alone,
1025 // sext_inreg the high part.
1026 unsigned ExcessBits =
1027 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1028 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1029 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1033 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo,
1035 MVT VT = N->getValueType(0);
1036 SDOperand Op = N->getOperand(0);
1037 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1038 if (VT == MVT::i64) {
1039 if (Op.getValueType() == MVT::f32)
1040 LC = RTLIB::FPTOSINT_F32_I64;
1041 else if (Op.getValueType() == MVT::f64)
1042 LC = RTLIB::FPTOSINT_F64_I64;
1043 else if (Op.getValueType() == MVT::f80)
1044 LC = RTLIB::FPTOSINT_F80_I64;
1045 else if (Op.getValueType() == MVT::ppcf128)
1046 LC = RTLIB::FPTOSINT_PPCF128_I64;
1047 } else if (VT == MVT::i128) {
1048 if (Op.getValueType() == MVT::f32)
1049 LC = RTLIB::FPTOSINT_F32_I128;
1050 else if (Op.getValueType() == MVT::f64)
1051 LC = RTLIB::FPTOSINT_F64_I128;
1052 else if (Op.getValueType() == MVT::f80)
1053 LC = RTLIB::FPTOSINT_F80_I128;
1054 else if (Op.getValueType() == MVT::ppcf128)
1055 LC = RTLIB::FPTOSINT_PPCF128_I128;
1057 assert(0 && "Unexpected fp-to-sint conversion!");
1059 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
1062 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo,
1064 MVT VT = N->getValueType(0);
1065 SDOperand Op = N->getOperand(0);
1066 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1067 if (VT == MVT::i64) {
1068 if (Op.getValueType() == MVT::f32)
1069 LC = RTLIB::FPTOUINT_F32_I64;
1070 else if (Op.getValueType() == MVT::f64)
1071 LC = RTLIB::FPTOUINT_F64_I64;
1072 else if (Op.getValueType() == MVT::f80)
1073 LC = RTLIB::FPTOUINT_F80_I64;
1074 else if (Op.getValueType() == MVT::ppcf128)
1075 LC = RTLIB::FPTOUINT_PPCF128_I64;
1076 } else if (VT == MVT::i128) {
1077 if (Op.getValueType() == MVT::f32)
1078 LC = RTLIB::FPTOUINT_F32_I128;
1079 else if (Op.getValueType() == MVT::f64)
1080 LC = RTLIB::FPTOUINT_F64_I128;
1081 else if (Op.getValueType() == MVT::f80)
1082 LC = RTLIB::FPTOUINT_F80_I128;
1083 else if (Op.getValueType() == MVT::ppcf128)
1084 LC = RTLIB::FPTOUINT_PPCF128_I128;
1086 assert(0 && "Unexpected fp-to-uint conversion!");
1088 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1091 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1092 SDOperand &Lo, SDOperand &Hi) {
1093 // FIXME: Add support for indexed loads.
1094 MVT VT = N->getValueType(0);
1095 MVT NVT = TLI.getTypeToTransformTo(VT);
1096 SDOperand Ch = N->getChain(); // Legalize the chain.
1097 SDOperand Ptr = N->getBasePtr(); // Legalize the pointer.
1098 ISD::LoadExtType ExtType = N->getExtensionType();
1099 int SVOffset = N->getSrcValueOffset();
1100 unsigned Alignment = N->getAlignment();
1101 bool isVolatile = N->isVolatile();
1103 assert(!(NVT.getSizeInBits() & 7) && "Expanded type not byte sized!");
1105 if (ExtType == ISD::NON_EXTLOAD) {
1106 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1107 isVolatile, Alignment);
1108 // Increment the pointer to the other half.
1109 unsigned IncrementSize = NVT.getSizeInBits()/8;
1110 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1111 DAG.getIntPtrConstant(IncrementSize));
1112 Hi = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
1113 isVolatile, MinAlign(Alignment, IncrementSize));
1115 // Build a factor node to remember that this load is independent of the
1117 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1120 // Handle endianness of the load.
1121 if (TLI.isBigEndian())
1123 } else if (N->getMemoryVT().bitsLE(NVT)) {
1124 MVT EVT = N->getMemoryVT();
1126 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1127 isVolatile, Alignment);
1129 // Remember the chain.
1130 Ch = Lo.getValue(1);
1132 if (ExtType == ISD::SEXTLOAD) {
1133 // The high part is obtained by SRA'ing all but one of the bits of the
1135 unsigned LoSize = Lo.getValueType().getSizeInBits();
1136 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1137 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1138 } else if (ExtType == ISD::ZEXTLOAD) {
1139 // The high part is just a zero.
1140 Hi = DAG.getConstant(0, NVT);
1142 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1143 // The high part is undefined.
1144 Hi = DAG.getNode(ISD::UNDEF, NVT);
1146 } else if (TLI.isLittleEndian()) {
1147 // Little-endian - low bits are at low addresses.
1148 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1149 isVolatile, Alignment);
1151 unsigned ExcessBits =
1152 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1153 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1155 // Increment the pointer to the other half.
1156 unsigned IncrementSize = NVT.getSizeInBits()/8;
1157 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1158 DAG.getIntPtrConstant(IncrementSize));
1159 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1160 SVOffset+IncrementSize, NEVT,
1161 isVolatile, MinAlign(Alignment, IncrementSize));
1163 // Build a factor node to remember that this load is independent of the
1165 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1168 // Big-endian - high bits are at low addresses. Favor aligned loads at
1169 // the cost of some bit-fiddling.
1170 MVT EVT = N->getMemoryVT();
1171 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1172 unsigned IncrementSize = NVT.getSizeInBits()/8;
1173 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1175 // Load both the high bits and maybe some of the low bits.
1176 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1177 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1178 isVolatile, Alignment);
1180 // Increment the pointer to the other half.
1181 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1182 DAG.getIntPtrConstant(IncrementSize));
1183 // Load the rest of the low bits.
1184 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1185 SVOffset+IncrementSize,
1186 MVT::getIntegerVT(ExcessBits),
1187 isVolatile, MinAlign(Alignment, IncrementSize));
1189 // Build a factor node to remember that this load is independent of the
1191 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1194 if (ExcessBits < NVT.getSizeInBits()) {
1195 // Transfer low bits from the bottom of Hi to the top of Lo.
1196 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1197 DAG.getNode(ISD::SHL, NVT, Hi,
1198 DAG.getConstant(ExcessBits,
1199 TLI.getShiftAmountTy())));
1200 // Move high bits to the right position in Hi.
1201 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1202 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1203 TLI.getShiftAmountTy()));
1207 // Legalized the chain result - switch anything that used the old chain to
1209 ReplaceValueWith(SDOperand(N, 1), Ch);
1212 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1213 SDOperand &Lo, SDOperand &Hi) {
1214 SDOperand LL, LH, RL, RH;
1215 GetExpandedInteger(N->getOperand(0), LL, LH);
1216 GetExpandedInteger(N->getOperand(1), RL, RH);
1217 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1218 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1221 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1222 SDOperand &Lo, SDOperand &Hi) {
1223 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1224 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1225 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1228 void DAGTypeLegalizer::ExpandIntRes_SELECT(SDNode *N,
1229 SDOperand &Lo, SDOperand &Hi) {
1230 SDOperand LL, LH, RL, RH;
1231 GetExpandedInteger(N->getOperand(1), LL, LH);
1232 GetExpandedInteger(N->getOperand(2), RL, RH);
1233 Lo = DAG.getNode(ISD::SELECT, LL.getValueType(), N->getOperand(0), LL, RL);
1234 Hi = DAG.getNode(ISD::SELECT, LL.getValueType(), N->getOperand(0), LH, RH);
1237 void DAGTypeLegalizer::ExpandIntRes_SELECT_CC(SDNode *N,
1238 SDOperand &Lo, SDOperand &Hi) {
1239 SDOperand LL, LH, RL, RH;
1240 GetExpandedInteger(N->getOperand(2), LL, LH);
1241 GetExpandedInteger(N->getOperand(3), RL, RH);
1242 Lo = DAG.getNode(ISD::SELECT_CC, LL.getValueType(), N->getOperand(0),
1243 N->getOperand(1), LL, RL, N->getOperand(4));
1244 Hi = DAG.getNode(ISD::SELECT_CC, LL.getValueType(), N->getOperand(0),
1245 N->getOperand(1), LH, RH, N->getOperand(4));
1248 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1249 SDOperand &Lo, SDOperand &Hi) {
1250 // Expand the subcomponents.
1251 SDOperand LHSL, LHSH, RHSL, RHSH;
1252 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1253 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1254 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1255 SDOperand LoOps[2] = { LHSL, RHSL };
1256 SDOperand HiOps[3] = { LHSH, RHSH };
1258 if (N->getOpcode() == ISD::ADD) {
1259 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1260 HiOps[2] = Lo.getValue(1);
1261 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1263 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1264 HiOps[2] = Lo.getValue(1);
1265 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1269 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1270 SDOperand &Lo, SDOperand &Hi) {
1271 // Expand the subcomponents.
1272 SDOperand LHSL, LHSH, RHSL, RHSH;
1273 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1274 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1275 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1276 SDOperand LoOps[2] = { LHSL, RHSL };
1277 SDOperand HiOps[3] = { LHSH, RHSH };
1279 if (N->getOpcode() == ISD::ADDC) {
1280 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1281 HiOps[2] = Lo.getValue(1);
1282 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1284 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1285 HiOps[2] = Lo.getValue(1);
1286 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1289 // Legalized the flag result - switch anything that used the old flag to
1291 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1294 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1295 SDOperand &Lo, SDOperand &Hi) {
1296 // Expand the subcomponents.
1297 SDOperand LHSL, LHSH, RHSL, RHSH;
1298 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1299 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1300 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1301 SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1302 SDOperand HiOps[3] = { LHSH, RHSH };
1304 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1305 HiOps[2] = Lo.getValue(1);
1306 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1308 // Legalized the flag result - switch anything that used the old flag to
1310 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1313 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1314 SDOperand &Lo, SDOperand &Hi) {
1315 MVT VT = N->getValueType(0);
1316 MVT NVT = TLI.getTypeToTransformTo(VT);
1318 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1319 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1320 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1321 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1322 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1323 SDOperand LL, LH, RL, RH;
1324 GetExpandedInteger(N->getOperand(0), LL, LH);
1325 GetExpandedInteger(N->getOperand(1), RL, RH);
1326 unsigned OuterBitSize = VT.getSizeInBits();
1327 unsigned BitSize = NVT.getSizeInBits();
1328 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1329 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1331 if (DAG.MaskedValueIsZero(N->getOperand(0),
1332 APInt::getHighBitsSet(OuterBitSize, LHSSB)) &&
1333 DAG.MaskedValueIsZero(N->getOperand(1),
1334 APInt::getHighBitsSet(OuterBitSize, RHSSB))) {
1335 // The inputs are both zero-extended.
1337 // We can emit a umul_lohi.
1338 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1339 Hi = SDOperand(Lo.Val, 1);
1343 // We can emit a mulhu+mul.
1344 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1345 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1349 if (LHSSB > BitSize && RHSSB > BitSize) {
1350 // The input values are both sign-extended.
1352 // We can emit a smul_lohi.
1353 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1354 Hi = SDOperand(Lo.Val, 1);
1358 // We can emit a mulhs+mul.
1359 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1360 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1365 // Lo,Hi = umul LHS, RHS.
1366 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1367 DAG.getVTList(NVT, NVT), LL, RL);
1369 Hi = UMulLOHI.getValue(1);
1370 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1371 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1372 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1373 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1378 // If nothing else, we can make a libcall.
1379 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1380 SplitInteger(MakeLibCall(RTLIB::MUL_I64, VT, Ops, 2, true/*sign irrelevant*/),
1384 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1385 SDOperand &Lo, SDOperand &Hi) {
1386 assert(N->getValueType(0) == MVT::i64 && "Unsupported sdiv!");
1387 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1388 SplitInteger(MakeLibCall(RTLIB::SDIV_I64, N->getValueType(0), Ops, 2, true),
1392 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1393 SDOperand &Lo, SDOperand &Hi) {
1394 assert(N->getValueType(0) == MVT::i64 && "Unsupported srem!");
1395 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1396 SplitInteger(MakeLibCall(RTLIB::SREM_I64, N->getValueType(0), Ops, 2, true),
1400 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1401 SDOperand &Lo, SDOperand &Hi) {
1402 assert(N->getValueType(0) == MVT::i64 && "Unsupported udiv!");
1403 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1404 SplitInteger(MakeLibCall(RTLIB::UDIV_I64, N->getValueType(0), Ops, 2, false),
1408 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1409 SDOperand &Lo, SDOperand &Hi) {
1410 assert(N->getValueType(0) == MVT::i64 && "Unsupported urem!");
1411 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1412 SplitInteger(MakeLibCall(RTLIB::UREM_I64, N->getValueType(0), Ops, 2, false),
1416 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1417 SDOperand &Lo, SDOperand &Hi) {
1418 MVT VT = N->getValueType(0);
1420 // If we can emit an efficient shift operation, do so now. Check to see if
1421 // the RHS is a constant.
1422 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1423 return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi);
1425 // If we can determine that the high bit of the shift is zero or one, even if
1426 // the low bits are variable, emit this shift in an optimized form.
1427 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1430 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1432 if (N->getOpcode() == ISD::SHL) {
1433 PartsOpc = ISD::SHL_PARTS;
1434 } else if (N->getOpcode() == ISD::SRL) {
1435 PartsOpc = ISD::SRL_PARTS;
1437 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1438 PartsOpc = ISD::SRA_PARTS;
1441 // Next check to see if the target supports this SHL_PARTS operation or if it
1442 // will custom expand it.
1443 MVT NVT = TLI.getTypeToTransformTo(VT);
1444 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1445 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1446 Action == TargetLowering::Custom) {
1447 // Expand the subcomponents.
1448 SDOperand LHSL, LHSH;
1449 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1451 SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) };
1452 MVT VT = LHSL.getValueType();
1453 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1454 Hi = Lo.getValue(1);
1458 // Otherwise, emit a libcall.
1459 assert(VT == MVT::i64 && "Unsupported shift!");
1463 if (N->getOpcode() == ISD::SHL) {
1464 LC = RTLIB::SHL_I64;
1465 isSigned = false; /*sign irrelevant*/
1466 } else if (N->getOpcode() == ISD::SRL) {
1467 LC = RTLIB::SRL_I64;
1470 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1471 LC = RTLIB::SRA_I64;
1475 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1476 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1479 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1480 SDOperand &Lo, SDOperand &Hi) {
1481 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1482 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1483 MVT NVT = Lo.getValueType();
1485 SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1486 DAG.getConstant(0, NVT), ISD::SETNE);
1488 SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1489 SDOperand HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1491 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1492 DAG.getNode(ISD::ADD, NVT, LoLZ,
1493 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1494 Hi = DAG.getConstant(0, NVT);
1497 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1498 SDOperand &Lo, SDOperand &Hi) {
1499 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1500 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1501 MVT NVT = Lo.getValueType();
1502 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1503 DAG.getNode(ISD::CTPOP, NVT, Hi));
1504 Hi = DAG.getConstant(0, NVT);
1507 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1508 SDOperand &Lo, SDOperand &Hi) {
1509 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1510 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1511 MVT NVT = Lo.getValueType();
1513 SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1514 DAG.getConstant(0, NVT), ISD::SETNE);
1516 SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1517 SDOperand HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1519 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1520 DAG.getNode(ISD::ADD, NVT, HiLZ,
1521 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1522 Hi = DAG.getConstant(0, NVT);
1525 void DAGTypeLegalizer::ExpandIntRes_EXTRACT_VECTOR_ELT(SDNode *N,
1528 SDOperand OldVec = N->getOperand(0);
1529 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
1531 // Convert to a vector of the expanded element type, for example
1532 // <2 x i64> -> <4 x i32>.
1533 MVT OldVT = N->getValueType(0);
1534 MVT NewVT = TLI.getTypeToTransformTo(OldVT);
1535 assert(OldVT.getSizeInBits() == 2 * NewVT.getSizeInBits() &&
1536 "Do not know how to handle this expansion!");
1538 SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
1539 MVT::getVectorVT(NewVT, 2*OldElts),
1542 // Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector.
1543 SDOperand Idx = N->getOperand(1);
1545 // Make sure the type of Idx is big enough to hold the new values.
1546 if (Idx.getValueType().bitsLT(TLI.getPointerTy()))
1547 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
1549 Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, Idx);
1550 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, Idx);
1552 Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx,
1553 DAG.getConstant(1, Idx.getValueType()));
1554 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, Idx);
1556 if (TLI.isBigEndian())
1560 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1561 /// and the shift amount is a constant 'Amt'. Expand the operation.
1562 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1563 SDOperand &Lo, SDOperand &Hi) {
1564 // Expand the incoming operand to be shifted, so that we have its parts
1566 GetExpandedInteger(N->getOperand(0), InL, InH);
1568 MVT NVT = InL.getValueType();
1569 unsigned VTBits = N->getValueType(0).getSizeInBits();
1570 unsigned NVTBits = NVT.getSizeInBits();
1571 MVT ShTy = N->getOperand(1).getValueType();
1573 if (N->getOpcode() == ISD::SHL) {
1575 Lo = Hi = DAG.getConstant(0, NVT);
1576 } else if (Amt > NVTBits) {
1577 Lo = DAG.getConstant(0, NVT);
1578 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1579 } else if (Amt == NVTBits) {
1580 Lo = DAG.getConstant(0, NVT);
1583 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
1584 Hi = DAG.getNode(ISD::OR, NVT,
1585 DAG.getNode(ISD::SHL, NVT, InH,
1586 DAG.getConstant(Amt, ShTy)),
1587 DAG.getNode(ISD::SRL, NVT, InL,
1588 DAG.getConstant(NVTBits-Amt, ShTy)));
1593 if (N->getOpcode() == ISD::SRL) {
1595 Lo = DAG.getConstant(0, NVT);
1596 Hi = DAG.getConstant(0, NVT);
1597 } else if (Amt > NVTBits) {
1598 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1599 Hi = DAG.getConstant(0, NVT);
1600 } else if (Amt == NVTBits) {
1602 Hi = DAG.getConstant(0, NVT);
1604 Lo = DAG.getNode(ISD::OR, NVT,
1605 DAG.getNode(ISD::SRL, NVT, InL,
1606 DAG.getConstant(Amt, ShTy)),
1607 DAG.getNode(ISD::SHL, NVT, InH,
1608 DAG.getConstant(NVTBits-Amt, ShTy)));
1609 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
1614 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1616 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1617 DAG.getConstant(NVTBits-1, ShTy));
1618 } else if (Amt > NVTBits) {
1619 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1620 DAG.getConstant(Amt-NVTBits, ShTy));
1621 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1622 DAG.getConstant(NVTBits-1, ShTy));
1623 } else if (Amt == NVTBits) {
1625 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1626 DAG.getConstant(NVTBits-1, ShTy));
1628 Lo = DAG.getNode(ISD::OR, NVT,
1629 DAG.getNode(ISD::SRL, NVT, InL,
1630 DAG.getConstant(Amt, ShTy)),
1631 DAG.getNode(ISD::SHL, NVT, InH,
1632 DAG.getConstant(NVTBits-Amt, ShTy)));
1633 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
1637 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1638 /// this shift based on knowledge of the high bit of the shift amount. If we
1639 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1641 bool DAGTypeLegalizer::
1642 ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
1643 SDOperand Amt = N->getOperand(1);
1644 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1645 MVT ShTy = Amt.getValueType();
1646 unsigned ShBits = ShTy.getSizeInBits();
1647 unsigned NVTBits = NVT.getSizeInBits();
1648 assert(isPowerOf2_32(NVTBits) &&
1649 "Expanded integer type size not a power of two!");
1651 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1652 APInt KnownZero, KnownOne;
1653 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1655 // If we don't know anything about the high bits, exit.
1656 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1659 // Get the incoming operand to be shifted.
1661 GetExpandedInteger(N->getOperand(0), InL, InH);
1663 // If we know that any of the high bits of the shift amount are one, then we
1664 // can do this as a couple of simple shifts.
1665 if (KnownOne.intersects(HighBitMask)) {
1666 // Mask out the high bit, which we know is set.
1667 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1668 DAG.getConstant(~HighBitMask, ShTy));
1670 switch (N->getOpcode()) {
1671 default: assert(0 && "Unknown shift");
1673 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1674 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1677 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1678 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1681 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1682 DAG.getConstant(NVTBits-1, ShTy));
1683 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1688 // If we know that all of the high bits of the shift amount are zero, then we
1689 // can do this as a couple of simple shifts.
1690 if ((KnownZero & HighBitMask) == HighBitMask) {
1692 SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
1693 DAG.getConstant(NVTBits, ShTy),
1696 switch (N->getOpcode()) {
1697 default: assert(0 && "Unknown shift");
1698 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1700 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1703 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1704 Hi = DAG.getNode(ISD::OR, NVT,
1705 DAG.getNode(Op1, NVT, InH, Amt),
1706 DAG.getNode(Op2, NVT, InL, Amt2));
1714 //===----------------------------------------------------------------------===//
1715 // Integer Operand Expansion
1716 //===----------------------------------------------------------------------===//
1718 /// ExpandIntegerOperand - This method is called when the specified operand of
1719 /// the specified node is found to need expansion. At this point, all of the
1720 /// result types of the node are known to be legal, but other operands of the
1721 /// node may need promotion or expansion as well as the specified one.
1722 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1723 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1724 SDOperand Res(0, 0);
1726 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1727 == TargetLowering::Custom)
1728 Res = TLI.LowerOperation(SDOperand(N, 0), DAG);
1731 switch (N->getOpcode()) {
1734 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1735 N->dump(&DAG); cerr << "\n";
1737 assert(0 && "Do not know how to expand this operator's operand!");
1740 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1741 case ISD::BIT_CONVERT: Res = ExpandIntOp_BIT_CONVERT(N); break;
1743 case ISD::SINT_TO_FP:
1744 Res = ExpandIntOp_SINT_TO_FP(N->getOperand(0), N->getValueType(0));
1746 case ISD::UINT_TO_FP:
1747 Res = ExpandIntOp_UINT_TO_FP(N->getOperand(0), N->getValueType(0));
1749 case ISD::EXTRACT_ELEMENT: Res = ExpandIntOp_EXTRACT_ELEMENT(N); break;
1751 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1752 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1755 Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1758 case ISD::BUILD_VECTOR: Res = ExpandIntOp_BUILD_VECTOR(N); break;
1762 // If the result is null, the sub-method took care of registering results etc.
1763 if (!Res.Val) return false;
1764 // If the result is N, the sub-method updated N in place. Check to see if any
1765 // operands are new, and if so, mark them.
1767 // Mark N as new and remark N and its operands. This allows us to correctly
1768 // revisit N if it needs another step of expansion and allows us to visit
1769 // any new operands to N.
1774 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1775 "Invalid operand expansion");
1777 ReplaceValueWith(SDOperand(N, 0), Res);
1781 SDOperand DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
1783 GetExpandedInteger(N->getOperand(0), InL, InH);
1784 // Just truncate the low part of the source.
1785 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
1788 SDOperand DAGTypeLegalizer::ExpandIntOp_BIT_CONVERT(SDNode *N) {
1789 if (N->getValueType(0).isVector()) {
1790 // An illegal integer type is being converted to a legal vector type.
1791 // Make a two element vector out of the expanded parts and convert that
1792 // instead, but only if the new vector type is legal (otherwise there
1793 // is no point, and it might create expansion loops). For example, on
1794 // x86 this turns v1i64 = BIT_CONVERT i64 into v1i64 = BIT_CONVERT v2i32.
1795 MVT OVT = N->getOperand(0).getValueType();
1796 MVT NVT = MVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2);
1798 if (isTypeLegal(NVT)) {
1800 GetExpandedInteger(N->getOperand(0), Parts[0], Parts[1]);
1802 if (TLI.isBigEndian())
1803 std::swap(Parts[0], Parts[1]);
1805 SDOperand Vec = DAG.getNode(ISD::BUILD_VECTOR, NVT, Parts, 2);
1806 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Vec);
1810 // Otherwise, store to a temporary and load out again as the new type.
1811 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
1814 SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDOperand Source,
1816 // We know the destination is legal, but that the input needs to be expanded.
1817 MVT SourceVT = Source.getValueType();
1819 // Check to see if the target has a custom way to lower this. If so, use it.
1820 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
1821 default: assert(0 && "This action not implemented for this operation!");
1822 case TargetLowering::Legal:
1823 case TargetLowering::Expand:
1824 break; // This case is handled below.
1825 case TargetLowering::Custom:
1826 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
1828 if (NV.Val) return NV;
1829 break; // The target lowered this.
1832 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1833 if (SourceVT == MVT::i64) {
1834 if (DestTy == MVT::f32)
1835 LC = RTLIB::SINTTOFP_I64_F32;
1837 assert(DestTy == MVT::f64 && "Unknown fp value type!");
1838 LC = RTLIB::SINTTOFP_I64_F64;
1840 } else if (SourceVT == MVT::i128) {
1841 if (DestTy == MVT::f32)
1842 LC = RTLIB::SINTTOFP_I128_F32;
1843 else if (DestTy == MVT::f64)
1844 LC = RTLIB::SINTTOFP_I128_F64;
1845 else if (DestTy == MVT::f80)
1846 LC = RTLIB::SINTTOFP_I128_F80;
1848 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
1849 LC = RTLIB::SINTTOFP_I128_PPCF128;
1852 assert(0 && "Unknown int value type!");
1855 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
1856 "Don't know how to expand this SINT_TO_FP!");
1857 return MakeLibCall(LC, DestTy, &Source, 1, true);
1860 SDOperand DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDOperand Source,
1862 // We know the destination is legal, but that the input needs to be expanded.
1863 assert(getTypeAction(Source.getValueType()) == ExpandInteger &&
1864 "This is not an expansion!");
1866 // If this is unsigned, and not supported, first perform the conversion to
1867 // signed, then adjust the result if the sign bit is set.
1868 SDOperand SignedConv = ExpandIntOp_SINT_TO_FP(Source, DestTy);
1870 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
1871 // incoming integer is set. To handle this, we dynamically test to see if
1872 // it is set, and, if so, add a fudge factor.
1874 GetExpandedInteger(Source, Lo, Hi);
1876 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1877 DAG.getConstant(0, Hi.getValueType()),
1879 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
1880 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
1881 SignSet, Four, Zero);
1882 uint64_t FF = 0x5f800000ULL;
1883 if (TLI.isLittleEndian()) FF <<= 32;
1884 Constant *FudgeFactor = ConstantInt::get((Type*)Type::Int64Ty, FF);
1886 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
1887 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
1888 SDOperand FudgeInReg;
1889 if (DestTy == MVT::f32)
1890 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
1891 else if (DestTy.bitsGT(MVT::f32))
1892 // FIXME: Avoid the extend by construction the right constantpool?
1893 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
1894 CPIdx, NULL, 0, MVT::f32);
1896 assert(0 && "Unexpected conversion");
1898 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
1901 SDOperand DAGTypeLegalizer::ExpandIntOp_EXTRACT_ELEMENT(SDNode *N) {
1903 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1904 return cast<ConstantSDNode>(N->getOperand(1))->getValue() ? Hi : Lo;
1907 SDOperand DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
1908 SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1909 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1910 ExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1912 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1913 // against zero to select between true and false values.
1914 if (NewRHS.Val == 0) {
1915 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1916 CCCode = ISD::SETNE;
1919 // Update N to have the operands specified.
1920 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
1921 DAG.getCondCode(CCCode), NewLHS, NewRHS,
1925 SDOperand DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
1926 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1927 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1928 ExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1930 // If ExpandSetCCOperands returned a scalar, use it.
1931 if (NewRHS.Val == 0) return NewLHS;
1933 // Otherwise, update N to have the operands specified.
1934 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1935 DAG.getCondCode(CCCode));
1938 /// ExpandSetCCOperands - Expand the operands of a comparison. This code is
1939 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
1940 void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
1941 ISD::CondCode &CCCode) {
1942 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1943 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1944 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1946 MVT VT = NewLHS.getValueType();
1947 if (VT == MVT::ppcf128) {
1948 // FIXME: This generated code sucks. We want to generate
1949 // FCMP crN, hi1, hi2
1951 // FCMP crN, lo1, lo2
1952 // The following can be improved, but not that much.
1953 SDOperand Tmp1, Tmp2, Tmp3;
1954 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
1955 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
1956 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
1957 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
1958 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
1959 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
1960 NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
1961 NewRHS = SDOperand(); // LHS is the result, not a compare.
1965 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1967 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1968 if (RHSCST->isAllOnesValue()) {
1969 // Equality comparison to -1.
1970 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1975 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1976 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1977 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1978 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1982 // If this is a comparison of the sign bit, just look at the top part.
1984 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1985 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1986 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1992 // FIXME: This generated code sucks.
1993 ISD::CondCode LowCC;
1995 default: assert(0 && "Unknown integer setcc!");
1997 case ISD::SETULT: LowCC = ISD::SETULT; break;
1999 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2001 case ISD::SETULE: LowCC = ISD::SETULE; break;
2003 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2006 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2007 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2008 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2010 // NOTE: on targets without efficient SELECT of bools, we can always use
2011 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2012 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
2013 SDOperand Tmp1, Tmp2;
2014 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
2015 false, DagCombineInfo);
2017 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
2018 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2019 CCCode, false, DagCombineInfo);
2021 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2022 DAG.getCondCode(CCCode));
2024 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
2025 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
2026 if ((Tmp1C && Tmp1C->isNullValue()) ||
2027 (Tmp2C && Tmp2C->isNullValue() &&
2028 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2029 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2030 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2031 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2032 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2033 // low part is known false, returns high part.
2034 // For LE / GE, if high part is known false, ignore the low part.
2035 // For LT / GT, if high part is known true, ignore the low part.
2037 NewRHS = SDOperand();
2041 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2042 ISD::SETEQ, false, DagCombineInfo);
2044 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2046 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
2047 NewLHS, Tmp1, Tmp2);
2048 NewRHS = SDOperand();
2051 SDOperand DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2052 // FIXME: Add support for indexed stores.
2053 assert(OpNo == 1 && "Can only expand the stored value so far");
2055 MVT VT = N->getOperand(1).getValueType();
2056 MVT NVT = TLI.getTypeToTransformTo(VT);
2057 SDOperand Ch = N->getChain();
2058 SDOperand Ptr = N->getBasePtr();
2059 int SVOffset = N->getSrcValueOffset();
2060 unsigned Alignment = N->getAlignment();
2061 bool isVolatile = N->isVolatile();
2064 assert(!(NVT.getSizeInBits() & 7) && "Expanded type not byte sized!");
2066 if (!N->isTruncatingStore()) {
2067 unsigned IncrementSize = 0;
2068 GetExpandedInteger(N->getValue(), Lo, Hi);
2069 IncrementSize = Hi.getValueType().getSizeInBits()/8;
2071 if (TLI.isBigEndian())
2074 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(),
2075 SVOffset, isVolatile, Alignment);
2077 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2078 DAG.getIntPtrConstant(IncrementSize));
2079 assert(isTypeLegal(Ptr.getValueType()) && "Pointers must be legal!");
2080 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
2081 isVolatile, MinAlign(Alignment, IncrementSize));
2082 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2083 } else if (N->getMemoryVT().bitsLE(NVT)) {
2084 GetExpandedInteger(N->getValue(), Lo, Hi);
2085 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2086 N->getMemoryVT(), isVolatile, Alignment);
2087 } else if (TLI.isLittleEndian()) {
2088 // Little-endian - low bits are at low addresses.
2089 GetExpandedInteger(N->getValue(), Lo, Hi);
2091 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2092 isVolatile, Alignment);
2094 unsigned ExcessBits =
2095 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2096 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2098 // Increment the pointer to the other half.
2099 unsigned IncrementSize = NVT.getSizeInBits()/8;
2100 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2101 DAG.getIntPtrConstant(IncrementSize));
2102 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2103 SVOffset+IncrementSize, NEVT,
2104 isVolatile, MinAlign(Alignment, IncrementSize));
2105 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2107 // Big-endian - high bits are at low addresses. Favor aligned stores at
2108 // the cost of some bit-fiddling.
2109 GetExpandedInteger(N->getValue(), Lo, Hi);
2111 MVT EVT = N->getMemoryVT();
2112 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2113 unsigned IncrementSize = NVT.getSizeInBits()/8;
2114 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2115 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2117 if (ExcessBits < NVT.getSizeInBits()) {
2118 // Transfer high bits from the top of Lo to the bottom of Hi.
2119 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
2120 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2121 TLI.getShiftAmountTy()));
2122 Hi = DAG.getNode(ISD::OR, NVT, Hi,
2123 DAG.getNode(ISD::SRL, NVT, Lo,
2124 DAG.getConstant(ExcessBits,
2125 TLI.getShiftAmountTy())));
2128 // Store both the high bits and maybe some of the low bits.
2129 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2130 SVOffset, HiVT, isVolatile, Alignment);
2132 // Increment the pointer to the other half.
2133 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2134 DAG.getIntPtrConstant(IncrementSize));
2135 // Store the lowest ExcessBits bits in the second half.
2136 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
2137 SVOffset+IncrementSize,
2138 MVT::getIntegerVT(ExcessBits),
2139 isVolatile, MinAlign(Alignment, IncrementSize));
2140 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2144 SDOperand DAGTypeLegalizer::ExpandIntOp_BUILD_VECTOR(SDNode *N) {
2145 // The vector type is legal but the element type needs expansion.
2146 MVT VecVT = N->getValueType(0);
2147 unsigned NumElts = VecVT.getVectorNumElements();
2148 MVT OldVT = N->getOperand(0).getValueType();
2149 MVT NewVT = TLI.getTypeToTransformTo(OldVT);
2151 assert(OldVT.getSizeInBits() == 2 * NewVT.getSizeInBits() &&
2152 "Do not know how to expand this operand!");
2154 // Build a vector of twice the length out of the expanded elements.
2155 // For example <2 x i64> -> <4 x i32>.
2156 std::vector<SDOperand> NewElts;
2157 NewElts.reserve(NumElts*2);
2159 for (unsigned i = 0; i < NumElts; ++i) {
2161 GetExpandedInteger(N->getOperand(i), Lo, Hi);
2162 if (TLI.isBigEndian())
2164 NewElts.push_back(Lo);
2165 NewElts.push_back(Hi);
2168 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
2169 MVT::getVectorVT(NewVT, NewElts.size()),
2170 &NewElts[0], NewElts.size());
2172 // Convert the new vector to the old vector type.
2173 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);