1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/Constants.h"
25 //===----------------------------------------------------------------------===//
26 // Integer Result Promotion
27 //===----------------------------------------------------------------------===//
29 /// PromoteIntegerResult - This method is called when a result of a node is
30 /// found to be in need of promotion to a larger type. At this point, the node
31 /// may also have invalid operands or may have other results that need
32 /// expansion, we just know that (at least) one result needs promotion.
33 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
35 SDOperand Result = SDOperand();
37 switch (N->getOpcode()) {
40 cerr << "PromoteIntegerResult #" << ResNo << ": ";
41 N->dump(&DAG); cerr << "\n";
43 assert(0 && "Do not know how to promote this operator!");
45 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
46 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
48 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
49 case ISD::SIGN_EXTEND:
50 case ISD::ZERO_EXTEND:
51 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
52 case ISD::FP_ROUND: Result = PromoteIntRes_FP_ROUND(N); break;
54 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
55 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
56 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
57 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
65 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
68 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
71 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
73 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
74 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
77 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
78 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
80 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
81 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
82 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
84 case ISD::EXTRACT_VECTOR_ELT:
85 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N);
89 // If Result is null, the sub-method took care of registering the result.
91 SetPromotedInteger(SDOperand(N, ResNo), Result);
94 SDOperand DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
95 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
98 SDOperand DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
99 MVT VT = N->getValueType(0);
100 // Zero extend things like i1, sign extend everything else. It shouldn't
101 // matter in theory which one we pick, but this tends to give better code?
102 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
103 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
105 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
109 SDOperand DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
112 switch (getTypeAction(N->getOperand(0).getValueType())) {
113 default: assert(0 && "Unknown type action!");
116 Res = N->getOperand(0);
119 Res = GetPromotedInteger(N->getOperand(0));
123 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
124 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
125 "Truncation doesn't make sense!");
126 if (Res.getValueType() == NVT)
129 // Truncate to NVT instead of VT
130 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
133 SDOperand DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
134 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
136 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
137 SDOperand Res = GetPromotedInteger(N->getOperand(0));
138 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
139 "Extension doesn't make sense!");
141 // If the result and operand types are the same after promotion, simplify
142 // to an in-register extension.
143 if (NVT == Res.getValueType()) {
144 // The high bits are not guaranteed to be anything. Insert an extend.
145 if (N->getOpcode() == ISD::SIGN_EXTEND)
146 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
147 DAG.getValueType(N->getOperand(0).getValueType()));
148 if (N->getOpcode() == ISD::ZERO_EXTEND)
149 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
150 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
155 // Otherwise, just extend the original operand all the way to the larger type.
156 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
159 SDOperand DAGTypeLegalizer::PromoteIntRes_FP_ROUND(SDNode *N) {
160 // NOTE: Assumes input is legal.
161 if (N->getConstantOperandVal(1) == 0)
162 return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
163 N->getOperand(0), DAG.getValueType(N->getValueType(0)));
164 // If the precision discard isn't needed, just return the operand unrounded.
165 return N->getOperand(0);
168 SDOperand DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
169 unsigned NewOpc = N->getOpcode();
170 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
172 // If we're promoting a UINT to a larger size, check to see if the new node
173 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
174 // we can use that instead. This allows us to generate better code for
175 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
176 // legal, such as PowerPC.
177 if (N->getOpcode() == ISD::FP_TO_UINT) {
178 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
179 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
180 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
181 NewOpc = ISD::FP_TO_SINT;
184 return DAG.getNode(NewOpc, NVT, N->getOperand(0));
187 SDOperand DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
188 assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
189 && "SetCC type is not legal??");
190 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
191 N->getOperand(0), N->getOperand(1), N->getOperand(2));
194 SDOperand DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
195 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
196 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
197 ISD::LoadExtType ExtType =
198 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
199 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
200 N->getSrcValue(), N->getSrcValueOffset(),
201 N->getMemoryVT(), N->isVolatile(),
204 // Legalized the chain result - switch anything that used the old chain to
206 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
210 SDOperand DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
211 // The pair element type may be legal, or may not promote to the same type as
212 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
213 return DAG.getNode(ISD::ANY_EXTEND,
214 TLI.getTypeToTransformTo(N->getValueType(0)),
215 JoinIntegers(N->getOperand(0), N->getOperand(1)));
218 SDOperand DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
219 SDOperand InOp = N->getOperand(0);
220 MVT InVT = InOp.getValueType();
221 MVT NInVT = TLI.getTypeToTransformTo(InVT);
222 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
224 switch (getTypeAction(InVT)) {
226 assert(false && "Unknown type action!");
231 if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
232 // The input promotes to the same size. Convert the promoted value.
233 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
236 // Promote the integer operand by hand.
237 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp));
242 // Convert the element to an integer and promote it by hand.
243 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
244 BitConvertToInteger(GetScalarizedVector(InOp)));
246 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
247 // pieces of the input into integers and reassemble in the final type.
249 GetSplitVector(N->getOperand(0), Lo, Hi);
250 Lo = BitConvertToInteger(Lo);
251 Hi = BitConvertToInteger(Hi);
253 if (TLI.isBigEndian())
256 InOp = DAG.getNode(ISD::ANY_EXTEND,
257 MVT::getIntegerVT(OutVT.getSizeInBits()),
258 JoinIntegers(Lo, Hi));
259 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
262 // Otherwise, lower the bit-convert to a store/load from the stack, then
264 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
265 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val));
268 SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
269 // The input may have strange things in the top bits of the registers, but
270 // these operations don't care. They may have weird bits going out, but
271 // that too is okay if they are integer operations.
272 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
273 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
274 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
277 SDOperand DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
278 // Sign extend the input.
279 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
280 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
281 MVT VT = N->getValueType(0);
282 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
283 DAG.getValueType(VT));
284 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
285 DAG.getValueType(VT));
287 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
290 SDOperand DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
291 // Zero extend the input.
292 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
293 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
294 MVT VT = N->getValueType(0);
295 LHS = DAG.getZeroExtendInReg(LHS, VT);
296 RHS = DAG.getZeroExtendInReg(RHS, VT);
298 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
301 SDOperand DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
302 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
303 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
306 SDOperand DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
307 // The input value must be properly sign extended.
308 MVT VT = N->getValueType(0);
309 MVT NVT = TLI.getTypeToTransformTo(VT);
310 SDOperand Res = GetPromotedInteger(N->getOperand(0));
311 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
312 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
315 SDOperand DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
316 // The input value must be properly zero extended.
317 MVT VT = N->getValueType(0);
318 MVT NVT = TLI.getTypeToTransformTo(VT);
319 SDOperand Res = ZExtPromotedInteger(N->getOperand(0));
320 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
323 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
324 SDOperand LHS = GetPromotedInteger(N->getOperand(1));
325 SDOperand RHS = GetPromotedInteger(N->getOperand(2));
326 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
329 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
330 SDOperand LHS = GetPromotedInteger(N->getOperand(2));
331 SDOperand RHS = GetPromotedInteger(N->getOperand(3));
332 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
333 N->getOperand(1), LHS, RHS, N->getOperand(4));
336 SDOperand DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
337 SDOperand Op = GetPromotedInteger(N->getOperand(0));
338 MVT OVT = N->getValueType(0);
339 MVT NVT = Op.getValueType();
340 // Zero extend to the promoted type and do the count there.
341 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
342 // Subtract off the extra leading bits in the bigger type.
343 return DAG.getNode(ISD::SUB, NVT, Op,
344 DAG.getConstant(NVT.getSizeInBits() -
345 OVT.getSizeInBits(), NVT));
348 SDOperand DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
349 SDOperand Op = GetPromotedInteger(N->getOperand(0));
350 MVT OVT = N->getValueType(0);
351 MVT NVT = Op.getValueType();
352 // Zero extend to the promoted type and do the count there.
353 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
356 SDOperand DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
357 SDOperand Op = GetPromotedInteger(N->getOperand(0));
358 MVT OVT = N->getValueType(0);
359 MVT NVT = Op.getValueType();
360 // The count is the same in the promoted type except if the original
361 // value was zero. This can be handled by setting the bit just off
362 // the top of the original type.
363 Op = DAG.getNode(ISD::OR, NVT, Op,
364 // FIXME: Do this using an APINT constant.
365 DAG.getConstant(1UL << OVT.getSizeInBits(), NVT));
366 return DAG.getNode(ISD::CTTZ, NVT, Op);
369 SDOperand DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
370 MVT OldVT = N->getValueType(0);
371 SDOperand OldVec = N->getOperand(0);
372 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
375 assert(!isTypeLegal(OldVec.getValueType()) &&
376 "Legal one-element vector of a type needing promotion!");
377 // It is tempting to follow GetScalarizedVector by a call to
378 // GetPromotedInteger, but this would be wrong because the
379 // scalarized value may not yet have been processed.
380 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
381 GetScalarizedVector(OldVec));
384 // Convert to a vector half as long with an element type of twice the width,
385 // for example <4 x i16> -> <2 x i32>.
386 assert(!(OldElts & 1) && "Odd length vectors not supported!");
387 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
388 assert(OldVT.isSimple() && NewVT.isSimple());
390 SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
391 MVT::getVectorVT(NewVT, OldElts / 2),
394 // Extract the element at OldIdx / 2 from the new vector.
395 SDOperand OldIdx = N->getOperand(1);
396 SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
397 DAG.getConstant(1, TLI.getShiftAmountTy()));
398 SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
400 // Select the appropriate half of the element: Lo if OldIdx was even,
403 SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
404 DAG.getConstant(OldVT.getSizeInBits(),
405 TLI.getShiftAmountTy()));
406 if (TLI.isBigEndian())
409 SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
410 DAG.getConstant(1, TLI.getShiftAmountTy()));
411 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
414 //===----------------------------------------------------------------------===//
415 // Integer Operand Promotion
416 //===----------------------------------------------------------------------===//
418 /// PromoteIntegerOperand - This method is called when the specified operand of
419 /// the specified node is found to need promotion. At this point, all of the
420 /// result types of the node are known to be legal, but other operands of the
421 /// node may need promotion or expansion as well as the specified one.
422 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
423 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
425 switch (N->getOpcode()) {
428 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
429 N->dump(&DAG); cerr << "\n";
431 assert(0 && "Do not know how to promote this operator's operand!");
434 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
435 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
436 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
437 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
438 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break;
439 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break;
440 case ISD::SINT_TO_FP:
441 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break;
442 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
444 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
445 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
446 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
447 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
448 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
450 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
453 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
454 case ISD::INSERT_VECTOR_ELT:
455 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);
458 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
461 // If the result is null, the sub-method took care of registering results etc.
462 if (!Res.Val) return false;
463 // If the result is N, the sub-method updated N in place.
465 // Mark N as new and remark N and its operands. This allows us to correctly
466 // revisit N if it needs another step of promotion and allows us to visit
467 // any new operands to N.
472 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
473 "Invalid operand expansion");
475 ReplaceValueWith(SDOperand(N, 0), Res);
479 SDOperand DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
480 SDOperand Op = GetPromotedInteger(N->getOperand(0));
481 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
484 SDOperand DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
485 SDOperand Op = GetPromotedInteger(N->getOperand(0));
486 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
487 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
490 SDOperand DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
491 SDOperand Op = GetPromotedInteger(N->getOperand(0));
492 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
493 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
494 Op, DAG.getValueType(N->getOperand(0).getValueType()));
497 SDOperand DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
498 SDOperand Op = GetPromotedInteger(N->getOperand(0));
499 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
502 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
503 SDOperand Op = GetPromotedInteger(N->getOperand(0));
504 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
507 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
508 SDOperand Op = GetPromotedInteger(N->getOperand(0));
509 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
510 DAG.getIntPtrConstant(0));
513 SDOperand DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
514 SDOperand In = GetPromotedInteger(N->getOperand(0));
515 MVT OpVT = N->getOperand(0).getValueType();
516 if (N->getOpcode() == ISD::UINT_TO_FP)
517 In = DAG.getZeroExtendInReg(In, OpVT);
519 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
520 In, DAG.getValueType(OpVT));
522 return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
525 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
526 // Since the result type is legal, the operands must promote to it.
527 MVT OVT = N->getOperand(0).getValueType();
528 SDOperand Lo = GetPromotedInteger(N->getOperand(0));
529 SDOperand Hi = GetPromotedInteger(N->getOperand(1));
530 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
532 Lo = DAG.getZeroExtendInReg(Lo, OVT);
533 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
534 DAG.getConstant(OVT.getSizeInBits(),
535 TLI.getShiftAmountTy()));
536 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
539 SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
540 assert(OpNo == 0 && "Only know how to promote condition");
541 SDOperand Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition.
543 // The top bits of the promoted condition are not necessarily zero, ensure
544 // that the value is properly zero extended.
545 unsigned BitWidth = Cond.getValueSizeInBits();
546 if (!DAG.MaskedValueIsZero(Cond,
547 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
548 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
550 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
551 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
555 SDOperand DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
556 assert(OpNo == 1 && "only know how to promote condition");
557 SDOperand Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
559 // The top bits of the promoted condition are not necessarily zero, ensure
560 // that the value is properly zero extended.
561 unsigned BitWidth = Cond.getValueSizeInBits();
562 if (!DAG.MaskedValueIsZero(Cond,
563 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
564 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
566 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
567 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
571 SDOperand DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
572 assert(OpNo == 2 && "Don't know how to promote this operand!");
574 SDOperand LHS = N->getOperand(2);
575 SDOperand RHS = N->getOperand(3);
576 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
578 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
580 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
581 N->getOperand(1), LHS, RHS, N->getOperand(4));
584 SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
585 assert(OpNo == 0 && "Don't know how to promote this operand!");
587 SDOperand LHS = N->getOperand(0);
588 SDOperand RHS = N->getOperand(1);
589 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
591 // The CC (#4) and the possible return values (#2 and #3) have legal types.
592 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2),
593 N->getOperand(3), N->getOperand(4));
596 SDOperand DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
597 assert(OpNo == 0 && "Don't know how to promote this operand!");
599 SDOperand LHS = N->getOperand(0);
600 SDOperand RHS = N->getOperand(1);
601 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
603 // The CC (#2) is always legal.
604 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
607 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
608 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
609 void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
610 ISD::CondCode CCCode) {
611 MVT VT = NewLHS.getValueType();
613 // Get the promoted values.
614 NewLHS = GetPromotedInteger(NewLHS);
615 NewRHS = GetPromotedInteger(NewRHS);
617 // Otherwise, we have to insert explicit sign or zero extends. Note
618 // that we could insert sign extends for ALL conditions, but zero extend
619 // is cheaper on many machines (an AND instead of two shifts), so prefer
622 default: assert(0 && "Unknown integer comparison!");
629 // ALL of these operations will work if we either sign or zero extend
630 // the operands (including the unsigned comparisons!). Zero extend is
631 // usually a simpler/cheaper operation, so prefer it.
632 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
633 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
639 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
640 DAG.getValueType(VT));
641 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
642 DAG.getValueType(VT));
647 SDOperand DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
648 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
649 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
650 int SVOffset = N->getSrcValueOffset();
651 unsigned Alignment = N->getAlignment();
652 bool isVolatile = N->isVolatile();
654 SDOperand Val = GetPromotedInteger(N->getValue()); // Get promoted value.
656 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
658 // Truncate the value and store the result.
659 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
660 SVOffset, N->getMemoryVT(),
661 isVolatile, Alignment);
664 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
665 // The vector type is legal but the element type is not. This implies
666 // that the vector is a power-of-two in length and that the element
667 // type does not have a strange size (eg: it is not i1).
668 MVT VecVT = N->getValueType(0);
669 unsigned NumElts = VecVT.getVectorNumElements();
670 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
672 // Build a vector of half the length out of elements of twice the bitwidth.
673 // For example <4 x i16> -> <2 x i32>.
674 MVT OldVT = N->getOperand(0).getValueType();
675 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
676 assert(OldVT.isSimple() && NewVT.isSimple());
678 std::vector<SDOperand> NewElts;
679 NewElts.reserve(NumElts/2);
681 for (unsigned i = 0; i < NumElts; i += 2) {
682 // Combine two successive elements into one promoted element.
683 SDOperand Lo = N->getOperand(i);
684 SDOperand Hi = N->getOperand(i+1);
685 if (TLI.isBigEndian())
687 NewElts.push_back(JoinIntegers(Lo, Hi));
690 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
691 MVT::getVectorVT(NewVT, NewElts.size()),
692 &NewElts[0], NewElts.size());
694 // Convert the new vector to the old vector type.
695 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
698 SDOperand DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
701 // Promote the inserted value. This is valid because the type does not
702 // have to match the vector element type.
704 // Check that any extra bits introduced will be truncated away.
705 assert(N->getOperand(1).getValueType().getSizeInBits() >=
706 N->getValueType(0).getVectorElementType().getSizeInBits() &&
707 "Type of inserted value narrower than vector element type!");
708 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
709 GetPromotedInteger(N->getOperand(1)),
713 assert(OpNo == 2 && "Different operand and result vector types?");
715 // Promote the index.
716 SDOperand Idx = N->getOperand(2);
717 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType());
718 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
719 N->getOperand(1), Idx);
722 SDOperand DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
724 NewOps[0] = N->getOperand(0);
725 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
726 SDOperand Flag = GetPromotedInteger(N->getOperand(i));
727 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
729 return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps,
730 array_lengthof(NewOps));
734 //===----------------------------------------------------------------------===//
735 // Integer Result Expansion
736 //===----------------------------------------------------------------------===//
738 /// ExpandIntegerResult - This method is called when the specified result of the
739 /// specified node is found to need expansion. At this point, the node may also
740 /// have invalid operands or may have other results that need promotion, we just
741 /// know that (at least) one result needs expansion.
742 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
743 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
745 Lo = Hi = SDOperand();
747 // See if the target wants to custom expand this node.
748 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
749 TargetLowering::Custom) {
750 // If the target wants to, allow it to lower this itself.
751 if (SDNode *P = TLI.ExpandOperationResult(N, DAG)) {
752 // Everything that once used N now uses P. We are guaranteed that the
753 // result value types of N and the result value types of P match.
754 ReplaceNodeWith(N, P);
759 switch (N->getOpcode()) {
762 cerr << "ExpandIntegerResult #" << ResNo << ": ";
763 N->dump(&DAG); cerr << "\n";
765 assert(0 && "Do not know how to expand the result of this operator!");
768 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
769 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
770 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
771 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
773 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
774 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
775 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
776 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
778 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
779 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
780 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
781 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
782 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
783 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
784 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
785 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
786 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
787 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
791 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
792 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
794 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
796 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
798 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
799 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
800 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
801 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
802 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
803 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
806 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
808 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
809 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
810 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
813 // If Lo/Hi is null, the sub-method took care of registering results etc.
815 SetExpandedInteger(SDOperand(N, ResNo), Lo, Hi);
818 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
819 SDOperand &Lo, SDOperand &Hi) {
820 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
821 unsigned NBitWidth = NVT.getSizeInBits();
822 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
823 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
824 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
827 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
828 SDOperand &Lo, SDOperand &Hi) {
829 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
830 SDOperand Op = N->getOperand(0);
831 if (Op.getValueType().bitsLE(NVT)) {
832 // The low part is any extension of the input (which degenerates to a copy).
833 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
834 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
836 // For example, extension of an i48 to an i64. The operand type necessarily
837 // promotes to the result type, so will end up being expanded too.
838 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
839 "Only know how to promote this result!");
840 SDOperand Res = GetPromotedInteger(Op);
841 assert(Res.getValueType() == N->getValueType(0) &&
842 "Operand over promoted?");
843 // Split the promoted operand. This will simplify when it is expanded.
844 SplitInteger(Res, Lo, Hi);
848 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
849 SDOperand &Lo, SDOperand &Hi) {
850 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
851 SDOperand Op = N->getOperand(0);
852 if (Op.getValueType().bitsLE(NVT)) {
853 // The low part is zero extension of the input (which degenerates to a copy).
854 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
855 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
857 // For example, extension of an i48 to an i64. The operand type necessarily
858 // promotes to the result type, so will end up being expanded too.
859 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
860 "Only know how to promote this result!");
861 SDOperand Res = GetPromotedInteger(Op);
862 assert(Res.getValueType() == N->getValueType(0) &&
863 "Operand over promoted?");
864 // Split the promoted operand. This will simplify when it is expanded.
865 SplitInteger(Res, Lo, Hi);
866 unsigned ExcessBits =
867 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
868 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
872 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
873 SDOperand &Lo, SDOperand &Hi) {
874 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
875 SDOperand Op = N->getOperand(0);
876 if (Op.getValueType().bitsLE(NVT)) {
877 // The low part is sign extension of the input (which degenerates to a copy).
878 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
879 // The high part is obtained by SRA'ing all but one of the bits of low part.
880 unsigned LoSize = NVT.getSizeInBits();
881 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
882 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
884 // For example, extension of an i48 to an i64. The operand type necessarily
885 // promotes to the result type, so will end up being expanded too.
886 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
887 "Only know how to promote this result!");
888 SDOperand Res = GetPromotedInteger(Op);
889 assert(Res.getValueType() == N->getValueType(0) &&
890 "Operand over promoted?");
891 // Split the promoted operand. This will simplify when it is expanded.
892 SplitInteger(Res, Lo, Hi);
893 unsigned ExcessBits =
894 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
895 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
896 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
900 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
901 SDOperand &Lo, SDOperand &Hi) {
902 GetExpandedInteger(N->getOperand(0), Lo, Hi);
903 MVT NVT = Lo.getValueType();
904 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
905 unsigned NVTBits = NVT.getSizeInBits();
906 unsigned EVTBits = EVT.getSizeInBits();
908 if (NVTBits < EVTBits) {
909 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
910 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
912 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
913 // The high part must be zero, make it explicit.
914 Hi = DAG.getConstant(0, NVT);
918 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
919 SDOperand &Lo, SDOperand &Hi) {
920 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
921 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
922 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
923 DAG.getConstant(NVT.getSizeInBits(),
924 TLI.getShiftAmountTy()));
925 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
928 void DAGTypeLegalizer::
929 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
930 GetExpandedInteger(N->getOperand(0), Lo, Hi);
931 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
933 if (EVT.bitsLE(Lo.getValueType())) {
934 // sext_inreg the low part if needed.
935 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
938 // The high part gets the sign extension from the lo-part. This handles
939 // things like sextinreg V:i64 from i8.
940 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
941 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
942 TLI.getShiftAmountTy()));
944 // For example, extension of an i48 to an i64. Leave the low part alone,
945 // sext_inreg the high part.
946 unsigned ExcessBits =
947 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
948 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
949 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
953 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo,
955 MVT VT = N->getValueType(0);
956 SDOperand Op = N->getOperand(0);
957 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
958 if (VT == MVT::i64) {
959 if (Op.getValueType() == MVT::f32)
960 LC = RTLIB::FPTOSINT_F32_I64;
961 else if (Op.getValueType() == MVT::f64)
962 LC = RTLIB::FPTOSINT_F64_I64;
963 else if (Op.getValueType() == MVT::f80)
964 LC = RTLIB::FPTOSINT_F80_I64;
965 else if (Op.getValueType() == MVT::ppcf128)
966 LC = RTLIB::FPTOSINT_PPCF128_I64;
967 } else if (VT == MVT::i128) {
968 if (Op.getValueType() == MVT::f32)
969 LC = RTLIB::FPTOSINT_F32_I128;
970 else if (Op.getValueType() == MVT::f64)
971 LC = RTLIB::FPTOSINT_F64_I128;
972 else if (Op.getValueType() == MVT::f80)
973 LC = RTLIB::FPTOSINT_F80_I128;
974 else if (Op.getValueType() == MVT::ppcf128)
975 LC = RTLIB::FPTOSINT_PPCF128_I128;
977 assert(0 && "Unexpected fp-to-sint conversion!");
979 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
982 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo,
984 MVT VT = N->getValueType(0);
985 SDOperand Op = N->getOperand(0);
986 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
987 if (VT == MVT::i64) {
988 if (Op.getValueType() == MVT::f32)
989 LC = RTLIB::FPTOUINT_F32_I64;
990 else if (Op.getValueType() == MVT::f64)
991 LC = RTLIB::FPTOUINT_F64_I64;
992 else if (Op.getValueType() == MVT::f80)
993 LC = RTLIB::FPTOUINT_F80_I64;
994 else if (Op.getValueType() == MVT::ppcf128)
995 LC = RTLIB::FPTOUINT_PPCF128_I64;
996 } else if (VT == MVT::i128) {
997 if (Op.getValueType() == MVT::f32)
998 LC = RTLIB::FPTOUINT_F32_I128;
999 else if (Op.getValueType() == MVT::f64)
1000 LC = RTLIB::FPTOUINT_F64_I128;
1001 else if (Op.getValueType() == MVT::f80)
1002 LC = RTLIB::FPTOUINT_F80_I128;
1003 else if (Op.getValueType() == MVT::ppcf128)
1004 LC = RTLIB::FPTOUINT_PPCF128_I128;
1006 assert(0 && "Unexpected fp-to-uint conversion!");
1008 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1011 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1012 SDOperand &Lo, SDOperand &Hi) {
1013 if (ISD::isNormalLoad(N)) {
1014 ExpandRes_NormalLoad(N, Lo, Hi);
1018 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1020 MVT VT = N->getValueType(0);
1021 MVT NVT = TLI.getTypeToTransformTo(VT);
1022 SDOperand Ch = N->getChain(); // Legalize the chain.
1023 SDOperand Ptr = N->getBasePtr(); // Legalize the pointer.
1024 ISD::LoadExtType ExtType = N->getExtensionType();
1025 int SVOffset = N->getSrcValueOffset();
1026 unsigned Alignment = N->getAlignment();
1027 bool isVolatile = N->isVolatile();
1029 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1031 if (N->getMemoryVT().bitsLE(NVT)) {
1032 MVT EVT = N->getMemoryVT();
1034 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1035 isVolatile, Alignment);
1037 // Remember the chain.
1038 Ch = Lo.getValue(1);
1040 if (ExtType == ISD::SEXTLOAD) {
1041 // The high part is obtained by SRA'ing all but one of the bits of the
1043 unsigned LoSize = Lo.getValueType().getSizeInBits();
1044 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1045 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1046 } else if (ExtType == ISD::ZEXTLOAD) {
1047 // The high part is just a zero.
1048 Hi = DAG.getConstant(0, NVT);
1050 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1051 // The high part is undefined.
1052 Hi = DAG.getNode(ISD::UNDEF, NVT);
1054 } else if (TLI.isLittleEndian()) {
1055 // Little-endian - low bits are at low addresses.
1056 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1057 isVolatile, Alignment);
1059 unsigned ExcessBits =
1060 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1061 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1063 // Increment the pointer to the other half.
1064 unsigned IncrementSize = NVT.getSizeInBits()/8;
1065 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1066 DAG.getIntPtrConstant(IncrementSize));
1067 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1068 SVOffset+IncrementSize, NEVT,
1069 isVolatile, MinAlign(Alignment, IncrementSize));
1071 // Build a factor node to remember that this load is independent of the
1073 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1076 // Big-endian - high bits are at low addresses. Favor aligned loads at
1077 // the cost of some bit-fiddling.
1078 MVT EVT = N->getMemoryVT();
1079 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1080 unsigned IncrementSize = NVT.getSizeInBits()/8;
1081 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1083 // Load both the high bits and maybe some of the low bits.
1084 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1085 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1086 isVolatile, Alignment);
1088 // Increment the pointer to the other half.
1089 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1090 DAG.getIntPtrConstant(IncrementSize));
1091 // Load the rest of the low bits.
1092 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1093 SVOffset+IncrementSize,
1094 MVT::getIntegerVT(ExcessBits),
1095 isVolatile, MinAlign(Alignment, IncrementSize));
1097 // Build a factor node to remember that this load is independent of the
1099 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1102 if (ExcessBits < NVT.getSizeInBits()) {
1103 // Transfer low bits from the bottom of Hi to the top of Lo.
1104 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1105 DAG.getNode(ISD::SHL, NVT, Hi,
1106 DAG.getConstant(ExcessBits,
1107 TLI.getShiftAmountTy())));
1108 // Move high bits to the right position in Hi.
1109 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1110 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1111 TLI.getShiftAmountTy()));
1115 // Legalized the chain result - switch anything that used the old chain to
1117 ReplaceValueWith(SDOperand(N, 1), Ch);
1120 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1121 SDOperand &Lo, SDOperand &Hi) {
1122 SDOperand LL, LH, RL, RH;
1123 GetExpandedInteger(N->getOperand(0), LL, LH);
1124 GetExpandedInteger(N->getOperand(1), RL, RH);
1125 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1126 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1129 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1130 SDOperand &Lo, SDOperand &Hi) {
1131 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1132 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1133 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1136 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1137 SDOperand &Lo, SDOperand &Hi) {
1138 // Expand the subcomponents.
1139 SDOperand LHSL, LHSH, RHSL, RHSH;
1140 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1141 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1142 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1143 SDOperand LoOps[2] = { LHSL, RHSL };
1144 SDOperand HiOps[3] = { LHSH, RHSH };
1146 if (N->getOpcode() == ISD::ADD) {
1147 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1148 HiOps[2] = Lo.getValue(1);
1149 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1151 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1152 HiOps[2] = Lo.getValue(1);
1153 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1157 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1158 SDOperand &Lo, SDOperand &Hi) {
1159 // Expand the subcomponents.
1160 SDOperand LHSL, LHSH, RHSL, RHSH;
1161 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1162 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1163 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1164 SDOperand LoOps[2] = { LHSL, RHSL };
1165 SDOperand HiOps[3] = { LHSH, RHSH };
1167 if (N->getOpcode() == ISD::ADDC) {
1168 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1169 HiOps[2] = Lo.getValue(1);
1170 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1172 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1173 HiOps[2] = Lo.getValue(1);
1174 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1177 // Legalized the flag result - switch anything that used the old flag to
1179 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1182 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1183 SDOperand &Lo, SDOperand &Hi) {
1184 // Expand the subcomponents.
1185 SDOperand LHSL, LHSH, RHSL, RHSH;
1186 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1187 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1188 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1189 SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1190 SDOperand HiOps[3] = { LHSH, RHSH };
1192 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1193 HiOps[2] = Lo.getValue(1);
1194 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1196 // Legalized the flag result - switch anything that used the old flag to
1198 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1201 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1202 SDOperand &Lo, SDOperand &Hi) {
1203 MVT VT = N->getValueType(0);
1204 MVT NVT = TLI.getTypeToTransformTo(VT);
1206 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1207 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1208 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1209 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1210 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1211 SDOperand LL, LH, RL, RH;
1212 GetExpandedInteger(N->getOperand(0), LL, LH);
1213 GetExpandedInteger(N->getOperand(1), RL, RH);
1214 unsigned OuterBitSize = VT.getSizeInBits();
1215 unsigned InnerBitSize = NVT.getSizeInBits();
1216 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1217 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1219 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1220 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1221 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1222 // The inputs are both zero-extended.
1224 // We can emit a umul_lohi.
1225 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1226 Hi = SDOperand(Lo.Val, 1);
1230 // We can emit a mulhu+mul.
1231 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1232 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1236 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1237 // The input values are both sign-extended.
1239 // We can emit a smul_lohi.
1240 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1241 Hi = SDOperand(Lo.Val, 1);
1245 // We can emit a mulhs+mul.
1246 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1247 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1252 // Lo,Hi = umul LHS, RHS.
1253 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1254 DAG.getVTList(NVT, NVT), LL, RL);
1256 Hi = UMulLOHI.getValue(1);
1257 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1258 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1259 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1260 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1264 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1265 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1266 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1267 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1268 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1269 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1274 // If nothing else, we can make a libcall.
1276 switch (VT.getSimpleVT()) {
1278 assert(false && "Unsupported MUL!");
1280 LC = RTLIB::MUL_I64;
1284 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1285 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi);
1288 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1289 SDOperand &Lo, SDOperand &Hi) {
1290 assert(N->getValueType(0) == MVT::i64 && "Unsupported sdiv!");
1291 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1292 SplitInteger(MakeLibCall(RTLIB::SDIV_I64, N->getValueType(0), Ops, 2, true),
1296 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1297 SDOperand &Lo, SDOperand &Hi) {
1298 assert(N->getValueType(0) == MVT::i64 && "Unsupported srem!");
1299 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1300 SplitInteger(MakeLibCall(RTLIB::SREM_I64, N->getValueType(0), Ops, 2, true),
1304 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1305 SDOperand &Lo, SDOperand &Hi) {
1306 assert(N->getValueType(0) == MVT::i64 && "Unsupported udiv!");
1307 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1308 SplitInteger(MakeLibCall(RTLIB::UDIV_I64, N->getValueType(0), Ops, 2, false),
1312 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1313 SDOperand &Lo, SDOperand &Hi) {
1314 assert(N->getValueType(0) == MVT::i64 && "Unsupported urem!");
1315 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1316 SplitInteger(MakeLibCall(RTLIB::UREM_I64, N->getValueType(0), Ops, 2, false),
1320 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1321 SDOperand &Lo, SDOperand &Hi) {
1322 MVT VT = N->getValueType(0);
1324 // If we can emit an efficient shift operation, do so now. Check to see if
1325 // the RHS is a constant.
1326 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1327 return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi);
1329 // If we can determine that the high bit of the shift is zero or one, even if
1330 // the low bits are variable, emit this shift in an optimized form.
1331 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1334 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1336 if (N->getOpcode() == ISD::SHL) {
1337 PartsOpc = ISD::SHL_PARTS;
1338 } else if (N->getOpcode() == ISD::SRL) {
1339 PartsOpc = ISD::SRL_PARTS;
1341 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1342 PartsOpc = ISD::SRA_PARTS;
1345 // Next check to see if the target supports this SHL_PARTS operation or if it
1346 // will custom expand it.
1347 MVT NVT = TLI.getTypeToTransformTo(VT);
1348 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1349 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1350 Action == TargetLowering::Custom) {
1351 // Expand the subcomponents.
1352 SDOperand LHSL, LHSH;
1353 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1355 SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) };
1356 MVT VT = LHSL.getValueType();
1357 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1358 Hi = Lo.getValue(1);
1362 // Otherwise, emit a libcall.
1363 assert(VT == MVT::i64 && "Unsupported shift!");
1367 if (N->getOpcode() == ISD::SHL) {
1368 LC = RTLIB::SHL_I64;
1369 isSigned = false; /*sign irrelevant*/
1370 } else if (N->getOpcode() == ISD::SRL) {
1371 LC = RTLIB::SRL_I64;
1374 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1375 LC = RTLIB::SRA_I64;
1379 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1380 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1383 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1384 SDOperand &Lo, SDOperand &Hi) {
1385 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1386 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1387 MVT NVT = Lo.getValueType();
1389 SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1390 DAG.getConstant(0, NVT), ISD::SETNE);
1392 SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1393 SDOperand HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1395 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1396 DAG.getNode(ISD::ADD, NVT, LoLZ,
1397 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1398 Hi = DAG.getConstant(0, NVT);
1401 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1402 SDOperand &Lo, SDOperand &Hi) {
1403 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1404 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1405 MVT NVT = Lo.getValueType();
1406 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1407 DAG.getNode(ISD::CTPOP, NVT, Hi));
1408 Hi = DAG.getConstant(0, NVT);
1411 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1412 SDOperand &Lo, SDOperand &Hi) {
1413 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1414 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1415 MVT NVT = Lo.getValueType();
1417 SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1418 DAG.getConstant(0, NVT), ISD::SETNE);
1420 SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1421 SDOperand HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1423 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1424 DAG.getNode(ISD::ADD, NVT, HiLZ,
1425 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1426 Hi = DAG.getConstant(0, NVT);
1429 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1430 /// and the shift amount is a constant 'Amt'. Expand the operation.
1431 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1432 SDOperand &Lo, SDOperand &Hi) {
1433 // Expand the incoming operand to be shifted, so that we have its parts
1435 GetExpandedInteger(N->getOperand(0), InL, InH);
1437 MVT NVT = InL.getValueType();
1438 unsigned VTBits = N->getValueType(0).getSizeInBits();
1439 unsigned NVTBits = NVT.getSizeInBits();
1440 MVT ShTy = N->getOperand(1).getValueType();
1442 if (N->getOpcode() == ISD::SHL) {
1444 Lo = Hi = DAG.getConstant(0, NVT);
1445 } else if (Amt > NVTBits) {
1446 Lo = DAG.getConstant(0, NVT);
1447 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1448 } else if (Amt == NVTBits) {
1449 Lo = DAG.getConstant(0, NVT);
1452 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
1453 Hi = DAG.getNode(ISD::OR, NVT,
1454 DAG.getNode(ISD::SHL, NVT, InH,
1455 DAG.getConstant(Amt, ShTy)),
1456 DAG.getNode(ISD::SRL, NVT, InL,
1457 DAG.getConstant(NVTBits-Amt, ShTy)));
1462 if (N->getOpcode() == ISD::SRL) {
1464 Lo = DAG.getConstant(0, NVT);
1465 Hi = DAG.getConstant(0, NVT);
1466 } else if (Amt > NVTBits) {
1467 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1468 Hi = DAG.getConstant(0, NVT);
1469 } else if (Amt == NVTBits) {
1471 Hi = DAG.getConstant(0, NVT);
1473 Lo = DAG.getNode(ISD::OR, NVT,
1474 DAG.getNode(ISD::SRL, NVT, InL,
1475 DAG.getConstant(Amt, ShTy)),
1476 DAG.getNode(ISD::SHL, NVT, InH,
1477 DAG.getConstant(NVTBits-Amt, ShTy)));
1478 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
1483 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1485 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1486 DAG.getConstant(NVTBits-1, ShTy));
1487 } else if (Amt > NVTBits) {
1488 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1489 DAG.getConstant(Amt-NVTBits, ShTy));
1490 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1491 DAG.getConstant(NVTBits-1, ShTy));
1492 } else if (Amt == NVTBits) {
1494 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1495 DAG.getConstant(NVTBits-1, ShTy));
1497 Lo = DAG.getNode(ISD::OR, NVT,
1498 DAG.getNode(ISD::SRL, NVT, InL,
1499 DAG.getConstant(Amt, ShTy)),
1500 DAG.getNode(ISD::SHL, NVT, InH,
1501 DAG.getConstant(NVTBits-Amt, ShTy)));
1502 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
1506 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1507 /// this shift based on knowledge of the high bit of the shift amount. If we
1508 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1510 bool DAGTypeLegalizer::
1511 ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
1512 SDOperand Amt = N->getOperand(1);
1513 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1514 MVT ShTy = Amt.getValueType();
1515 unsigned ShBits = ShTy.getSizeInBits();
1516 unsigned NVTBits = NVT.getSizeInBits();
1517 assert(isPowerOf2_32(NVTBits) &&
1518 "Expanded integer type size not a power of two!");
1520 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1521 APInt KnownZero, KnownOne;
1522 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1524 // If we don't know anything about the high bits, exit.
1525 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1528 // Get the incoming operand to be shifted.
1530 GetExpandedInteger(N->getOperand(0), InL, InH);
1532 // If we know that any of the high bits of the shift amount are one, then we
1533 // can do this as a couple of simple shifts.
1534 if (KnownOne.intersects(HighBitMask)) {
1535 // Mask out the high bit, which we know is set.
1536 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1537 DAG.getConstant(~HighBitMask, ShTy));
1539 switch (N->getOpcode()) {
1540 default: assert(0 && "Unknown shift");
1542 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1543 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1546 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1547 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1550 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1551 DAG.getConstant(NVTBits-1, ShTy));
1552 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1557 // If we know that all of the high bits of the shift amount are zero, then we
1558 // can do this as a couple of simple shifts.
1559 if ((KnownZero & HighBitMask) == HighBitMask) {
1561 SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
1562 DAG.getConstant(NVTBits, ShTy),
1565 switch (N->getOpcode()) {
1566 default: assert(0 && "Unknown shift");
1567 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1569 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1572 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1573 Hi = DAG.getNode(ISD::OR, NVT,
1574 DAG.getNode(Op1, NVT, InH, Amt),
1575 DAG.getNode(Op2, NVT, InL, Amt2));
1583 //===----------------------------------------------------------------------===//
1584 // Integer Operand Expansion
1585 //===----------------------------------------------------------------------===//
1587 /// ExpandIntegerOperand - This method is called when the specified operand of
1588 /// the specified node is found to need expansion. At this point, all of the
1589 /// result types of the node are known to be legal, but other operands of the
1590 /// node may need promotion or expansion as well as the specified one.
1591 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1592 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1593 SDOperand Res(0, 0);
1595 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1596 == TargetLowering::Custom)
1597 Res = TLI.LowerOperation(SDOperand(N, 0), DAG);
1600 switch (N->getOpcode()) {
1603 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1604 N->dump(&DAG); cerr << "\n";
1606 assert(0 && "Do not know how to expand this operator's operand!");
1609 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1610 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1611 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1613 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1615 case ISD::SINT_TO_FP:
1616 Res = ExpandIntOp_SINT_TO_FP(N->getOperand(0), N->getValueType(0));
1618 case ISD::UINT_TO_FP:
1619 Res = ExpandIntOp_UINT_TO_FP(N->getOperand(0), N->getValueType(0));
1622 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1623 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1624 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1627 Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1632 // If the result is null, the sub-method took care of registering results etc.
1633 if (!Res.Val) return false;
1634 // If the result is N, the sub-method updated N in place. Check to see if any
1635 // operands are new, and if so, mark them.
1637 // Mark N as new and remark N and its operands. This allows us to correctly
1638 // revisit N if it needs another step of expansion and allows us to visit
1639 // any new operands to N.
1644 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1645 "Invalid operand expansion");
1647 ReplaceValueWith(SDOperand(N, 0), Res);
1651 SDOperand DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
1653 GetExpandedInteger(N->getOperand(0), InL, InH);
1654 // Just truncate the low part of the source.
1655 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
1658 SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDOperand Source,
1660 // We know the destination is legal, but that the input needs to be expanded.
1661 MVT SourceVT = Source.getValueType();
1663 // Check to see if the target has a custom way to lower this. If so, use it.
1664 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
1665 default: assert(0 && "This action not implemented for this operation!");
1666 case TargetLowering::Legal:
1667 case TargetLowering::Expand:
1668 break; // This case is handled below.
1669 case TargetLowering::Custom:
1670 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
1672 if (NV.Val) return NV;
1673 break; // The target lowered this.
1676 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1677 if (SourceVT == MVT::i64) {
1678 if (DestTy == MVT::f32)
1679 LC = RTLIB::SINTTOFP_I64_F32;
1681 assert(DestTy == MVT::f64 && "Unknown fp value type!");
1682 LC = RTLIB::SINTTOFP_I64_F64;
1684 } else if (SourceVT == MVT::i128) {
1685 if (DestTy == MVT::f32)
1686 LC = RTLIB::SINTTOFP_I128_F32;
1687 else if (DestTy == MVT::f64)
1688 LC = RTLIB::SINTTOFP_I128_F64;
1689 else if (DestTy == MVT::f80)
1690 LC = RTLIB::SINTTOFP_I128_F80;
1692 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
1693 LC = RTLIB::SINTTOFP_I128_PPCF128;
1696 assert(0 && "Unknown int value type!");
1699 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
1700 "Don't know how to expand this SINT_TO_FP!");
1701 return MakeLibCall(LC, DestTy, &Source, 1, true);
1704 SDOperand DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDOperand Source,
1706 // We know the destination is legal, but that the input needs to be expanded.
1707 assert(getTypeAction(Source.getValueType()) == ExpandInteger &&
1708 "This is not an expansion!");
1710 // If this is unsigned, and not supported, first perform the conversion to
1711 // signed, then adjust the result if the sign bit is set.
1712 SDOperand SignedConv = ExpandIntOp_SINT_TO_FP(Source, DestTy);
1714 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
1715 // incoming integer is set. To handle this, we dynamically test to see if
1716 // it is set, and, if so, add a fudge factor.
1718 GetExpandedInteger(Source, Lo, Hi);
1720 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1721 DAG.getConstant(0, Hi.getValueType()),
1723 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
1724 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
1725 SignSet, Four, Zero);
1726 uint64_t FF = 0x5f800000ULL;
1727 if (TLI.isLittleEndian()) FF <<= 32;
1728 Constant *FudgeFactor = ConstantInt::get((Type*)Type::Int64Ty, FF);
1730 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
1731 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
1732 SDOperand FudgeInReg;
1733 if (DestTy == MVT::f32)
1734 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
1735 else if (DestTy.bitsGT(MVT::f32))
1736 // FIXME: Avoid the extend by construction the right constantpool?
1737 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
1738 CPIdx, NULL, 0, MVT::f32);
1740 assert(0 && "Unexpected conversion");
1742 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
1745 SDOperand DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
1746 SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1747 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1748 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1750 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1751 // against zero to select between true and false values.
1752 if (NewRHS.Val == 0) {
1753 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1754 CCCode = ISD::SETNE;
1757 // Update N to have the operands specified.
1758 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
1759 DAG.getCondCode(CCCode), NewLHS, NewRHS,
1763 SDOperand DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
1764 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1765 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
1766 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1768 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1769 // against zero to select between true and false values.
1770 if (NewRHS.Val == 0) {
1771 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1772 CCCode = ISD::SETNE;
1775 // Update N to have the operands specified.
1776 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1777 N->getOperand(2), N->getOperand(3),
1778 DAG.getCondCode(CCCode));
1781 SDOperand DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
1782 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1783 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1784 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1786 // If ExpandSetCCOperands returned a scalar, use it.
1787 if (NewRHS.Val == 0) {
1788 assert(NewLHS.getValueType() == N->getValueType(0) &&
1789 "Unexpected setcc expansion!");
1793 // Otherwise, update N to have the operands specified.
1794 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1795 DAG.getCondCode(CCCode));
1798 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1799 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1800 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDOperand &NewLHS,
1802 ISD::CondCode &CCCode) {
1803 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1804 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1805 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1807 MVT VT = NewLHS.getValueType();
1809 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1810 if (RHSLo == RHSHi) {
1811 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1812 if (RHSCST->isAllOnesValue()) {
1813 // Equality comparison to -1.
1814 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1821 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1822 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1823 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1824 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1828 // If this is a comparison of the sign bit, just look at the top part.
1830 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1831 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1832 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1838 // FIXME: This generated code sucks.
1839 ISD::CondCode LowCC;
1841 default: assert(0 && "Unknown integer setcc!");
1843 case ISD::SETULT: LowCC = ISD::SETULT; break;
1845 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1847 case ISD::SETULE: LowCC = ISD::SETULE; break;
1849 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1852 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1853 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1854 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1856 // NOTE: on targets without efficient SELECT of bools, we can always use
1857 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1858 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1859 SDOperand Tmp1, Tmp2;
1860 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
1861 false, DagCombineInfo);
1863 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
1864 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1865 CCCode, false, DagCombineInfo);
1867 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1868 DAG.getCondCode(CCCode));
1870 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
1871 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
1872 if ((Tmp1C && Tmp1C->isNullValue()) ||
1873 (Tmp2C && Tmp2C->isNullValue() &&
1874 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1875 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1876 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
1877 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1878 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1879 // low part is known false, returns high part.
1880 // For LE / GE, if high part is known false, ignore the low part.
1881 // For LT / GT, if high part is known true, ignore the low part.
1883 NewRHS = SDOperand();
1887 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1888 ISD::SETEQ, false, DagCombineInfo);
1890 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1892 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1893 NewLHS, Tmp1, Tmp2);
1894 NewRHS = SDOperand();
1897 SDOperand DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
1898 if (ISD::isNormalStore(N))
1899 return ExpandOp_NormalStore(N, OpNo);
1901 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1902 assert(OpNo == 1 && "Can only expand the stored value so far");
1904 MVT VT = N->getOperand(1).getValueType();
1905 MVT NVT = TLI.getTypeToTransformTo(VT);
1906 SDOperand Ch = N->getChain();
1907 SDOperand Ptr = N->getBasePtr();
1908 int SVOffset = N->getSrcValueOffset();
1909 unsigned Alignment = N->getAlignment();
1910 bool isVolatile = N->isVolatile();
1913 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1915 if (N->getMemoryVT().bitsLE(NVT)) {
1916 GetExpandedInteger(N->getValue(), Lo, Hi);
1917 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1918 N->getMemoryVT(), isVolatile, Alignment);
1919 } else if (TLI.isLittleEndian()) {
1920 // Little-endian - low bits are at low addresses.
1921 GetExpandedInteger(N->getValue(), Lo, Hi);
1923 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1924 isVolatile, Alignment);
1926 unsigned ExcessBits =
1927 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1928 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1930 // Increment the pointer to the other half.
1931 unsigned IncrementSize = NVT.getSizeInBits()/8;
1932 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1933 DAG.getIntPtrConstant(IncrementSize));
1934 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1935 SVOffset+IncrementSize, NEVT,
1936 isVolatile, MinAlign(Alignment, IncrementSize));
1937 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1939 // Big-endian - high bits are at low addresses. Favor aligned stores at
1940 // the cost of some bit-fiddling.
1941 GetExpandedInteger(N->getValue(), Lo, Hi);
1943 MVT EVT = N->getMemoryVT();
1944 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1945 unsigned IncrementSize = NVT.getSizeInBits()/8;
1946 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1947 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
1949 if (ExcessBits < NVT.getSizeInBits()) {
1950 // Transfer high bits from the top of Lo to the bottom of Hi.
1951 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
1952 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1953 TLI.getShiftAmountTy()));
1954 Hi = DAG.getNode(ISD::OR, NVT, Hi,
1955 DAG.getNode(ISD::SRL, NVT, Lo,
1956 DAG.getConstant(ExcessBits,
1957 TLI.getShiftAmountTy())));
1960 // Store both the high bits and maybe some of the low bits.
1961 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1962 SVOffset, HiVT, isVolatile, Alignment);
1964 // Increment the pointer to the other half.
1965 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1966 DAG.getIntPtrConstant(IncrementSize));
1967 // Store the lowest ExcessBits bits in the second half.
1968 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
1969 SVOffset+IncrementSize,
1970 MVT::getIntegerVT(ExcessBits),
1971 isVolatile, MinAlign(Alignment, IncrementSize));
1972 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);