1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37 SDValue Res = SDValue();
39 // See if the target wants to custom expand this node.
40 if (CustomLowerNode(N, N->getValueType(ResNo), true))
43 switch (N->getOpcode()) {
46 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47 N->dump(&DAG); dbgs() << "\n";
49 llvm_unreachable("Do not know how to promote this operator!");
50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
52 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
56 case ISD::CONVERT_RNDSAT:
57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
61 case ISD::EXTRACT_VECTOR_ELT:
62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
68 case ISD::SIGN_EXTEND_INREG:
69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
76 case ISD::SIGN_EXTEND:
77 case ISD::ZERO_EXTEND:
78 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
81 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
83 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
90 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
93 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
96 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
99 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
101 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
103 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
105 case ISD::ATOMIC_LOAD_ADD:
106 case ISD::ATOMIC_LOAD_SUB:
107 case ISD::ATOMIC_LOAD_AND:
108 case ISD::ATOMIC_LOAD_OR:
109 case ISD::ATOMIC_LOAD_XOR:
110 case ISD::ATOMIC_LOAD_NAND:
111 case ISD::ATOMIC_LOAD_MIN:
112 case ISD::ATOMIC_LOAD_MAX:
113 case ISD::ATOMIC_LOAD_UMIN:
114 case ISD::ATOMIC_LOAD_UMAX:
115 case ISD::ATOMIC_SWAP:
116 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
118 case ISD::ATOMIC_CMP_SWAP:
119 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
122 // If the result is null then the sub-method took care of registering it.
124 SetPromotedInteger(SDValue(N, ResNo), Res);
127 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
128 // Sign-extend the new bits, and continue the assertion.
129 SDValue Op = SExtPromotedInteger(N->getOperand(0));
130 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
131 Op.getValueType(), Op, N->getOperand(1));
134 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
135 // Zero the new bits, and continue the assertion.
136 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
137 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
138 Op.getValueType(), Op, N->getOperand(1));
141 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
142 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
143 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
145 N->getChain(), N->getBasePtr(),
146 Op2, N->getSrcValue(), N->getAlignment());
147 // Legalized the chain result - switch anything that used the old chain to
149 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
153 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
154 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
155 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
156 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
157 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
158 Op2, Op3, N->getSrcValue(), N->getAlignment());
159 // Legalized the chain result - switch anything that used the old chain to
161 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
165 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
166 SDValue InOp = N->getOperand(0);
167 EVT InVT = InOp.getValueType();
168 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
169 EVT OutVT = N->getValueType(0);
170 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
171 DebugLoc dl = N->getDebugLoc();
173 switch (getTypeAction(InVT)) {
175 assert(false && "Unknown type action!");
180 if (NOutVT.bitsEq(NInVT))
181 // The input promotes to the same size. Convert the promoted value.
182 return DAG.getNode(ISD::BIT_CONVERT, dl,
183 NOutVT, GetPromotedInteger(InOp));
186 // Promote the integer operand by hand.
187 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
191 case ScalarizeVector:
192 // Convert the element to an integer and promote it by hand.
193 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
194 BitConvertToInteger(GetScalarizedVector(InOp)));
196 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
197 // pieces of the input into integers and reassemble in the final type.
199 GetSplitVector(N->getOperand(0), Lo, Hi);
200 Lo = BitConvertToInteger(Lo);
201 Hi = BitConvertToInteger(Hi);
203 if (TLI.isBigEndian())
206 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
207 EVT::getIntegerVT(*DAG.getContext(),
208 NOutVT.getSizeInBits()),
209 JoinIntegers(Lo, Hi));
210 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
213 if (OutVT.bitsEq(NInVT))
214 // The input is widened to the same size. Convert to the widened value.
215 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
218 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
219 CreateStackStoreLoad(InOp, OutVT));
222 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
223 SDValue Op = GetPromotedInteger(N->getOperand(0));
224 EVT OVT = N->getValueType(0);
225 EVT NVT = Op.getValueType();
226 DebugLoc dl = N->getDebugLoc();
228 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
229 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
230 DAG.getConstant(DiffBits, TLI.getPointerTy()));
233 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
234 // The pair element type may be legal, or may not promote to the same type as
235 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
236 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
237 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
238 JoinIntegers(N->getOperand(0), N->getOperand(1)));
241 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
242 EVT VT = N->getValueType(0);
243 // FIXME there is no actual debug info here
244 DebugLoc dl = N->getDebugLoc();
245 // Zero extend things like i1, sign extend everything else. It shouldn't
246 // matter in theory which one we pick, but this tends to give better code?
247 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
248 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(*DAG.getContext(), VT),
250 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
254 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
255 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
256 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
257 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
258 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
259 "can only promote integers");
260 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
261 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
262 N->getOperand(1), N->getOperand(2),
263 N->getOperand(3), N->getOperand(4), CvtCode);
266 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
267 // Zero extend to the promoted type and do the count there.
268 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
269 DebugLoc dl = N->getDebugLoc();
270 EVT OVT = N->getValueType(0);
271 EVT NVT = Op.getValueType();
272 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
273 // Subtract off the extra leading bits in the bigger type.
274 return DAG.getNode(ISD::SUB, dl, NVT, Op,
275 DAG.getConstant(NVT.getSizeInBits() -
276 OVT.getSizeInBits(), NVT));
279 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
280 // Zero extend to the promoted type and do the count there.
281 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
282 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
285 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
286 SDValue Op = GetPromotedInteger(N->getOperand(0));
287 EVT OVT = N->getValueType(0);
288 EVT NVT = Op.getValueType();
289 DebugLoc dl = N->getDebugLoc();
290 // The count is the same in the promoted type except if the original
291 // value was zero. This can be handled by setting the bit just off
292 // the top of the original type.
293 APInt TopBit(NVT.getSizeInBits(), 0);
294 TopBit.set(OVT.getSizeInBits());
295 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
296 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
299 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
300 DebugLoc dl = N->getDebugLoc();
301 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
302 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
306 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
307 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
308 unsigned NewOpc = N->getOpcode();
309 DebugLoc dl = N->getDebugLoc();
311 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
312 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
313 // and SINT conversions are Custom, there is no way to tell which is preferable.
314 // We choose SINT because that's the right thing on PPC.)
315 if (N->getOpcode() == ISD::FP_TO_UINT &&
316 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
317 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
318 NewOpc = ISD::FP_TO_SINT;
320 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
322 // Assert that the converted value fits in the original type. If it doesn't
323 // (eg: because the value being converted is too big), then the result of the
324 // original operation was undefined anyway, so the assert is still correct.
325 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
326 ISD::AssertZext : ISD::AssertSext, dl,
327 NVT, Res, DAG.getValueType(N->getValueType(0)));
330 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
331 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
332 DebugLoc dl = N->getDebugLoc();
334 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
336 return DAG.getNode(ISD::AssertZext, dl,
337 NVT, Res, DAG.getValueType(N->getValueType(0)));
340 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
341 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
342 DebugLoc dl = N->getDebugLoc();
344 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
345 SDValue Res = GetPromotedInteger(N->getOperand(0));
346 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
348 // If the result and operand types are the same after promotion, simplify
349 // to an in-register extension.
350 if (NVT == Res.getValueType()) {
351 // The high bits are not guaranteed to be anything. Insert an extend.
352 if (N->getOpcode() == ISD::SIGN_EXTEND)
353 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
354 DAG.getValueType(N->getOperand(0).getValueType()));
355 if (N->getOpcode() == ISD::ZERO_EXTEND)
356 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
357 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
362 // Otherwise, just extend the original operand all the way to the larger type.
363 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
366 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
367 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
368 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
369 ISD::LoadExtType ExtType =
370 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
371 DebugLoc dl = N->getDebugLoc();
372 SDValue Res = DAG.getExtLoad(ExtType, NVT, dl, N->getChain(), N->getBasePtr(),
373 N->getSrcValue(), N->getSrcValueOffset(),
374 N->getMemoryVT(), N->isVolatile(),
375 N->isNonTemporal(), N->getAlignment());
377 // Legalized the chain result - switch anything that used the old chain to
379 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
383 /// Promote the overflow flag of an overflowing arithmetic node.
384 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
385 // Simply change the return type of the boolean result.
386 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
387 EVT ValueVTs[] = { N->getValueType(0), NVT };
388 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
389 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
390 DAG.getVTList(ValueVTs, 2), Ops, 2);
392 // Modified the sum result - switch anything that used the old sum to use
394 ReplaceValueWith(SDValue(N, 0), Res);
396 return SDValue(Res.getNode(), 1);
399 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
401 return PromoteIntRes_Overflow(N);
403 // The operation overflowed iff the result in the larger type is not the
404 // sign extension of its truncation to the original type.
405 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
406 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
407 EVT OVT = N->getOperand(0).getValueType();
408 EVT NVT = LHS.getValueType();
409 DebugLoc dl = N->getDebugLoc();
411 // Do the arithmetic in the larger type.
412 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
413 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
415 // Calculate the overflow flag: sign extend the arithmetic result from
416 // the original type.
417 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
418 DAG.getValueType(OVT));
419 // Overflowed if and only if this is not equal to Res.
420 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
422 // Use the calculated overflow everywhere.
423 ReplaceValueWith(SDValue(N, 1), Ofl);
428 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
429 // Sign extend the input.
430 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
431 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
432 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
433 LHS.getValueType(), LHS, RHS);
436 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
437 SDValue LHS = GetPromotedInteger(N->getOperand(1));
438 SDValue RHS = GetPromotedInteger(N->getOperand(2));
439 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
440 LHS.getValueType(), N->getOperand(0),LHS,RHS);
443 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
444 SDValue LHS = GetPromotedInteger(N->getOperand(2));
445 SDValue RHS = GetPromotedInteger(N->getOperand(3));
446 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
447 LHS.getValueType(), N->getOperand(0),
448 N->getOperand(1), LHS, RHS, N->getOperand(4));
451 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
452 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
453 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
454 DebugLoc dl = N->getDebugLoc();
456 // Get the SETCC result using the canonical SETCC type.
457 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
458 N->getOperand(1), N->getOperand(2));
460 // Convert to the expected type.
461 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
462 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
463 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
466 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
467 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
468 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
469 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
472 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
473 SDValue Op = GetPromotedInteger(N->getOperand(0));
474 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
475 Op.getValueType(), Op, N->getOperand(1));
478 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
479 // The input may have strange things in the top bits of the registers, but
480 // these operations don't care. They may have weird bits going out, but
481 // that too is okay if they are integer operations.
482 SDValue LHS = GetPromotedInteger(N->getOperand(0));
483 SDValue RHS = GetPromotedInteger(N->getOperand(1));
484 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
485 LHS.getValueType(), LHS, RHS);
488 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
489 // The input value must be properly sign extended.
490 SDValue Res = SExtPromotedInteger(N->getOperand(0));
491 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
492 Res.getValueType(), Res, N->getOperand(1));
495 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
496 // The input value must be properly zero extended.
497 EVT VT = N->getValueType(0);
498 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
499 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
500 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
503 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
504 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
507 switch (getTypeAction(N->getOperand(0).getValueType())) {
508 default: llvm_unreachable("Unknown type action!");
511 Res = N->getOperand(0);
514 Res = GetPromotedInteger(N->getOperand(0));
518 // Truncate to NVT instead of VT
519 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
522 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
524 return PromoteIntRes_Overflow(N);
526 // The operation overflowed iff the result in the larger type is not the
527 // zero extension of its truncation to the original type.
528 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
529 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
530 EVT OVT = N->getOperand(0).getValueType();
531 EVT NVT = LHS.getValueType();
532 DebugLoc dl = N->getDebugLoc();
534 // Do the arithmetic in the larger type.
535 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
536 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
538 // Calculate the overflow flag: zero extend the arithmetic result from
539 // the original type.
540 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
541 // Overflowed if and only if this is not equal to Res.
542 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
544 // Use the calculated overflow everywhere.
545 ReplaceValueWith(SDValue(N, 1), Ofl);
550 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
551 // Zero extend the input.
552 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
553 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
554 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
555 LHS.getValueType(), LHS, RHS);
558 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
559 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
560 N->getValueType(0)));
563 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
564 SDValue Chain = N->getOperand(0); // Get the chain.
565 SDValue Ptr = N->getOperand(1); // Get the pointer.
566 EVT VT = N->getValueType(0);
567 DebugLoc dl = N->getDebugLoc();
569 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
570 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
571 // The argument is passed as NumRegs registers of type RegVT.
573 SmallVector<SDValue, 8> Parts(NumRegs);
574 for (unsigned i = 0; i < NumRegs; ++i) {
575 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
576 N->getConstantOperandVal(3));
577 Chain = Parts[i].getValue(1);
580 // Handle endianness of the load.
581 if (TLI.isBigEndian())
582 std::reverse(Parts.begin(), Parts.end());
584 // Assemble the parts in the promoted type.
585 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
586 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
587 for (unsigned i = 1; i < NumRegs; ++i) {
588 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
589 // Shift it to the right position and "or" it in.
590 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
591 DAG.getConstant(i * RegVT.getSizeInBits(),
592 TLI.getPointerTy()));
593 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
596 // Modified the chain result - switch anything that used the old chain to
598 ReplaceValueWith(SDValue(N, 1), Chain);
603 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
604 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
605 return PromoteIntRes_Overflow(N);
608 //===----------------------------------------------------------------------===//
609 // Integer Operand Promotion
610 //===----------------------------------------------------------------------===//
612 /// PromoteIntegerOperand - This method is called when the specified operand of
613 /// the specified node is found to need promotion. At this point, all of the
614 /// result types of the node are known to be legal, but other operands of the
615 /// node may need promotion or expansion as well as the specified one.
616 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
617 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
618 SDValue Res = SDValue();
620 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
623 switch (N->getOpcode()) {
626 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
627 N->dump(&DAG); dbgs() << "\n";
629 llvm_unreachable("Do not know how to promote this operator's operand!");
631 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
632 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
633 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
634 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
635 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
636 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
637 case ISD::CONVERT_RNDSAT:
638 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
639 case ISD::INSERT_VECTOR_ELT:
640 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
641 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
642 case ISD::SCALAR_TO_VECTOR:
643 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
644 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
645 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
646 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
647 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
648 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
649 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
651 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
652 case ISD::FP16_TO_FP32:
653 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
654 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
660 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
663 // If the result is null, the sub-method took care of registering results etc.
664 if (!Res.getNode()) return false;
666 // If the result is N, the sub-method updated N in place. Tell the legalizer
668 if (Res.getNode() == N)
671 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
672 "Invalid operand expansion");
674 ReplaceValueWith(SDValue(N, 0), Res);
678 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
679 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
680 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
681 ISD::CondCode CCCode) {
682 // We have to insert explicit sign or zero extends. Note that we could
683 // insert sign extends for ALL conditions, but zero extend is cheaper on
684 // many machines (an AND instead of two shifts), so prefer it.
686 default: llvm_unreachable("Unknown integer comparison!");
693 // ALL of these operations will work if we either sign or zero extend
694 // the operands (including the unsigned comparisons!). Zero extend is
695 // usually a simpler/cheaper operation, so prefer it.
696 NewLHS = ZExtPromotedInteger(NewLHS);
697 NewRHS = ZExtPromotedInteger(NewRHS);
703 NewLHS = SExtPromotedInteger(NewLHS);
704 NewRHS = SExtPromotedInteger(NewRHS);
709 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
710 SDValue Op = GetPromotedInteger(N->getOperand(0));
711 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
714 SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) {
715 // This should only occur in unusual situations like bitcasting to an
716 // x86_fp80, so just turn it into a store+load
717 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
720 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
721 assert(OpNo == 2 && "Don't know how to promote this operand!");
723 SDValue LHS = N->getOperand(2);
724 SDValue RHS = N->getOperand(3);
725 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
727 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
729 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
730 N->getOperand(1), LHS, RHS, N->getOperand(4)),
734 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
735 assert(OpNo == 1 && "only know how to promote condition");
737 // Promote all the way up to the canonical SetCC type.
738 EVT SVT = TLI.getSetCCResultType(MVT::Other);
739 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
741 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
742 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
743 N->getOperand(2)), 0);
746 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
747 // Since the result type is legal, the operands must promote to it.
748 EVT OVT = N->getOperand(0).getValueType();
749 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
750 SDValue Hi = GetPromotedInteger(N->getOperand(1));
751 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
752 DebugLoc dl = N->getDebugLoc();
754 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
755 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
756 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
759 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
760 // The vector type is legal but the element type is not. This implies
761 // that the vector is a power-of-two in length and that the element
762 // type does not have a strange size (eg: it is not i1).
763 EVT VecVT = N->getValueType(0);
764 unsigned NumElts = VecVT.getVectorNumElements();
765 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
767 // Promote the inserted value. The type does not need to match the
768 // vector element type. Check that any extra bits introduced will be
770 assert(N->getOperand(0).getValueType().getSizeInBits() >=
771 N->getValueType(0).getVectorElementType().getSizeInBits() &&
772 "Type of inserted value narrower than vector element type!");
774 SmallVector<SDValue, 16> NewOps;
775 for (unsigned i = 0; i < NumElts; ++i)
776 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
778 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
781 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
782 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
783 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
784 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
785 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
786 "can only promote integer arguments");
787 SDValue InOp = GetPromotedInteger(N->getOperand(0));
788 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
789 N->getOperand(1), N->getOperand(2),
790 N->getOperand(3), N->getOperand(4), CvtCode);
793 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
796 // Promote the inserted value. This is valid because the type does not
797 // have to match the vector element type.
799 // Check that any extra bits introduced will be truncated away.
800 assert(N->getOperand(1).getValueType().getSizeInBits() >=
801 N->getValueType(0).getVectorElementType().getSizeInBits() &&
802 "Type of inserted value narrower than vector element type!");
803 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
804 GetPromotedInteger(N->getOperand(1)),
809 assert(OpNo == 2 && "Different operand and result vector types?");
811 // Promote the index.
812 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
813 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
814 N->getOperand(1), Idx), 0);
817 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
819 DebugLoc dl = N->getDebugLoc();
820 NewOps[0] = N->getOperand(0);
821 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
822 SDValue Flag = GetPromotedInteger(N->getOperand(i));
823 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
825 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0);
828 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
829 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
830 // the operand in place.
831 return SDValue(DAG.UpdateNodeOperands(N,
832 GetPromotedInteger(N->getOperand(0))), 0);
835 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
836 assert(OpNo == 0 && "Only know how to promote condition");
838 // Promote all the way up to the canonical SetCC type.
839 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
840 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
842 return SDValue(DAG.UpdateNodeOperands(N, Cond,
843 N->getOperand(1), N->getOperand(2)), 0);
846 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
847 assert(OpNo == 0 && "Don't know how to promote this operand!");
849 SDValue LHS = N->getOperand(0);
850 SDValue RHS = N->getOperand(1);
851 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
853 // The CC (#4) and the possible return values (#2 and #3) have legal types.
854 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
855 N->getOperand(3), N->getOperand(4)), 0);
858 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
859 assert(OpNo == 0 && "Don't know how to promote this operand!");
861 SDValue LHS = N->getOperand(0);
862 SDValue RHS = N->getOperand(1);
863 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
865 // The CC (#2) is always legal.
866 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
869 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
870 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
871 ZExtPromotedInteger(N->getOperand(1))), 0);
874 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
875 SDValue Op = GetPromotedInteger(N->getOperand(0));
876 DebugLoc dl = N->getDebugLoc();
877 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
878 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
879 Op, DAG.getValueType(N->getOperand(0).getValueType()));
882 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
883 return SDValue(DAG.UpdateNodeOperands(N,
884 SExtPromotedInteger(N->getOperand(0))), 0);
887 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
888 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
889 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
890 int SVOffset = N->getSrcValueOffset();
891 unsigned Alignment = N->getAlignment();
892 bool isVolatile = N->isVolatile();
893 bool isNonTemporal = N->isNonTemporal();
894 DebugLoc dl = N->getDebugLoc();
896 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
898 // Truncate the value and store the result.
899 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
900 SVOffset, N->getMemoryVT(),
901 isVolatile, isNonTemporal, Alignment);
904 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
905 SDValue Op = GetPromotedInteger(N->getOperand(0));
906 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
909 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
910 return SDValue(DAG.UpdateNodeOperands(N,
911 ZExtPromotedInteger(N->getOperand(0))), 0);
914 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
915 DebugLoc dl = N->getDebugLoc();
916 SDValue Op = GetPromotedInteger(N->getOperand(0));
917 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
918 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
922 //===----------------------------------------------------------------------===//
923 // Integer Result Expansion
924 //===----------------------------------------------------------------------===//
926 /// ExpandIntegerResult - This method is called when the specified result of the
927 /// specified node is found to need expansion. At this point, the node may also
928 /// have invalid operands or may have other results that need promotion, we just
929 /// know that (at least) one result needs expansion.
930 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
931 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
935 // See if the target wants to custom expand this node.
936 if (CustomLowerNode(N, N->getValueType(ResNo), true))
939 switch (N->getOpcode()) {
942 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
943 N->dump(&DAG); dbgs() << "\n";
945 llvm_unreachable("Do not know how to expand the result of this operator!");
947 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
948 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
949 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
950 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
952 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
953 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
954 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
955 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
956 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
958 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
959 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
960 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
961 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
962 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
963 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
964 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
965 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
966 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
967 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
968 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
969 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
970 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
971 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
972 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
973 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
974 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
975 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
976 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
977 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
981 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
984 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
987 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
990 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
994 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
997 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
999 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1002 // If Lo/Hi is null, the sub-method took care of registering results etc.
1004 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1007 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1008 /// and the shift amount is a constant 'Amt'. Expand the operation.
1009 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1010 SDValue &Lo, SDValue &Hi) {
1011 DebugLoc dl = N->getDebugLoc();
1012 // Expand the incoming operand to be shifted, so that we have its parts
1014 GetExpandedInteger(N->getOperand(0), InL, InH);
1016 EVT NVT = InL.getValueType();
1017 unsigned VTBits = N->getValueType(0).getSizeInBits();
1018 unsigned NVTBits = NVT.getSizeInBits();
1019 EVT ShTy = N->getOperand(1).getValueType();
1021 if (N->getOpcode() == ISD::SHL) {
1023 Lo = Hi = DAG.getConstant(0, NVT);
1024 } else if (Amt > NVTBits) {
1025 Lo = DAG.getConstant(0, NVT);
1026 Hi = DAG.getNode(ISD::SHL, dl,
1027 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1028 } else if (Amt == NVTBits) {
1029 Lo = DAG.getConstant(0, NVT);
1031 } else if (Amt == 1 &&
1032 TLI.isOperationLegalOrCustom(ISD::ADDC,
1033 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1034 // Emit this X << 1 as X+X.
1035 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1036 SDValue LoOps[2] = { InL, InL };
1037 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1038 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1039 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1041 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1042 Hi = DAG.getNode(ISD::OR, dl, NVT,
1043 DAG.getNode(ISD::SHL, dl, NVT, InH,
1044 DAG.getConstant(Amt, ShTy)),
1045 DAG.getNode(ISD::SRL, dl, NVT, InL,
1046 DAG.getConstant(NVTBits-Amt, ShTy)));
1051 if (N->getOpcode() == ISD::SRL) {
1053 Lo = DAG.getConstant(0, NVT);
1054 Hi = DAG.getConstant(0, NVT);
1055 } else if (Amt > NVTBits) {
1056 Lo = DAG.getNode(ISD::SRL, dl,
1057 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1058 Hi = DAG.getConstant(0, NVT);
1059 } else if (Amt == NVTBits) {
1061 Hi = DAG.getConstant(0, NVT);
1063 Lo = DAG.getNode(ISD::OR, dl, NVT,
1064 DAG.getNode(ISD::SRL, dl, NVT, InL,
1065 DAG.getConstant(Amt, ShTy)),
1066 DAG.getNode(ISD::SHL, dl, NVT, InH,
1067 DAG.getConstant(NVTBits-Amt, ShTy)));
1068 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1073 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1075 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1076 DAG.getConstant(NVTBits-1, ShTy));
1077 } else if (Amt > NVTBits) {
1078 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1079 DAG.getConstant(Amt-NVTBits, ShTy));
1080 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1081 DAG.getConstant(NVTBits-1, ShTy));
1082 } else if (Amt == NVTBits) {
1084 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1085 DAG.getConstant(NVTBits-1, ShTy));
1087 Lo = DAG.getNode(ISD::OR, dl, NVT,
1088 DAG.getNode(ISD::SRL, dl, NVT, InL,
1089 DAG.getConstant(Amt, ShTy)),
1090 DAG.getNode(ISD::SHL, dl, NVT, InH,
1091 DAG.getConstant(NVTBits-Amt, ShTy)));
1092 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1096 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1097 /// this shift based on knowledge of the high bit of the shift amount. If we
1098 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1100 bool DAGTypeLegalizer::
1101 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1102 SDValue Amt = N->getOperand(1);
1103 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1104 EVT ShTy = Amt.getValueType();
1105 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1106 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1107 assert(isPowerOf2_32(NVTBits) &&
1108 "Expanded integer type size not a power of two!");
1109 DebugLoc dl = N->getDebugLoc();
1111 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1112 APInt KnownZero, KnownOne;
1113 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1115 // If we don't know anything about the high bits, exit.
1116 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1119 // Get the incoming operand to be shifted.
1121 GetExpandedInteger(N->getOperand(0), InL, InH);
1123 // If we know that any of the high bits of the shift amount are one, then we
1124 // can do this as a couple of simple shifts.
1125 if (KnownOne.intersects(HighBitMask)) {
1126 // Mask out the high bit, which we know is set.
1127 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1128 DAG.getConstant(~HighBitMask, ShTy));
1130 switch (N->getOpcode()) {
1131 default: llvm_unreachable("Unknown shift");
1133 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1134 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1137 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1138 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1141 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1142 DAG.getConstant(NVTBits-1, ShTy));
1143 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1149 // FIXME: This code is broken for shifts with a zero amount!
1150 // If we know that all of the high bits of the shift amount are zero, then we
1151 // can do this as a couple of simple shifts.
1152 if ((KnownZero & HighBitMask) == HighBitMask) {
1154 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1155 DAG.getConstant(NVTBits, ShTy),
1158 switch (N->getOpcode()) {
1159 default: llvm_unreachable("Unknown shift");
1160 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1162 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1165 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1166 Hi = DAG.getNode(ISD::OR, NVT,
1167 DAG.getNode(Op1, NVT, InH, Amt),
1168 DAG.getNode(Op2, NVT, InL, Amt2));
1176 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1178 bool DAGTypeLegalizer::
1179 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1180 SDValue Amt = N->getOperand(1);
1181 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1182 EVT ShTy = Amt.getValueType();
1183 unsigned NVTBits = NVT.getSizeInBits();
1184 assert(isPowerOf2_32(NVTBits) &&
1185 "Expanded integer type size not a power of two!");
1186 DebugLoc dl = N->getDebugLoc();
1188 // Get the incoming operand to be shifted.
1190 GetExpandedInteger(N->getOperand(0), InL, InH);
1192 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1193 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1194 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1195 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1196 Amt, NVBitsNode, ISD::SETULT);
1198 SDValue LoS, HiS, LoL, HiL;
1199 switch (N->getOpcode()) {
1200 default: llvm_unreachable("Unknown shift");
1202 // Short: ShAmt < NVTBits
1203 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1204 HiS = DAG.getNode(ISD::OR, dl, NVT,
1205 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1206 // FIXME: If Amt is zero, the following shift generates an undefined result
1207 // on some architectures.
1208 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1210 // Long: ShAmt >= NVTBits
1211 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1212 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1214 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1215 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1218 // Short: ShAmt < NVTBits
1219 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1220 LoS = DAG.getNode(ISD::OR, dl, NVT,
1221 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1222 // FIXME: If Amt is zero, the following shift generates an undefined result
1223 // on some architectures.
1224 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1226 // Long: ShAmt >= NVTBits
1227 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1228 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1230 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1231 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1234 // Short: ShAmt < NVTBits
1235 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1236 LoS = DAG.getNode(ISD::OR, dl, NVT,
1237 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1238 // FIXME: If Amt is zero, the following shift generates an undefined result
1239 // on some architectures.
1240 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1242 // Long: ShAmt >= NVTBits
1243 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1244 DAG.getConstant(NVTBits-1, ShTy));
1245 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1247 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1248 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1255 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1256 SDValue &Lo, SDValue &Hi) {
1257 DebugLoc dl = N->getDebugLoc();
1258 // Expand the subcomponents.
1259 SDValue LHSL, LHSH, RHSL, RHSH;
1260 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1261 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1263 EVT NVT = LHSL.getValueType();
1264 SDValue LoOps[2] = { LHSL, RHSL };
1265 SDValue HiOps[3] = { LHSH, RHSH };
1267 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1268 // them. TODO: Teach operation legalization how to expand unsupported
1269 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1270 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1271 // generate a value of this type in the expanded code sequence.
1273 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1274 ISD::ADDC : ISD::SUBC,
1275 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1278 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1279 if (N->getOpcode() == ISD::ADD) {
1280 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1281 HiOps[2] = Lo.getValue(1);
1282 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1284 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1285 HiOps[2] = Lo.getValue(1);
1286 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1289 if (N->getOpcode() == ISD::ADD) {
1290 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1291 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1292 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1294 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1295 DAG.getConstant(1, NVT),
1296 DAG.getConstant(0, NVT));
1297 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1299 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1300 DAG.getConstant(1, NVT), Carry1);
1301 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1303 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1304 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1306 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1307 LoOps[0], LoOps[1], ISD::SETULT);
1308 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1309 DAG.getConstant(1, NVT),
1310 DAG.getConstant(0, NVT));
1311 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1316 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1317 SDValue &Lo, SDValue &Hi) {
1318 // Expand the subcomponents.
1319 SDValue LHSL, LHSH, RHSL, RHSH;
1320 DebugLoc dl = N->getDebugLoc();
1321 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1322 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1323 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1324 SDValue LoOps[2] = { LHSL, RHSL };
1325 SDValue HiOps[3] = { LHSH, RHSH };
1327 if (N->getOpcode() == ISD::ADDC) {
1328 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1329 HiOps[2] = Lo.getValue(1);
1330 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1332 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1333 HiOps[2] = Lo.getValue(1);
1334 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1337 // Legalized the flag result - switch anything that used the old flag to
1339 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1342 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1343 SDValue &Lo, SDValue &Hi) {
1344 // Expand the subcomponents.
1345 SDValue LHSL, LHSH, RHSL, RHSH;
1346 DebugLoc dl = N->getDebugLoc();
1347 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1348 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1349 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1350 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1351 SDValue HiOps[3] = { LHSH, RHSH };
1353 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1354 HiOps[2] = Lo.getValue(1);
1355 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1357 // Legalized the flag result - switch anything that used the old flag to
1359 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1362 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1363 SDValue &Lo, SDValue &Hi) {
1364 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1365 DebugLoc dl = N->getDebugLoc();
1366 SDValue Op = N->getOperand(0);
1367 if (Op.getValueType().bitsLE(NVT)) {
1368 // The low part is any extension of the input (which degenerates to a copy).
1369 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1370 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1372 // For example, extension of an i48 to an i64. The operand type necessarily
1373 // promotes to the result type, so will end up being expanded too.
1374 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1375 "Only know how to promote this result!");
1376 SDValue Res = GetPromotedInteger(Op);
1377 assert(Res.getValueType() == N->getValueType(0) &&
1378 "Operand over promoted?");
1379 // Split the promoted operand. This will simplify when it is expanded.
1380 SplitInteger(Res, Lo, Hi);
1384 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1385 SDValue &Lo, SDValue &Hi) {
1386 DebugLoc dl = N->getDebugLoc();
1387 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1388 EVT NVT = Lo.getValueType();
1389 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1390 unsigned NVTBits = NVT.getSizeInBits();
1391 unsigned EVTBits = EVT.getSizeInBits();
1393 if (NVTBits < EVTBits) {
1394 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1395 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1396 EVTBits - NVTBits)));
1398 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1399 // The high part replicates the sign bit of Lo, make it explicit.
1400 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1401 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1405 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1406 SDValue &Lo, SDValue &Hi) {
1407 DebugLoc dl = N->getDebugLoc();
1408 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1409 EVT NVT = Lo.getValueType();
1410 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1411 unsigned NVTBits = NVT.getSizeInBits();
1412 unsigned EVTBits = EVT.getSizeInBits();
1414 if (NVTBits < EVTBits) {
1415 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1416 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1417 EVTBits - NVTBits)));
1419 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1420 // The high part must be zero, make it explicit.
1421 Hi = DAG.getConstant(0, NVT);
1425 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1426 SDValue &Lo, SDValue &Hi) {
1427 DebugLoc dl = N->getDebugLoc();
1428 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1429 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1430 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1433 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1434 SDValue &Lo, SDValue &Hi) {
1435 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1436 unsigned NBitWidth = NVT.getSizeInBits();
1437 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1438 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1439 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1442 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1443 SDValue &Lo, SDValue &Hi) {
1444 DebugLoc dl = N->getDebugLoc();
1445 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1446 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1447 EVT NVT = Lo.getValueType();
1449 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1450 DAG.getConstant(0, NVT), ISD::SETNE);
1452 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1453 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1455 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1456 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1457 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1458 Hi = DAG.getConstant(0, NVT);
1461 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1462 SDValue &Lo, SDValue &Hi) {
1463 DebugLoc dl = N->getDebugLoc();
1464 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1465 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1466 EVT NVT = Lo.getValueType();
1467 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1468 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1469 Hi = DAG.getConstant(0, NVT);
1472 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1473 SDValue &Lo, SDValue &Hi) {
1474 DebugLoc dl = N->getDebugLoc();
1475 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1476 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1477 EVT NVT = Lo.getValueType();
1479 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1480 DAG.getConstant(0, NVT), ISD::SETNE);
1482 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1483 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1485 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1486 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1487 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1488 Hi = DAG.getConstant(0, NVT);
1491 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1493 DebugLoc dl = N->getDebugLoc();
1494 EVT VT = N->getValueType(0);
1495 SDValue Op = N->getOperand(0);
1496 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1497 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1498 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1501 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1503 DebugLoc dl = N->getDebugLoc();
1504 EVT VT = N->getValueType(0);
1505 SDValue Op = N->getOperand(0);
1506 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1507 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1508 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1511 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1512 SDValue &Lo, SDValue &Hi) {
1513 if (ISD::isNormalLoad(N)) {
1514 ExpandRes_NormalLoad(N, Lo, Hi);
1518 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1520 EVT VT = N->getValueType(0);
1521 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1522 SDValue Ch = N->getChain();
1523 SDValue Ptr = N->getBasePtr();
1524 ISD::LoadExtType ExtType = N->getExtensionType();
1525 int SVOffset = N->getSrcValueOffset();
1526 unsigned Alignment = N->getAlignment();
1527 bool isVolatile = N->isVolatile();
1528 bool isNonTemporal = N->isNonTemporal();
1529 DebugLoc dl = N->getDebugLoc();
1531 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1533 if (N->getMemoryVT().bitsLE(NVT)) {
1534 EVT MemVT = N->getMemoryVT();
1536 Lo = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1537 MemVT, isVolatile, isNonTemporal, Alignment);
1539 // Remember the chain.
1540 Ch = Lo.getValue(1);
1542 if (ExtType == ISD::SEXTLOAD) {
1543 // The high part is obtained by SRA'ing all but one of the bits of the
1545 unsigned LoSize = Lo.getValueType().getSizeInBits();
1546 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1547 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1548 } else if (ExtType == ISD::ZEXTLOAD) {
1549 // The high part is just a zero.
1550 Hi = DAG.getConstant(0, NVT);
1552 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1553 // The high part is undefined.
1554 Hi = DAG.getUNDEF(NVT);
1556 } else if (TLI.isLittleEndian()) {
1557 // Little-endian - low bits are at low addresses.
1558 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1559 isVolatile, isNonTemporal, Alignment);
1561 unsigned ExcessBits =
1562 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1563 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1565 // Increment the pointer to the other half.
1566 unsigned IncrementSize = NVT.getSizeInBits()/8;
1567 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1568 DAG.getIntPtrConstant(IncrementSize));
1569 Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getSrcValue(),
1570 SVOffset+IncrementSize, NEVT,
1571 isVolatile, isNonTemporal,
1572 MinAlign(Alignment, IncrementSize));
1574 // Build a factor node to remember that this load is independent of the
1576 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1579 // Big-endian - high bits are at low addresses. Favor aligned loads at
1580 // the cost of some bit-fiddling.
1581 EVT MemVT = N->getMemoryVT();
1582 unsigned EBytes = MemVT.getStoreSize();
1583 unsigned IncrementSize = NVT.getSizeInBits()/8;
1584 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1586 // Load both the high bits and maybe some of the low bits.
1587 Hi = DAG.getExtLoad(ExtType, NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1588 EVT::getIntegerVT(*DAG.getContext(),
1589 MemVT.getSizeInBits() - ExcessBits),
1590 isVolatile, isNonTemporal, Alignment);
1592 // Increment the pointer to the other half.
1593 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1594 DAG.getIntPtrConstant(IncrementSize));
1595 // Load the rest of the low bits.
1596 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, dl, Ch, Ptr, N->getSrcValue(),
1597 SVOffset+IncrementSize,
1598 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1599 isVolatile, isNonTemporal,
1600 MinAlign(Alignment, IncrementSize));
1602 // Build a factor node to remember that this load is independent of the
1604 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1607 if (ExcessBits < NVT.getSizeInBits()) {
1608 // Transfer low bits from the bottom of Hi to the top of Lo.
1609 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1610 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1611 DAG.getConstant(ExcessBits,
1612 TLI.getPointerTy())));
1613 // Move high bits to the right position in Hi.
1614 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1616 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1617 TLI.getPointerTy()));
1621 // Legalized the chain result - switch anything that used the old chain to
1623 ReplaceValueWith(SDValue(N, 1), Ch);
1626 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1627 SDValue &Lo, SDValue &Hi) {
1628 DebugLoc dl = N->getDebugLoc();
1629 SDValue LL, LH, RL, RH;
1630 GetExpandedInteger(N->getOperand(0), LL, LH);
1631 GetExpandedInteger(N->getOperand(1), RL, RH);
1632 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1633 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1636 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1637 SDValue &Lo, SDValue &Hi) {
1638 EVT VT = N->getValueType(0);
1639 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1640 DebugLoc dl = N->getDebugLoc();
1642 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1643 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1644 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1645 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1646 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1647 SDValue LL, LH, RL, RH;
1648 GetExpandedInteger(N->getOperand(0), LL, LH);
1649 GetExpandedInteger(N->getOperand(1), RL, RH);
1650 unsigned OuterBitSize = VT.getSizeInBits();
1651 unsigned InnerBitSize = NVT.getSizeInBits();
1652 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1653 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1655 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1656 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1657 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1658 // The inputs are both zero-extended.
1660 // We can emit a umul_lohi.
1661 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1662 Hi = SDValue(Lo.getNode(), 1);
1666 // We can emit a mulhu+mul.
1667 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1668 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1672 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1673 // The input values are both sign-extended.
1675 // We can emit a smul_lohi.
1676 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1677 Hi = SDValue(Lo.getNode(), 1);
1681 // We can emit a mulhs+mul.
1682 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1683 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1688 // Lo,Hi = umul LHS, RHS.
1689 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1690 DAG.getVTList(NVT, NVT), LL, RL);
1692 Hi = UMulLOHI.getValue(1);
1693 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1694 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1695 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1696 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1700 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1701 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1702 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1703 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1704 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1705 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1710 // If nothing else, we can make a libcall.
1711 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1713 LC = RTLIB::MUL_I16;
1714 else if (VT == MVT::i32)
1715 LC = RTLIB::MUL_I32;
1716 else if (VT == MVT::i64)
1717 LC = RTLIB::MUL_I64;
1718 else if (VT == MVT::i128)
1719 LC = RTLIB::MUL_I128;
1720 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1722 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1723 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1726 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
1727 SDValue &Lo, SDValue &Hi) {
1728 SDValue LHS = Node->getOperand(0);
1729 SDValue RHS = Node->getOperand(1);
1730 DebugLoc dl = Node->getDebugLoc();
1732 // Expand the result by simply replacing it with the equivalent
1733 // non-overflow-checking operation.
1734 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
1735 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1737 SplitInteger(Sum, Lo, Hi);
1739 // Compute the overflow.
1741 // LHSSign -> LHS >= 0
1742 // RHSSign -> RHS >= 0
1743 // SumSign -> Sum >= 0
1746 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
1748 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
1750 EVT OType = Node->getValueType(1);
1751 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
1753 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
1754 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
1755 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
1756 Node->getOpcode() == ISD::SADDO ?
1757 ISD::SETEQ : ISD::SETNE);
1759 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
1760 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
1762 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
1764 // Use the calculated overflow everywhere.
1765 ReplaceValueWith(SDValue(Node, 1), Cmp);
1768 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1769 SDValue &Lo, SDValue &Hi) {
1770 EVT VT = N->getValueType(0);
1771 DebugLoc dl = N->getDebugLoc();
1773 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1775 LC = RTLIB::SDIV_I16;
1776 else if (VT == MVT::i32)
1777 LC = RTLIB::SDIV_I32;
1778 else if (VT == MVT::i64)
1779 LC = RTLIB::SDIV_I64;
1780 else if (VT == MVT::i128)
1781 LC = RTLIB::SDIV_I128;
1782 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1784 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1785 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1788 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1789 SDValue &Lo, SDValue &Hi) {
1790 EVT VT = N->getValueType(0);
1791 DebugLoc dl = N->getDebugLoc();
1793 // If we can emit an efficient shift operation, do so now. Check to see if
1794 // the RHS is a constant.
1795 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1796 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1798 // If we can determine that the high bit of the shift is zero or one, even if
1799 // the low bits are variable, emit this shift in an optimized form.
1800 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1803 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1805 if (N->getOpcode() == ISD::SHL) {
1806 PartsOpc = ISD::SHL_PARTS;
1807 } else if (N->getOpcode() == ISD::SRL) {
1808 PartsOpc = ISD::SRL_PARTS;
1810 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1811 PartsOpc = ISD::SRA_PARTS;
1814 // Next check to see if the target supports this SHL_PARTS operation or if it
1815 // will custom expand it.
1816 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1817 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1818 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1819 Action == TargetLowering::Custom) {
1820 // Expand the subcomponents.
1822 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1824 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1825 EVT VT = LHSL.getValueType();
1826 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1827 Hi = Lo.getValue(1);
1831 // Otherwise, emit a libcall.
1832 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1834 if (N->getOpcode() == ISD::SHL) {
1835 isSigned = false; /*sign irrelevant*/
1837 LC = RTLIB::SHL_I16;
1838 else if (VT == MVT::i32)
1839 LC = RTLIB::SHL_I32;
1840 else if (VT == MVT::i64)
1841 LC = RTLIB::SHL_I64;
1842 else if (VT == MVT::i128)
1843 LC = RTLIB::SHL_I128;
1844 } else if (N->getOpcode() == ISD::SRL) {
1847 LC = RTLIB::SRL_I16;
1848 else if (VT == MVT::i32)
1849 LC = RTLIB::SRL_I32;
1850 else if (VT == MVT::i64)
1851 LC = RTLIB::SRL_I64;
1852 else if (VT == MVT::i128)
1853 LC = RTLIB::SRL_I128;
1855 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1858 LC = RTLIB::SRA_I16;
1859 else if (VT == MVT::i32)
1860 LC = RTLIB::SRA_I32;
1861 else if (VT == MVT::i64)
1862 LC = RTLIB::SRA_I64;
1863 else if (VT == MVT::i128)
1864 LC = RTLIB::SRA_I128;
1867 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
1868 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1869 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1873 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
1874 llvm_unreachable("Unsupported shift!");
1877 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1878 SDValue &Lo, SDValue &Hi) {
1879 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1880 DebugLoc dl = N->getDebugLoc();
1881 SDValue Op = N->getOperand(0);
1882 if (Op.getValueType().bitsLE(NVT)) {
1883 // The low part is sign extension of the input (degenerates to a copy).
1884 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1885 // The high part is obtained by SRA'ing all but one of the bits of low part.
1886 unsigned LoSize = NVT.getSizeInBits();
1887 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1888 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1890 // For example, extension of an i48 to an i64. The operand type necessarily
1891 // promotes to the result type, so will end up being expanded too.
1892 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1893 "Only know how to promote this result!");
1894 SDValue Res = GetPromotedInteger(Op);
1895 assert(Res.getValueType() == N->getValueType(0) &&
1896 "Operand over promoted?");
1897 // Split the promoted operand. This will simplify when it is expanded.
1898 SplitInteger(Res, Lo, Hi);
1899 unsigned ExcessBits =
1900 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1901 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1902 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1907 void DAGTypeLegalizer::
1908 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1909 DebugLoc dl = N->getDebugLoc();
1910 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1911 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1913 if (EVT.bitsLE(Lo.getValueType())) {
1914 // sext_inreg the low part if needed.
1915 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1918 // The high part gets the sign extension from the lo-part. This handles
1919 // things like sextinreg V:i64 from i8.
1920 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1921 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1922 TLI.getPointerTy()));
1924 // For example, extension of an i48 to an i64. Leave the low part alone,
1925 // sext_inreg the high part.
1926 unsigned ExcessBits =
1927 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1928 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1929 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits)));
1933 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1934 SDValue &Lo, SDValue &Hi) {
1935 EVT VT = N->getValueType(0);
1936 DebugLoc dl = N->getDebugLoc();
1938 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1940 LC = RTLIB::SREM_I16;
1941 else if (VT == MVT::i32)
1942 LC = RTLIB::SREM_I32;
1943 else if (VT == MVT::i64)
1944 LC = RTLIB::SREM_I64;
1945 else if (VT == MVT::i128)
1946 LC = RTLIB::SREM_I128;
1947 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1949 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1950 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1953 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1954 SDValue &Lo, SDValue &Hi) {
1955 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1956 DebugLoc dl = N->getDebugLoc();
1957 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1958 Hi = DAG.getNode(ISD::SRL, dl,
1959 N->getOperand(0).getValueType(), N->getOperand(0),
1960 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1961 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1964 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
1965 SDValue &Lo, SDValue &Hi) {
1966 SDValue LHS = N->getOperand(0);
1967 SDValue RHS = N->getOperand(1);
1968 DebugLoc dl = N->getDebugLoc();
1970 // Expand the result by simply replacing it with the equivalent
1971 // non-overflow-checking operation.
1972 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
1973 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1975 SplitInteger(Sum, Lo, Hi);
1977 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
1978 // overflows iff a - b > a.
1979 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
1980 N->getOpcode () == ISD::UADDO ?
1981 ISD::SETULT : ISD::SETUGT);
1983 // Use the calculated overflow everywhere.
1984 ReplaceValueWith(SDValue(N, 1), Ofl);
1987 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1988 SDValue &Lo, SDValue &Hi) {
1989 EVT VT = N->getValueType(0);
1990 DebugLoc dl = N->getDebugLoc();
1992 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1994 LC = RTLIB::UDIV_I16;
1995 else if (VT == MVT::i32)
1996 LC = RTLIB::UDIV_I32;
1997 else if (VT == MVT::i64)
1998 LC = RTLIB::UDIV_I64;
1999 else if (VT == MVT::i128)
2000 LC = RTLIB::UDIV_I128;
2001 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2003 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2004 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2007 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2008 SDValue &Lo, SDValue &Hi) {
2009 EVT VT = N->getValueType(0);
2010 DebugLoc dl = N->getDebugLoc();
2012 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2014 LC = RTLIB::UREM_I16;
2015 else if (VT == MVT::i32)
2016 LC = RTLIB::UREM_I32;
2017 else if (VT == MVT::i64)
2018 LC = RTLIB::UREM_I64;
2019 else if (VT == MVT::i128)
2020 LC = RTLIB::UREM_I128;
2021 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2023 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2024 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2027 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2028 SDValue &Lo, SDValue &Hi) {
2029 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2030 DebugLoc dl = N->getDebugLoc();
2031 SDValue Op = N->getOperand(0);
2032 if (Op.getValueType().bitsLE(NVT)) {
2033 // The low part is zero extension of the input (degenerates to a copy).
2034 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2035 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2037 // For example, extension of an i48 to an i64. The operand type necessarily
2038 // promotes to the result type, so will end up being expanded too.
2039 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
2040 "Only know how to promote this result!");
2041 SDValue Res = GetPromotedInteger(Op);
2042 assert(Res.getValueType() == N->getValueType(0) &&
2043 "Operand over promoted?");
2044 // Split the promoted operand. This will simplify when it is expanded.
2045 SplitInteger(Res, Lo, Hi);
2046 unsigned ExcessBits =
2047 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2048 Hi = DAG.getZeroExtendInReg(Hi, dl,
2049 EVT::getIntegerVT(*DAG.getContext(), ExcessBits));
2054 //===----------------------------------------------------------------------===//
2055 // Integer Operand Expansion
2056 //===----------------------------------------------------------------------===//
2058 /// ExpandIntegerOperand - This method is called when the specified operand of
2059 /// the specified node is found to need expansion. At this point, all of the
2060 /// result types of the node are known to be legal, but other operands of the
2061 /// node may need promotion or expansion as well as the specified one.
2062 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2063 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2064 SDValue Res = SDValue();
2066 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2069 switch (N->getOpcode()) {
2072 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2073 N->dump(&DAG); dbgs() << "\n";
2075 llvm_unreachable("Do not know how to expand this operator's operand!");
2077 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
2078 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2079 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2080 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2081 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2082 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2083 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2084 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2085 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2086 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2087 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2088 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2094 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2095 case ISD::RETURNADDR:
2096 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2099 // If the result is null, the sub-method took care of registering results etc.
2100 if (!Res.getNode()) return false;
2102 // If the result is N, the sub-method updated N in place. Tell the legalizer
2104 if (Res.getNode() == N)
2107 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2108 "Invalid operand expansion");
2110 ReplaceValueWith(SDValue(N, 0), Res);
2114 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2115 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2116 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2118 ISD::CondCode &CCCode,
2120 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2121 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2122 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2124 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2125 if (RHSLo == RHSHi) {
2126 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2127 if (RHSCST->isAllOnesValue()) {
2128 // Equality comparison to -1.
2129 NewLHS = DAG.getNode(ISD::AND, dl,
2130 LHSLo.getValueType(), LHSLo, LHSHi);
2137 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2138 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2139 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2140 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2144 // If this is a comparison of the sign bit, just look at the top part.
2146 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2147 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2148 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2154 // FIXME: This generated code sucks.
2155 ISD::CondCode LowCC;
2157 default: llvm_unreachable("Unknown integer setcc!");
2159 case ISD::SETULT: LowCC = ISD::SETULT; break;
2161 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2163 case ISD::SETULE: LowCC = ISD::SETULE; break;
2165 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2168 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2169 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2170 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2172 // NOTE: on targets without efficient SELECT of bools, we can always use
2173 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2174 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2176 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2177 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2178 if (!Tmp1.getNode())
2179 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2180 LHSLo, RHSLo, LowCC);
2181 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2182 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2183 if (!Tmp2.getNode())
2184 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2185 TLI.getSetCCResultType(LHSHi.getValueType()),
2186 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2188 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2189 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2190 if ((Tmp1C && Tmp1C->isNullValue()) ||
2191 (Tmp2C && Tmp2C->isNullValue() &&
2192 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2193 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2194 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2195 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2196 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2197 // low part is known false, returns high part.
2198 // For LE / GE, if high part is known false, ignore the low part.
2199 // For LT / GT, if high part is known true, ignore the low part.
2205 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2206 LHSHi, RHSHi, ISD::SETEQ, false,
2207 DagCombineInfo, dl);
2208 if (!NewLHS.getNode())
2209 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2210 LHSHi, RHSHi, ISD::SETEQ);
2211 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2212 NewLHS, Tmp1, Tmp2);
2216 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2217 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2218 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2219 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2221 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2222 // against zero to select between true and false values.
2223 if (NewRHS.getNode() == 0) {
2224 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2225 CCCode = ISD::SETNE;
2228 // Update N to have the operands specified.
2229 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2230 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2231 N->getOperand(4)), 0);
2234 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2235 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2236 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2237 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2239 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2240 // against zero to select between true and false values.
2241 if (NewRHS.getNode() == 0) {
2242 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2243 CCCode = ISD::SETNE;
2246 // Update N to have the operands specified.
2247 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2248 N->getOperand(2), N->getOperand(3),
2249 DAG.getCondCode(CCCode)), 0);
2252 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2253 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2254 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2255 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2257 // If ExpandSetCCOperands returned a scalar, use it.
2258 if (NewRHS.getNode() == 0) {
2259 assert(NewLHS.getValueType() == N->getValueType(0) &&
2260 "Unexpected setcc expansion!");
2264 // Otherwise, update N to have the operands specified.
2265 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2266 DAG.getCondCode(CCCode)), 0);
2269 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2270 // The value being shifted is legal, but the shift amount is too big.
2271 // It follows that either the result of the shift is undefined, or the
2272 // upper half of the shift amount is zero. Just use the lower half.
2274 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2275 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2278 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2279 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2280 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2281 // constant to valid type.
2283 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2284 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2287 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2288 SDValue Op = N->getOperand(0);
2289 EVT DstVT = N->getValueType(0);
2290 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2291 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2292 "Don't know how to expand this SINT_TO_FP!");
2293 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2296 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2297 if (ISD::isNormalStore(N))
2298 return ExpandOp_NormalStore(N, OpNo);
2300 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2301 assert(OpNo == 1 && "Can only expand the stored value so far");
2303 EVT VT = N->getOperand(1).getValueType();
2304 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2305 SDValue Ch = N->getChain();
2306 SDValue Ptr = N->getBasePtr();
2307 int SVOffset = N->getSrcValueOffset();
2308 unsigned Alignment = N->getAlignment();
2309 bool isVolatile = N->isVolatile();
2310 bool isNonTemporal = N->isNonTemporal();
2311 DebugLoc dl = N->getDebugLoc();
2314 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2316 if (N->getMemoryVT().bitsLE(NVT)) {
2317 GetExpandedInteger(N->getValue(), Lo, Hi);
2318 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2319 N->getMemoryVT(), isVolatile, isNonTemporal,
2321 } else if (TLI.isLittleEndian()) {
2322 // Little-endian - low bits are at low addresses.
2323 GetExpandedInteger(N->getValue(), Lo, Hi);
2325 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2326 isVolatile, isNonTemporal, Alignment);
2328 unsigned ExcessBits =
2329 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2330 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2332 // Increment the pointer to the other half.
2333 unsigned IncrementSize = NVT.getSizeInBits()/8;
2334 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2335 DAG.getIntPtrConstant(IncrementSize));
2336 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2337 SVOffset+IncrementSize, NEVT,
2338 isVolatile, isNonTemporal,
2339 MinAlign(Alignment, IncrementSize));
2340 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2342 // Big-endian - high bits are at low addresses. Favor aligned stores at
2343 // the cost of some bit-fiddling.
2344 GetExpandedInteger(N->getValue(), Lo, Hi);
2346 EVT ExtVT = N->getMemoryVT();
2347 unsigned EBytes = ExtVT.getStoreSize();
2348 unsigned IncrementSize = NVT.getSizeInBits()/8;
2349 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2350 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2351 ExtVT.getSizeInBits() - ExcessBits);
2353 if (ExcessBits < NVT.getSizeInBits()) {
2354 // Transfer high bits from the top of Lo to the bottom of Hi.
2355 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2356 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2357 TLI.getPointerTy()));
2358 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2359 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2360 DAG.getConstant(ExcessBits,
2361 TLI.getPointerTy())));
2364 // Store both the high bits and maybe some of the low bits.
2365 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2366 SVOffset, HiVT, isVolatile, isNonTemporal,
2369 // Increment the pointer to the other half.
2370 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2371 DAG.getIntPtrConstant(IncrementSize));
2372 // Store the lowest ExcessBits bits in the second half.
2373 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2374 SVOffset+IncrementSize,
2375 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2376 isVolatile, isNonTemporal,
2377 MinAlign(Alignment, IncrementSize));
2378 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2382 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2384 GetExpandedInteger(N->getOperand(0), InL, InH);
2385 // Just truncate the low part of the source.
2386 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2389 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
2390 switch (VT.getSimpleVT().SimpleTy) {
2391 default: llvm_unreachable("Unknown FP format");
2392 case MVT::f32: return &APFloat::IEEEsingle;
2393 case MVT::f64: return &APFloat::IEEEdouble;
2394 case MVT::f80: return &APFloat::x87DoubleExtended;
2395 case MVT::f128: return &APFloat::IEEEquad;
2396 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
2400 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2401 SDValue Op = N->getOperand(0);
2402 EVT SrcVT = Op.getValueType();
2403 EVT DstVT = N->getValueType(0);
2404 DebugLoc dl = N->getDebugLoc();
2406 // The following optimization is valid only if every value in SrcVT (when
2407 // treated as signed) is representable in DstVT. Check that the mantissa
2408 // size of DstVT is >= than the number of bits in SrcVT -1.
2409 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT);
2410 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 &&
2411 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2412 // Do a signed conversion then adjust the result.
2413 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2414 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2416 // The result of the signed conversion needs adjusting if the 'sign bit' of
2417 // the incoming integer was set. To handle this, we dynamically test to see
2418 // if it is set, and, if so, add a fudge factor.
2420 const uint64_t F32TwoE32 = 0x4F800000ULL;
2421 const uint64_t F32TwoE64 = 0x5F800000ULL;
2422 const uint64_t F32TwoE128 = 0x7F800000ULL;
2425 if (SrcVT == MVT::i32)
2426 FF = APInt(32, F32TwoE32);
2427 else if (SrcVT == MVT::i64)
2428 FF = APInt(32, F32TwoE64);
2429 else if (SrcVT == MVT::i128)
2430 FF = APInt(32, F32TwoE128);
2432 assert(false && "Unsupported UINT_TO_FP!");
2434 // Check whether the sign bit is set.
2436 GetExpandedInteger(Op, Lo, Hi);
2437 SDValue SignSet = DAG.getSetCC(dl,
2438 TLI.getSetCCResultType(Hi.getValueType()),
2439 Hi, DAG.getConstant(0, Hi.getValueType()),
2442 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2443 SDValue FudgePtr = DAG.getConstantPool(
2444 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2445 TLI.getPointerTy());
2447 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2448 SDValue Zero = DAG.getIntPtrConstant(0);
2449 SDValue Four = DAG.getIntPtrConstant(4);
2450 if (TLI.isBigEndian()) std::swap(Zero, Four);
2451 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2453 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2454 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2455 Alignment = std::min(Alignment, 4u);
2457 // Load the value out, extending it from f32 to the destination float type.
2458 // FIXME: Avoid the extend by constructing the right constant pool?
2459 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, dl, DAG.getEntryNode(),
2460 FudgePtr, NULL, 0, MVT::f32,
2461 false, false, Alignment);
2462 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2465 // Otherwise, use a libcall.
2466 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2467 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2468 "Don't know how to expand this UINT_TO_FP!");
2469 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);