1 //===-- LegalizeTypesExpand.cpp - Expansion for LegalizeTypes -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements expansion support for LegalizeTypes. Expansion is the
11 // act of changing a computation in an invalid type to be a computation in
12 // multiple registers of a smaller type. For example, implementing i64
13 // arithmetic in two i32 registers (as is often needed on 32-bit targets, for
16 //===----------------------------------------------------------------------===//
18 #include "LegalizeTypes.h"
19 #include "llvm/Constants.h"
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 /// ExpandResult - This method is called when the specified result of the
27 /// specified node is found to need expansion. At this point, the node may also
28 /// have invalid operands or may have other results that need promotion, we just
29 /// know that (at least) one result needs expansion.
30 void DAGTypeLegalizer::ExpandResult(SDNode *N, unsigned ResNo) {
31 DEBUG(cerr << "Expand node result: "; N->dump(&DAG); cerr << "\n");
33 Lo = Hi = SDOperand();
35 // See if the target wants to custom expand this node.
36 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
37 TargetLowering::Custom) {
38 // If the target wants to, allow it to lower this itself.
39 if (SDNode *P = TLI.ExpandOperationResult(N, DAG)) {
40 // Everything that once used N now uses P. We are guaranteed that the
41 // result value types of N and the result value types of P match.
42 ReplaceNodeWith(N, P);
47 switch (N->getOpcode()) {
50 cerr << "ExpandResult #" << ResNo << ": ";
51 N->dump(&DAG); cerr << "\n";
53 assert(0 && "Do not know how to expand the result of this operator!");
56 case ISD::UNDEF: ExpandResult_UNDEF(N, Lo, Hi); break;
57 case ISD::Constant: ExpandResult_Constant(N, Lo, Hi); break;
58 case ISD::BUILD_PAIR: ExpandResult_BUILD_PAIR(N, Lo, Hi); break;
59 case ISD::MERGE_VALUES: ExpandResult_MERGE_VALUES(N, Lo, Hi); break;
60 case ISD::ANY_EXTEND: ExpandResult_ANY_EXTEND(N, Lo, Hi); break;
61 case ISD::ZERO_EXTEND: ExpandResult_ZERO_EXTEND(N, Lo, Hi); break;
62 case ISD::SIGN_EXTEND: ExpandResult_SIGN_EXTEND(N, Lo, Hi); break;
63 case ISD::AssertZext: ExpandResult_AssertZext(N, Lo, Hi); break;
64 case ISD::TRUNCATE: ExpandResult_TRUNCATE(N, Lo, Hi); break;
65 case ISD::BIT_CONVERT: ExpandResult_BIT_CONVERT(N, Lo, Hi); break;
66 case ISD::SIGN_EXTEND_INREG: ExpandResult_SIGN_EXTEND_INREG(N, Lo, Hi); break;
67 case ISD::LOAD: ExpandResult_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
71 case ISD::XOR: ExpandResult_Logical(N, Lo, Hi); break;
72 case ISD::BSWAP: ExpandResult_BSWAP(N, Lo, Hi); break;
74 case ISD::SUB: ExpandResult_ADDSUB(N, Lo, Hi); break;
76 case ISD::SUBC: ExpandResult_ADDSUBC(N, Lo, Hi); break;
78 case ISD::SUBE: ExpandResult_ADDSUBE(N, Lo, Hi); break;
79 case ISD::SELECT: ExpandResult_SELECT(N, Lo, Hi); break;
80 case ISD::SELECT_CC: ExpandResult_SELECT_CC(N, Lo, Hi); break;
81 case ISD::MUL: ExpandResult_MUL(N, Lo, Hi); break;
84 case ISD::SRL: ExpandResult_Shift(N, Lo, Hi); break;
87 // If Lo/Hi is null, the sub-method took care of registering results etc.
89 SetExpandedOp(SDOperand(N, ResNo), Lo, Hi);
92 void DAGTypeLegalizer::ExpandResult_UNDEF(SDNode *N,
93 SDOperand &Lo, SDOperand &Hi) {
94 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
95 Lo = Hi = DAG.getNode(ISD::UNDEF, NVT);
98 void DAGTypeLegalizer::ExpandResult_Constant(SDNode *N,
99 SDOperand &Lo, SDOperand &Hi) {
100 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
101 uint64_t Cst = cast<ConstantSDNode>(N)->getValue();
102 Lo = DAG.getConstant(Cst, NVT);
103 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
106 void DAGTypeLegalizer::ExpandResult_BUILD_PAIR(SDNode *N,
107 SDOperand &Lo, SDOperand &Hi) {
108 // Return the operands.
109 Lo = N->getOperand(0);
110 Hi = N->getOperand(1);
113 void DAGTypeLegalizer::ExpandResult_MERGE_VALUES(SDNode *N,
114 SDOperand &Lo, SDOperand &Hi) {
115 // A MERGE_VALUES node can produce any number of values. We know that the
116 // first illegal one needs to be expanded into Lo/Hi.
119 // The string of legal results gets turns into the input operands, which have
121 for (i = 0; isTypeLegal(N->getValueType(i)); ++i)
122 ReplaceValueWith(SDOperand(N, i), SDOperand(N->getOperand(i)));
124 // The first illegal result must be the one that needs to be expanded.
125 GetExpandedOp(N->getOperand(i), Lo, Hi);
127 // Legalize the rest of the results into the input operands whether they are
129 unsigned e = N->getNumValues();
130 for (++i; i != e; ++i)
131 ReplaceValueWith(SDOperand(N, i), SDOperand(N->getOperand(i)));
134 void DAGTypeLegalizer::ExpandResult_ANY_EXTEND(SDNode *N,
135 SDOperand &Lo, SDOperand &Hi) {
136 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
137 SDOperand Op = N->getOperand(0);
138 if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) {
139 // The low part is any extension of the input (which degenerates to a copy).
140 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
141 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
143 // For example, extension of an i48 to an i64. The operand type necessarily
144 // promotes to the result type, so will end up being expanded too.
145 assert(getTypeAction(Op.getValueType()) == Promote &&
146 "Don't know how to expand this result!");
147 SDOperand Res = GetPromotedOp(Op);
148 assert(Res.getValueType() == N->getValueType(0) &&
149 "Operand over promoted?");
150 // Split the promoted operand. This will simplify when it is expanded.
151 SplitOp(Res, Lo, Hi);
155 void DAGTypeLegalizer::ExpandResult_ZERO_EXTEND(SDNode *N,
156 SDOperand &Lo, SDOperand &Hi) {
157 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
158 SDOperand Op = N->getOperand(0);
159 if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) {
160 // The low part is zero extension of the input (which degenerates to a copy).
161 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
162 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
164 // For example, extension of an i48 to an i64. The operand type necessarily
165 // promotes to the result type, so will end up being expanded too.
166 assert(getTypeAction(Op.getValueType()) == Promote &&
167 "Don't know how to expand this result!");
168 SDOperand Res = GetPromotedOp(Op);
169 assert(Res.getValueType() == N->getValueType(0) &&
170 "Operand over promoted?");
171 // Split the promoted operand. This will simplify when it is expanded.
172 SplitOp(Res, Lo, Hi);
173 unsigned ExcessBits =
174 MVT::getSizeInBits(Op.getValueType()) - MVT::getSizeInBits(NVT);
175 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerType(ExcessBits));
179 void DAGTypeLegalizer::ExpandResult_SIGN_EXTEND(SDNode *N,
180 SDOperand &Lo, SDOperand &Hi) {
181 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
182 SDOperand Op = N->getOperand(0);
183 if (MVT::getSizeInBits(Op.getValueType()) <= MVT::getSizeInBits(NVT)) {
184 // The low part is sign extension of the input (which degenerates to a copy).
185 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
186 // The high part is obtained by SRA'ing all but one of the bits of low part.
187 unsigned LoSize = MVT::getSizeInBits(NVT);
188 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
189 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
191 // For example, extension of an i48 to an i64. The operand type necessarily
192 // promotes to the result type, so will end up being expanded too.
193 assert(getTypeAction(Op.getValueType()) == Promote &&
194 "Don't know how to expand this result!");
195 SDOperand Res = GetPromotedOp(Op);
196 assert(Res.getValueType() == N->getValueType(0) &&
197 "Operand over promoted?");
198 // Split the promoted operand. This will simplify when it is expanded.
199 SplitOp(Res, Lo, Hi);
200 unsigned ExcessBits =
201 MVT::getSizeInBits(Op.getValueType()) - MVT::getSizeInBits(NVT);
202 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
203 DAG.getValueType(MVT::getIntegerType(ExcessBits)));
207 void DAGTypeLegalizer::ExpandResult_AssertZext(SDNode *N,
208 SDOperand &Lo, SDOperand &Hi) {
209 GetExpandedOp(N->getOperand(0), Lo, Hi);
210 MVT::ValueType NVT = Lo.getValueType();
211 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
212 unsigned NVTBits = MVT::getSizeInBits(NVT);
213 unsigned EVTBits = MVT::getSizeInBits(EVT);
215 if (NVTBits < EVTBits) {
216 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
217 DAG.getValueType(MVT::getIntegerType(EVTBits - NVTBits)));
219 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
220 // The high part must be zero, make it explicit.
221 Hi = DAG.getConstant(0, NVT);
225 void DAGTypeLegalizer::ExpandResult_TRUNCATE(SDNode *N,
226 SDOperand &Lo, SDOperand &Hi) {
227 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
228 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
229 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
230 DAG.getConstant(MVT::getSizeInBits(NVT),
231 TLI.getShiftAmountTy()));
232 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
235 void DAGTypeLegalizer::ExpandResult_BIT_CONVERT(SDNode *N,
236 SDOperand &Lo, SDOperand &Hi) {
237 // Lower the bit-convert to a store/load from the stack, then expand the load.
238 SDOperand Op = CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
239 ExpandResult_LOAD(cast<LoadSDNode>(Op.Val), Lo, Hi);
242 void DAGTypeLegalizer::
243 ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
244 GetExpandedOp(N->getOperand(0), Lo, Hi);
245 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
247 if (MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(Lo.getValueType())) {
248 // sext_inreg the low part if needed.
249 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
252 // The high part gets the sign extension from the lo-part. This handles
253 // things like sextinreg V:i64 from i8.
254 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
255 DAG.getConstant(MVT::getSizeInBits(Hi.getValueType())-1,
256 TLI.getShiftAmountTy()));
258 // For example, extension of an i48 to an i64. Leave the low part alone,
259 // sext_inreg the high part.
260 unsigned ExcessBits =
261 MVT::getSizeInBits(EVT) - MVT::getSizeInBits(Lo.getValueType());
262 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
263 DAG.getValueType(MVT::getIntegerType(ExcessBits)));
267 void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
268 SDOperand &Lo, SDOperand &Hi) {
269 MVT::ValueType VT = N->getValueType(0);
270 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
271 SDOperand Ch = N->getChain(); // Legalize the chain.
272 SDOperand Ptr = N->getBasePtr(); // Legalize the pointer.
273 ISD::LoadExtType ExtType = N->getExtensionType();
274 int SVOffset = N->getSrcValueOffset();
275 unsigned Alignment = N->getAlignment();
276 bool isVolatile = N->isVolatile();
278 assert(!(MVT::getSizeInBits(NVT) & 7) && "Expanded type not byte sized!");
280 if (ExtType == ISD::NON_EXTLOAD) {
281 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
282 isVolatile, Alignment);
283 // Increment the pointer to the other half.
284 unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
285 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
286 DAG.getIntPtrConstant(IncrementSize));
287 Hi = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
288 isVolatile, MinAlign(Alignment, IncrementSize));
290 // Build a factor node to remember that this load is independent of the
292 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
295 // Handle endianness of the load.
296 if (TLI.isBigEndian())
298 } else if (MVT::getSizeInBits(N->getMemoryVT()) <= MVT::getSizeInBits(NVT)) {
299 MVT::ValueType EVT = N->getMemoryVT();
301 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
302 isVolatile, Alignment);
304 // Remember the chain.
307 if (ExtType == ISD::SEXTLOAD) {
308 // The high part is obtained by SRA'ing all but one of the bits of the
310 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
311 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
312 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
313 } else if (ExtType == ISD::ZEXTLOAD) {
314 // The high part is just a zero.
315 Hi = DAG.getConstant(0, NVT);
317 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
318 // The high part is undefined.
319 Hi = DAG.getNode(ISD::UNDEF, NVT);
321 } else if (TLI.isLittleEndian()) {
322 // Little-endian - low bits are at low addresses.
323 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
324 isVolatile, Alignment);
326 unsigned ExcessBits =
327 MVT::getSizeInBits(N->getMemoryVT()) - MVT::getSizeInBits(NVT);
328 MVT::ValueType NEVT = MVT::getIntegerType(ExcessBits);
330 // Increment the pointer to the other half.
331 unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
332 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
333 DAG.getIntPtrConstant(IncrementSize));
334 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
335 SVOffset+IncrementSize, NEVT,
336 isVolatile, MinAlign(Alignment, IncrementSize));
338 // Build a factor node to remember that this load is independent of the
340 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
343 // Big-endian - high bits are at low addresses. Favor aligned loads at
344 // the cost of some bit-fiddling.
345 MVT::ValueType EVT = N->getMemoryVT();
346 unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8;
347 unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
348 unsigned ExcessBits = (EBytes - IncrementSize)*8;
350 // Load both the high bits and maybe some of the low bits.
351 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
352 MVT::getIntegerType(MVT::getSizeInBits(EVT)-ExcessBits),
353 isVolatile, Alignment);
355 // Increment the pointer to the other half.
356 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
357 DAG.getIntPtrConstant(IncrementSize));
358 // Load the rest of the low bits.
359 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
360 SVOffset+IncrementSize, MVT::getIntegerType(ExcessBits),
361 isVolatile, MinAlign(Alignment, IncrementSize));
363 // Build a factor node to remember that this load is independent of the
365 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
368 if (ExcessBits < MVT::getSizeInBits(NVT)) {
369 // Transfer low bits from the bottom of Hi to the top of Lo.
370 Lo = DAG.getNode(ISD::OR, NVT, Lo,
371 DAG.getNode(ISD::SHL, NVT, Hi,
372 DAG.getConstant(ExcessBits,
373 TLI.getShiftAmountTy())));
374 // Move high bits to the right position in Hi.
375 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
376 DAG.getConstant(MVT::getSizeInBits(NVT) - ExcessBits,
377 TLI.getShiftAmountTy()));
381 // Legalized the chain result - switch anything that used the old chain to
383 ReplaceValueWith(SDOperand(N, 1), Ch);
386 void DAGTypeLegalizer::ExpandResult_Logical(SDNode *N,
387 SDOperand &Lo, SDOperand &Hi) {
388 SDOperand LL, LH, RL, RH;
389 GetExpandedOp(N->getOperand(0), LL, LH);
390 GetExpandedOp(N->getOperand(1), RL, RH);
391 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
392 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
395 void DAGTypeLegalizer::ExpandResult_BSWAP(SDNode *N,
396 SDOperand &Lo, SDOperand &Hi) {
397 GetExpandedOp(N->getOperand(0), Hi, Lo); // Note swapped operands.
398 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
399 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
402 void DAGTypeLegalizer::ExpandResult_SELECT(SDNode *N,
403 SDOperand &Lo, SDOperand &Hi) {
404 SDOperand LL, LH, RL, RH;
405 GetExpandedOp(N->getOperand(1), LL, LH);
406 GetExpandedOp(N->getOperand(2), RL, RH);
407 Lo = DAG.getNode(ISD::SELECT, LL.getValueType(), N->getOperand(0), LL, RL);
409 assert(N->getOperand(0).getValueType() != MVT::f32 &&
410 "FIXME: softfp shouldn't use expand!");
411 Hi = DAG.getNode(ISD::SELECT, LL.getValueType(), N->getOperand(0), LH, RH);
414 void DAGTypeLegalizer::ExpandResult_SELECT_CC(SDNode *N,
415 SDOperand &Lo, SDOperand &Hi) {
416 SDOperand LL, LH, RL, RH;
417 GetExpandedOp(N->getOperand(2), LL, LH);
418 GetExpandedOp(N->getOperand(3), RL, RH);
419 Lo = DAG.getNode(ISD::SELECT_CC, LL.getValueType(), N->getOperand(0),
420 N->getOperand(1), LL, RL, N->getOperand(4));
422 assert(N->getOperand(0).getValueType() != MVT::f32 &&
423 "FIXME: softfp shouldn't use expand!");
424 Hi = DAG.getNode(ISD::SELECT_CC, LL.getValueType(), N->getOperand(0),
425 N->getOperand(1), LH, RH, N->getOperand(4));
428 void DAGTypeLegalizer::ExpandResult_ADDSUB(SDNode *N,
429 SDOperand &Lo, SDOperand &Hi) {
430 // Expand the subcomponents.
431 SDOperand LHSL, LHSH, RHSL, RHSH;
432 GetExpandedOp(N->getOperand(0), LHSL, LHSH);
433 GetExpandedOp(N->getOperand(1), RHSL, RHSH);
434 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
435 SDOperand LoOps[2] = { LHSL, RHSL };
436 SDOperand HiOps[3] = { LHSH, RHSH };
438 if (N->getOpcode() == ISD::ADD) {
439 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
440 HiOps[2] = Lo.getValue(1);
441 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
443 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
444 HiOps[2] = Lo.getValue(1);
445 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
449 void DAGTypeLegalizer::ExpandResult_ADDSUBC(SDNode *N,
450 SDOperand &Lo, SDOperand &Hi) {
451 // Expand the subcomponents.
452 SDOperand LHSL, LHSH, RHSL, RHSH;
453 GetExpandedOp(N->getOperand(0), LHSL, LHSH);
454 GetExpandedOp(N->getOperand(1), RHSL, RHSH);
455 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
456 SDOperand LoOps[2] = { LHSL, RHSL };
457 SDOperand HiOps[3] = { LHSH, RHSH };
459 if (N->getOpcode() == ISD::ADDC) {
460 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
461 HiOps[2] = Lo.getValue(1);
462 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
464 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
465 HiOps[2] = Lo.getValue(1);
466 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
469 // Legalized the flag result - switch anything that used the old flag to
471 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
474 void DAGTypeLegalizer::ExpandResult_ADDSUBE(SDNode *N,
475 SDOperand &Lo, SDOperand &Hi) {
476 // Expand the subcomponents.
477 SDOperand LHSL, LHSH, RHSL, RHSH;
478 GetExpandedOp(N->getOperand(0), LHSL, LHSH);
479 GetExpandedOp(N->getOperand(1), RHSL, RHSH);
480 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
481 SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
482 SDOperand HiOps[3] = { LHSH, RHSH };
484 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
485 HiOps[2] = Lo.getValue(1);
486 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
488 // Legalized the flag result - switch anything that used the old flag to
490 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
493 void DAGTypeLegalizer::ExpandResult_MUL(SDNode *N,
494 SDOperand &Lo, SDOperand &Hi) {
495 MVT::ValueType VT = N->getValueType(0);
496 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
498 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
499 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
500 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
501 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
502 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
503 SDOperand LL, LH, RL, RH;
504 GetExpandedOp(N->getOperand(0), LL, LH);
505 GetExpandedOp(N->getOperand(1), RL, RH);
506 unsigned BitSize = MVT::getSizeInBits(NVT);
507 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
508 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
510 // FIXME: generalize this to handle other bit sizes
511 if (LHSSB == 32 && RHSSB == 32 &&
512 DAG.MaskedValueIsZero(N->getOperand(0), 0xFFFFFFFF00000000ULL) &&
513 DAG.MaskedValueIsZero(N->getOperand(1), 0xFFFFFFFF00000000ULL)) {
514 // The inputs are both zero-extended.
516 // We can emit a umul_lohi.
517 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
518 Hi = SDOperand(Lo.Val, 1);
522 // We can emit a mulhu+mul.
523 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
524 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
528 if (LHSSB > BitSize && RHSSB > BitSize) {
529 // The input values are both sign-extended.
531 // We can emit a smul_lohi.
532 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
533 Hi = SDOperand(Lo.Val, 1);
537 // We can emit a mulhs+mul.
538 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
539 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
544 // Lo,Hi = umul LHS, RHS.
545 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
546 DAG.getVTList(NVT, NVT), LL, RL);
548 Hi = UMulLOHI.getValue(1);
549 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
550 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
551 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
552 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
559 // If nothing else, we can make a libcall.
560 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), N,
561 false/*sign irrelevant*/, Hi);
566 void DAGTypeLegalizer::ExpandResult_Shift(SDNode *N,
567 SDOperand &Lo, SDOperand &Hi) {
568 MVT::ValueType VT = N->getValueType(0);
570 // If we can emit an efficient shift operation, do so now. Check to see if
571 // the RHS is a constant.
572 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
573 return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi);
575 // If we can determine that the high bit of the shift is zero or one, even if
576 // the low bits are variable, emit this shift in an optimized form.
577 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
580 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
582 if (N->getOpcode() == ISD::SHL)
583 PartsOpc = ISD::SHL_PARTS;
584 else if (N->getOpcode() == ISD::SRL)
585 PartsOpc = ISD::SRL_PARTS;
587 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
588 PartsOpc = ISD::SRA_PARTS;
591 // Next check to see if the target supports this SHL_PARTS operation or if it
592 // will custom expand it.
593 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
594 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
595 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
596 Action == TargetLowering::Custom) {
597 // Expand the subcomponents.
598 SDOperand LHSL, LHSH;
599 GetExpandedOp(N->getOperand(0), LHSL, LHSH);
601 SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) };
602 MVT::ValueType VT = LHSL.getValueType();
603 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
610 // Otherwise, emit a libcall.
611 unsigned RuntimeCode = ; // SRL -> SRL_I64 etc.
613 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), N,
614 false/*lshr is unsigned*/, Hi);
619 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
620 /// and the shift amount is a constant 'Amt'. Expand the operation.
621 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
622 SDOperand &Lo, SDOperand &Hi) {
623 // Expand the incoming operand to be shifted, so that we have its parts
625 GetExpandedOp(N->getOperand(0), InL, InH);
627 MVT::ValueType NVT = InL.getValueType();
628 unsigned VTBits = MVT::getSizeInBits(N->getValueType(0));
629 unsigned NVTBits = MVT::getSizeInBits(NVT);
630 MVT::ValueType ShTy = N->getOperand(1).getValueType();
632 if (N->getOpcode() == ISD::SHL) {
634 Lo = Hi = DAG.getConstant(0, NVT);
635 } else if (Amt > NVTBits) {
636 Lo = DAG.getConstant(0, NVT);
637 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
638 } else if (Amt == NVTBits) {
639 Lo = DAG.getConstant(0, NVT);
642 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
643 Hi = DAG.getNode(ISD::OR, NVT,
644 DAG.getNode(ISD::SHL, NVT, InH,
645 DAG.getConstant(Amt, ShTy)),
646 DAG.getNode(ISD::SRL, NVT, InL,
647 DAG.getConstant(NVTBits-Amt, ShTy)));
652 if (N->getOpcode() == ISD::SRL) {
654 Lo = DAG.getConstant(0, NVT);
655 Hi = DAG.getConstant(0, NVT);
656 } else if (Amt > NVTBits) {
657 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
658 Hi = DAG.getConstant(0, NVT);
659 } else if (Amt == NVTBits) {
661 Hi = DAG.getConstant(0, NVT);
663 Lo = DAG.getNode(ISD::OR, NVT,
664 DAG.getNode(ISD::SRL, NVT, InL,
665 DAG.getConstant(Amt, ShTy)),
666 DAG.getNode(ISD::SHL, NVT, InH,
667 DAG.getConstant(NVTBits-Amt, ShTy)));
668 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
673 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
675 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
676 DAG.getConstant(NVTBits-1, ShTy));
677 } else if (Amt > NVTBits) {
678 Lo = DAG.getNode(ISD::SRA, NVT, InH,
679 DAG.getConstant(Amt-NVTBits, ShTy));
680 Hi = DAG.getNode(ISD::SRA, NVT, InH,
681 DAG.getConstant(NVTBits-1, ShTy));
682 } else if (Amt == NVTBits) {
684 Hi = DAG.getNode(ISD::SRA, NVT, InH,
685 DAG.getConstant(NVTBits-1, ShTy));
687 Lo = DAG.getNode(ISD::OR, NVT,
688 DAG.getNode(ISD::SRL, NVT, InL,
689 DAG.getConstant(Amt, ShTy)),
690 DAG.getNode(ISD::SHL, NVT, InH,
691 DAG.getConstant(NVTBits-Amt, ShTy)));
692 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
696 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
697 /// this shift based on knowledge of the high bit of the shift amount. If we
698 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
700 bool DAGTypeLegalizer::
701 ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
702 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
703 unsigned NVTBits = MVT::getSizeInBits(NVT);
704 assert(!(NVTBits & (NVTBits - 1)) &&
705 "Expanded integer type size not a power of two!");
707 uint64_t HighBitMask = NVTBits, KnownZero, KnownOne;
708 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
710 // If we don't know anything about the high bit, exit.
711 if (((KnownZero|KnownOne) & HighBitMask) == 0)
714 // Get the incoming operand to be shifted.
716 GetExpandedOp(N->getOperand(0), InL, InH);
717 SDOperand Amt = N->getOperand(1);
719 // If we know that the high bit of the shift amount is one, then we can do
720 // this as a couple of simple shifts.
721 if (KnownOne & HighBitMask) {
722 // Mask out the high bit, which we know is set.
723 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
724 DAG.getConstant(NVTBits-1, Amt.getValueType()));
726 switch (N->getOpcode()) {
727 default: assert(0 && "Unknown shift");
729 Lo = DAG.getConstant(0, NVT); // Low part is zero.
730 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
733 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
734 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
737 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
738 DAG.getConstant(NVTBits-1, Amt.getValueType()));
739 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
744 // If we know that the high bit of the shift amount is zero, then we can do
745 // this as a couple of simple shifts.
746 assert((KnownZero & HighBitMask) && "Bad mask computation above");
749 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
750 DAG.getConstant(NVTBits, Amt.getValueType()),
753 switch (N->getOpcode()) {
754 default: assert(0 && "Unknown shift");
755 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
757 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
760 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
761 Hi = DAG.getNode(ISD::OR, NVT,
762 DAG.getNode(Op1, NVT, InH, Amt),
763 DAG.getNode(Op2, NVT, InL, Amt2));
768 //===----------------------------------------------------------------------===//
770 //===----------------------------------------------------------------------===//
772 /// ExpandOperand - This method is called when the specified operand of the
773 /// specified node is found to need expansion. At this point, all of the result
774 /// types of the node are known to be legal, but other operands of the node may
775 /// need promotion or expansion as well as the specified one.
776 bool DAGTypeLegalizer::ExpandOperand(SDNode *N, unsigned OpNo) {
777 DEBUG(cerr << "Expand node operand: "; N->dump(&DAG); cerr << "\n");
780 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
781 == TargetLowering::Custom)
782 Res = TLI.LowerOperation(SDOperand(N, 0), DAG);
785 switch (N->getOpcode()) {
788 cerr << "ExpandOperand Op #" << OpNo << ": ";
789 N->dump(&DAG); cerr << "\n";
791 assert(0 && "Do not know how to expand this operator's operand!");
794 case ISD::TRUNCATE: Res = ExpandOperand_TRUNCATE(N); break;
795 case ISD::BIT_CONVERT: Res = ExpandOperand_BIT_CONVERT(N); break;
797 case ISD::SINT_TO_FP:
798 Res = ExpandOperand_SINT_TO_FP(N->getOperand(0), N->getValueType(0));
800 case ISD::UINT_TO_FP:
801 Res = ExpandOperand_UINT_TO_FP(N->getOperand(0), N->getValueType(0));
803 case ISD::EXTRACT_ELEMENT: Res = ExpandOperand_EXTRACT_ELEMENT(N); break;
804 case ISD::SETCC: Res = ExpandOperand_SETCC(N); break;
807 Res = ExpandOperand_STORE(cast<StoreSDNode>(N), OpNo);
811 case ISD::MEMMOVE: Res = HandleMemIntrinsic(N); break;
815 // If the result is null, the sub-method took care of registering results etc.
816 if (!Res.Val) return false;
817 // If the result is N, the sub-method updated N in place. Check to see if any
818 // operands are new, and if so, mark them.
820 // Mark N as new and remark N and its operands. This allows us to correctly
821 // revisit N if it needs another step of promotion and allows us to visit
822 // any new operands to N.
823 N->setNodeId(NewNode);
828 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
829 "Invalid operand expansion");
831 ReplaceValueWith(SDOperand(N, 0), Res);
835 SDOperand DAGTypeLegalizer::ExpandOperand_TRUNCATE(SDNode *N) {
837 GetExpandedOp(N->getOperand(0), InL, InH);
838 // Just truncate the low part of the source.
839 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
842 SDOperand DAGTypeLegalizer::ExpandOperand_BIT_CONVERT(SDNode *N) {
843 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
846 SDOperand DAGTypeLegalizer::ExpandOperand_SINT_TO_FP(SDOperand Source,
847 MVT::ValueType DestTy) {
848 // We know the destination is legal, but that the input needs to be expanded.
849 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
851 // Check to see if the target has a custom way to lower this. If so, use it.
852 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
853 default: assert(0 && "This action not implemented for this operation!");
854 case TargetLowering::Legal:
855 case TargetLowering::Expand:
856 break; // This case is handled below.
857 case TargetLowering::Custom:
858 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
860 if (NV.Val) return NV;
861 break; // The target lowered this.
865 if (DestTy == MVT::f32)
866 LC = RTLIB::SINTTOFP_I64_F32;
868 assert(DestTy == MVT::f64 && "Unknown fp value type!");
869 LC = RTLIB::SINTTOFP_I64_F64;
872 assert(0 && "FIXME: no libcalls yet!");
875 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
876 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
877 SDOperand UnusedHiPart;
878 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, true, UnusedHiPart);
882 SDOperand DAGTypeLegalizer::ExpandOperand_UINT_TO_FP(SDOperand Source,
883 MVT::ValueType DestTy) {
884 // We know the destination is legal, but that the input needs to be expanded.
885 assert(getTypeAction(Source.getValueType()) == Expand &&
886 "This is not an expansion!");
887 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
889 // If this is unsigned, and not supported, first perform the conversion to
890 // signed, then adjust the result if the sign bit is set.
891 SDOperand SignedConv = ExpandOperand_SINT_TO_FP(Source, DestTy);
893 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
894 // incoming integer is set. To handle this, we dynamically test to see if
895 // it is set, and, if so, add a fudge factor.
897 GetExpandedOp(Source, Lo, Hi);
899 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
900 DAG.getConstant(0, Hi.getValueType()),
902 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
903 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
904 SignSet, Four, Zero);
905 uint64_t FF = 0x5f800000ULL;
906 if (TLI.isLittleEndian()) FF <<= 32;
907 Constant *FudgeFactor = ConstantInt::get((Type*)Type::Int64Ty, FF);
909 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
910 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
911 SDOperand FudgeInReg;
912 if (DestTy == MVT::f32)
913 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
914 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
915 // FIXME: Avoid the extend by construction the right constantpool?
916 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
917 CPIdx, NULL, 0, MVT::f32);
919 assert(0 && "Unexpected conversion");
921 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
924 SDOperand DAGTypeLegalizer::ExpandOperand_EXTRACT_ELEMENT(SDNode *N) {
926 GetExpandedOp(N->getOperand(0), Lo, Hi);
927 return cast<ConstantSDNode>(N->getOperand(1))->getValue() ? Hi : Lo;
930 SDOperand DAGTypeLegalizer::ExpandOperand_SETCC(SDNode *N) {
931 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
932 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
933 ExpandSetCCOperands(NewLHS, NewRHS, CCCode);
935 // If ExpandSetCCOperands returned a scalar, use it.
936 if (NewRHS.Val == 0) return NewLHS;
938 // Otherwise, update N to have the operands specified.
939 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
940 DAG.getCondCode(CCCode));
943 /// ExpandSetCCOperands - Expand the operands of a comparison. This code is
944 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
945 void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS,
946 ISD::CondCode &CCCode) {
947 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
948 GetExpandedOp(NewLHS, LHSLo, LHSHi);
949 GetExpandedOp(NewRHS, RHSLo, RHSHi);
951 MVT::ValueType VT = NewLHS.getValueType();
952 if (VT == MVT::f32 || VT == MVT::f64) {
953 assert(0 && "FIXME: softfp not implemented yet! should be promote not exp");
956 if (VT == MVT::ppcf128) {
957 // FIXME: This generated code sucks. We want to generate
958 // FCMP crN, hi1, hi2
960 // FCMP crN, lo1, lo2
961 // The following can be improved, but not that much.
962 SDOperand Tmp1, Tmp2, Tmp3;
963 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
964 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
965 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
966 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
967 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
968 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
969 NewLHS = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
970 NewRHS = SDOperand(); // LHS is the result, not a compare.
975 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
977 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
978 if (RHSCST->isAllOnesValue()) {
979 // Equality comparison to -1.
980 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
985 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
986 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
987 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
988 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
992 // If this is a comparison of the sign bit, just look at the top part.
994 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
995 if ((CCCode == ISD::SETLT && CST->getValue() == 0) || // X < 0
996 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1002 // FIXME: This generated code sucks.
1003 ISD::CondCode LowCC;
1005 default: assert(0 && "Unknown integer setcc!");
1007 case ISD::SETULT: LowCC = ISD::SETULT; break;
1009 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1011 case ISD::SETULE: LowCC = ISD::SETULE; break;
1013 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1016 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1017 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1018 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1020 // NOTE: on targets without efficient SELECT of bools, we can always use
1021 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1022 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1023 SDOperand Tmp1, Tmp2;
1024 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
1025 false, DagCombineInfo);
1027 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
1028 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
1029 CCCode, false, DagCombineInfo);
1031 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,
1032 DAG.getCondCode(CCCode));
1034 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
1035 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
1036 if ((Tmp1C && Tmp1C->getValue() == 0) ||
1037 (Tmp2C && Tmp2C->getValue() == 0 &&
1038 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1039 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1040 (Tmp2C && Tmp2C->getValue() == 1 &&
1041 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1042 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1043 // low part is known false, returns high part.
1044 // For LE / GE, if high part is known false, ignore the low part.
1045 // For LT / GT, if high part is known true, ignore the low part.
1047 NewRHS = SDOperand();
1051 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
1052 ISD::SETEQ, false, DagCombineInfo);
1054 NewLHS = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
1055 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1056 NewLHS, Tmp1, Tmp2);
1057 NewRHS = SDOperand();
1060 SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
1061 assert(OpNo == 1 && "Can only expand the stored value so far");
1063 MVT::ValueType VT = N->getOperand(1).getValueType();
1064 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1065 SDOperand Ch = N->getChain();
1066 SDOperand Ptr = N->getBasePtr();
1067 int SVOffset = N->getSrcValueOffset();
1068 unsigned Alignment = N->getAlignment();
1069 bool isVolatile = N->isVolatile();
1072 assert(!(MVT::getSizeInBits(NVT) & 7) && "Expanded type not byte sized!");
1074 if (!N->isTruncatingStore()) {
1075 unsigned IncrementSize = 0;
1076 GetExpandedOp(N->getValue(), Lo, Hi);
1077 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1079 if (TLI.isBigEndian())
1082 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(),
1083 SVOffset, isVolatile, Alignment);
1085 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1086 DAG.getIntPtrConstant(IncrementSize));
1087 assert(isTypeLegal(Ptr.getValueType()) && "Pointers must be legal!");
1088 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
1089 isVolatile, MinAlign(Alignment, IncrementSize));
1090 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1091 } else if (MVT::getSizeInBits(N->getMemoryVT()) <= MVT::getSizeInBits(NVT)) {
1092 GetExpandedOp(N->getValue(), Lo, Hi);
1093 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1094 N->getMemoryVT(), isVolatile, Alignment);
1095 } else if (TLI.isLittleEndian()) {
1096 // Little-endian - low bits are at low addresses.
1097 GetExpandedOp(N->getValue(), Lo, Hi);
1099 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1100 isVolatile, Alignment);
1102 unsigned ExcessBits =
1103 MVT::getSizeInBits(N->getMemoryVT()) - MVT::getSizeInBits(NVT);
1104 MVT::ValueType NEVT = MVT::getIntegerType(ExcessBits);
1106 // Increment the pointer to the other half.
1107 unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
1108 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1109 DAG.getIntPtrConstant(IncrementSize));
1110 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1111 SVOffset+IncrementSize, NEVT,
1112 isVolatile, MinAlign(Alignment, IncrementSize));
1113 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1115 // Big-endian - high bits are at low addresses. Favor aligned stores at
1116 // the cost of some bit-fiddling.
1117 GetExpandedOp(N->getValue(), Lo, Hi);
1119 MVT::ValueType EVT = N->getMemoryVT();
1120 unsigned EBytes = MVT::getStoreSizeInBits(EVT)/8;
1121 unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
1122 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1123 MVT::ValueType HiVT =
1124 MVT::getIntegerType(MVT::getSizeInBits(EVT)-ExcessBits);
1126 if (ExcessBits < MVT::getSizeInBits(NVT)) {
1127 // Transfer high bits from the top of Lo to the bottom of Hi.
1128 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
1129 DAG.getConstant(MVT::getSizeInBits(NVT) - ExcessBits,
1130 TLI.getShiftAmountTy()));
1131 Hi = DAG.getNode(ISD::OR, NVT, Hi,
1132 DAG.getNode(ISD::SRL, NVT, Lo,
1133 DAG.getConstant(ExcessBits,
1134 TLI.getShiftAmountTy())));
1137 // Store both the high bits and maybe some of the low bits.
1138 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1139 SVOffset, HiVT, isVolatile, Alignment);
1141 // Increment the pointer to the other half.
1142 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1143 DAG.getIntPtrConstant(IncrementSize));
1144 // Store the lowest ExcessBits bits in the second half.
1145 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
1146 SVOffset+IncrementSize,
1147 MVT::getIntegerType(ExcessBits),
1148 isVolatile, MinAlign(Alignment, IncrementSize));
1149 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);