1 //===-- LegalizeTypesPromote.cpp - Promotion for LegalizeTypes ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements promotion support for LegalizeTypes. Promotion is the
11 // act of changing a computation in an invalid type to be a computation in a
12 // larger type. For example, implementing i8 arithmetic in an i32 register (as
13 // is often needed on powerpc for example).
15 //===----------------------------------------------------------------------===//
17 #include "LegalizeTypes.h"
20 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
24 /// PromoteResult - This method is called when a result of a node is found to be
25 /// in need of promotion to a larger type. At this point, the node may also
26 /// have invalid operands or may have other results that need expansion, we just
27 /// know that (at least) one result needs promotion.
28 void DAGTypeLegalizer::PromoteResult(SDNode *N, unsigned ResNo) {
29 DEBUG(cerr << "Promote node result: "; N->dump(&DAG); cerr << "\n");
30 SDOperand Result = SDOperand();
32 switch (N->getOpcode()) {
35 cerr << "PromoteResult #" << ResNo << ": ";
36 N->dump(&DAG); cerr << "\n";
38 assert(0 && "Do not know how to promote this operator!");
40 case ISD::UNDEF: Result = PromoteResult_UNDEF(N); break;
41 case ISD::Constant: Result = PromoteResult_Constant(N); break;
43 case ISD::TRUNCATE: Result = PromoteResult_TRUNCATE(N); break;
44 case ISD::SIGN_EXTEND:
45 case ISD::ZERO_EXTEND:
46 case ISD::ANY_EXTEND: Result = PromoteResult_INT_EXTEND(N); break;
47 case ISD::FP_ROUND: Result = PromoteResult_FP_ROUND(N); break;
49 case ISD::FP_TO_UINT: Result = PromoteResult_FP_TO_XINT(N); break;
50 case ISD::SETCC: Result = PromoteResult_SETCC(N); break;
51 case ISD::LOAD: Result = PromoteResult_LOAD(cast<LoadSDNode>(N)); break;
52 case ISD::BUILD_PAIR: Result = PromoteResult_BUILD_PAIR(N); break;
53 case ISD::BIT_CONVERT: Result = PromoteResult_BIT_CONVERT(N); break;
60 case ISD::MUL: Result = PromoteResult_SimpleIntBinOp(N); break;
63 case ISD::SREM: Result = PromoteResult_SDIV(N); break;
66 case ISD::UREM: Result = PromoteResult_UDIV(N); break;
68 case ISD::SHL: Result = PromoteResult_SHL(N); break;
69 case ISD::SRA: Result = PromoteResult_SRA(N); break;
70 case ISD::SRL: Result = PromoteResult_SRL(N); break;
72 case ISD::SELECT: Result = PromoteResult_SELECT(N); break;
73 case ISD::SELECT_CC: Result = PromoteResult_SELECT_CC(N); break;
75 case ISD::CTLZ: Result = PromoteResult_CTLZ(N); break;
76 case ISD::CTPOP: Result = PromoteResult_CTPOP(N); break;
77 case ISD::CTTZ: Result = PromoteResult_CTTZ(N); break;
79 case ISD::EXTRACT_VECTOR_ELT:
80 Result = PromoteResult_EXTRACT_VECTOR_ELT(N);
84 // If Result is null, the sub-method took care of registering the result.
86 SetPromotedOp(SDOperand(N, ResNo), Result);
89 SDOperand DAGTypeLegalizer::PromoteResult_UNDEF(SDNode *N) {
90 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
93 SDOperand DAGTypeLegalizer::PromoteResult_Constant(SDNode *N) {
94 MVT::ValueType VT = N->getValueType(0);
95 // Zero extend things like i1, sign extend everything else. It shouldn't
96 // matter in theory which one we pick, but this tends to give better code?
97 unsigned Opc = VT != MVT::i1 ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
98 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
100 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
104 SDOperand DAGTypeLegalizer::PromoteResult_TRUNCATE(SDNode *N) {
107 switch (getTypeAction(N->getOperand(0).getValueType())) {
108 default: assert(0 && "Unknown type action!");
111 Res = N->getOperand(0);
114 Res = GetPromotedOp(N->getOperand(0));
118 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
119 assert(MVT::getSizeInBits(Res.getValueType()) >= MVT::getSizeInBits(NVT) &&
120 "Truncation doesn't make sense!");
121 if (Res.getValueType() == NVT)
124 // Truncate to NVT instead of VT
125 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
128 SDOperand DAGTypeLegalizer::PromoteResult_INT_EXTEND(SDNode *N) {
129 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
131 if (getTypeAction(N->getOperand(0).getValueType()) == Promote) {
132 SDOperand Res = GetPromotedOp(N->getOperand(0));
133 assert(MVT::getSizeInBits(Res.getValueType()) <= MVT::getSizeInBits(NVT) &&
134 "Extension doesn't make sense!");
136 // If the result and operand types are the same after promotion, simplify
137 // to an in-register extension.
138 if (NVT == Res.getValueType()) {
139 // The high bits are not guaranteed to be anything. Insert an extend.
140 if (N->getOpcode() == ISD::SIGN_EXTEND)
141 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
142 DAG.getValueType(N->getOperand(0).getValueType()));
143 if (N->getOpcode() == ISD::ZERO_EXTEND)
144 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
145 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
150 // Otherwise, just extend the original operand all the way to the larger type.
151 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
154 SDOperand DAGTypeLegalizer::PromoteResult_FP_ROUND(SDNode *N) {
155 // NOTE: Assumes input is legal.
156 if (N->getConstantOperandVal(1) == 0)
157 return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
158 N->getOperand(0), DAG.getValueType(N->getValueType(0)));
159 // If the precision discard isn't needed, just return the operand unrounded.
160 return N->getOperand(0);
163 SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) {
164 SDOperand Op = N->getOperand(0);
165 // If the operand needed to be promoted, do so now.
166 if (getTypeAction(Op.getValueType()) == Promote)
167 // The input result is prerounded, so we don't have to do anything special.
168 Op = GetPromotedOp(Op);
170 unsigned NewOpc = N->getOpcode();
171 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
173 // If we're promoting a UINT to a larger size, check to see if the new node
174 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
175 // we can use that instead. This allows us to generate better code for
176 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
177 // legal, such as PowerPC.
178 if (N->getOpcode() == ISD::FP_TO_UINT) {
179 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
180 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
181 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
182 NewOpc = ISD::FP_TO_SINT;
185 return DAG.getNode(NewOpc, NVT, Op);
188 SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) {
189 assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
190 && "SetCC type is not legal??");
191 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
192 N->getOperand(0), N->getOperand(1), N->getOperand(2));
195 SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) {
196 // FIXME: Add support for indexed loads.
197 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
198 ISD::LoadExtType ExtType =
199 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
200 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
201 N->getSrcValue(), N->getSrcValueOffset(),
202 N->getMemoryVT(), N->isVolatile(),
205 // Legalized the chain result - switch anything that used the old chain to
207 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
211 SDOperand DAGTypeLegalizer::PromoteResult_BUILD_PAIR(SDNode *N) {
212 // The pair element type may be legal, or may not promote to the same type as
213 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
214 return DAG.getNode(ISD::ANY_EXTEND,
215 TLI.getTypeToTransformTo(N->getValueType(0)),
216 JoinIntegers(N->getOperand(0), N->getOperand(1)));
219 SDOperand DAGTypeLegalizer::PromoteResult_BIT_CONVERT(SDNode *N) {
220 SDOperand InOp = N->getOperand(0);
221 MVT::ValueType InVT = InOp.getValueType();
222 MVT::ValueType NInVT = TLI.getTypeToTransformTo(InVT);
223 MVT::ValueType OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
225 switch (getTypeAction(InVT)) {
227 assert(false && "Unknown type action!");
232 if (MVT::getSizeInBits(OutVT) == MVT::getSizeInBits(NInVT))
233 // The input promotes to the same size. Convert the promoted value.
234 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedOp(InOp));
239 // Promote the integer operand by hand.
240 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetIntegerOp(InOp));
242 // Convert the element to an integer and promote it by hand.
243 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
244 BitConvertToInteger(GetScalarizedOp(InOp)));
246 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
247 // pieces of the input into integers and reassemble in the final type.
249 GetSplitOp(N->getOperand(0), Lo, Hi);
250 Lo = BitConvertToInteger(Lo);
251 Hi = BitConvertToInteger(Hi);
253 if (TLI.isBigEndian())
256 InOp = DAG.getNode(ISD::ANY_EXTEND,
257 MVT::getIntegerType(MVT::getSizeInBits(OutVT)),
258 JoinIntegers(Lo, Hi));
259 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
262 // Otherwise, lower the bit-convert to a store/load from the stack, then
264 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
265 return PromoteResult_LOAD(cast<LoadSDNode>(Op.Val));
268 SDOperand DAGTypeLegalizer::PromoteResult_SimpleIntBinOp(SDNode *N) {
269 // The input may have strange things in the top bits of the registers, but
270 // these operations don't care. They may have weird bits going out, but
271 // that too is okay if they are integer operations.
272 SDOperand LHS = GetPromotedOp(N->getOperand(0));
273 SDOperand RHS = GetPromotedOp(N->getOperand(1));
274 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
277 SDOperand DAGTypeLegalizer::PromoteResult_SDIV(SDNode *N) {
278 // Sign extend the input.
279 SDOperand LHS = GetPromotedOp(N->getOperand(0));
280 SDOperand RHS = GetPromotedOp(N->getOperand(1));
281 MVT::ValueType VT = N->getValueType(0);
282 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
283 DAG.getValueType(VT));
284 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
285 DAG.getValueType(VT));
287 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
290 SDOperand DAGTypeLegalizer::PromoteResult_UDIV(SDNode *N) {
291 // Zero extend the input.
292 SDOperand LHS = GetPromotedOp(N->getOperand(0));
293 SDOperand RHS = GetPromotedOp(N->getOperand(1));
294 MVT::ValueType VT = N->getValueType(0);
295 LHS = DAG.getZeroExtendInReg(LHS, VT);
296 RHS = DAG.getZeroExtendInReg(RHS, VT);
298 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
301 SDOperand DAGTypeLegalizer::PromoteResult_SHL(SDNode *N) {
302 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
303 GetPromotedOp(N->getOperand(0)), N->getOperand(1));
306 SDOperand DAGTypeLegalizer::PromoteResult_SRA(SDNode *N) {
307 // The input value must be properly sign extended.
308 MVT::ValueType VT = N->getValueType(0);
309 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
310 SDOperand Res = GetPromotedOp(N->getOperand(0));
311 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
312 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
315 SDOperand DAGTypeLegalizer::PromoteResult_SRL(SDNode *N) {
316 // The input value must be properly zero extended.
317 MVT::ValueType VT = N->getValueType(0);
318 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
319 SDOperand Res = GetPromotedZExtOp(N->getOperand(0));
320 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
323 SDOperand DAGTypeLegalizer::PromoteResult_SELECT(SDNode *N) {
324 SDOperand LHS = GetPromotedOp(N->getOperand(1));
325 SDOperand RHS = GetPromotedOp(N->getOperand(2));
326 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
329 SDOperand DAGTypeLegalizer::PromoteResult_SELECT_CC(SDNode *N) {
330 SDOperand LHS = GetPromotedOp(N->getOperand(2));
331 SDOperand RHS = GetPromotedOp(N->getOperand(3));
332 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
333 N->getOperand(1), LHS, RHS, N->getOperand(4));
336 SDOperand DAGTypeLegalizer::PromoteResult_CTLZ(SDNode *N) {
337 SDOperand Op = GetPromotedOp(N->getOperand(0));
338 MVT::ValueType OVT = N->getValueType(0);
339 MVT::ValueType NVT = Op.getValueType();
340 // Zero extend to the promoted type and do the count there.
341 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
342 // Subtract off the extra leading bits in the bigger type.
343 return DAG.getNode(ISD::SUB, NVT, Op,
344 DAG.getConstant(MVT::getSizeInBits(NVT) -
345 MVT::getSizeInBits(OVT), NVT));
348 SDOperand DAGTypeLegalizer::PromoteResult_CTPOP(SDNode *N) {
349 SDOperand Op = GetPromotedOp(N->getOperand(0));
350 MVT::ValueType OVT = N->getValueType(0);
351 MVT::ValueType NVT = Op.getValueType();
352 // Zero extend to the promoted type and do the count there.
353 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
356 SDOperand DAGTypeLegalizer::PromoteResult_CTTZ(SDNode *N) {
357 SDOperand Op = GetPromotedOp(N->getOperand(0));
358 MVT::ValueType OVT = N->getValueType(0);
359 MVT::ValueType NVT = Op.getValueType();
360 // The count is the same in the promoted type except if the original
361 // value was zero. This can be handled by setting the bit just off
362 // the top of the original type.
363 Op = DAG.getNode(ISD::OR, NVT, Op,
364 // FIXME: Do this using an APINT constant.
365 DAG.getConstant(1UL << MVT::getSizeInBits(OVT), NVT));
366 return DAG.getNode(ISD::CTTZ, NVT, Op);
369 SDOperand DAGTypeLegalizer::PromoteResult_EXTRACT_VECTOR_ELT(SDNode *N) {
370 MVT::ValueType OldVT = N->getValueType(0);
371 SDOperand OldVec = N->getOperand(0);
372 unsigned OldElts = MVT::getVectorNumElements(OldVec.getValueType());
375 assert(!isTypeLegal(OldVec.getValueType()) &&
376 "Legal one-element vector of a type needing promotion!");
377 // It is tempting to follow GetScalarizedOp by a call to GetPromotedOp,
378 // but this would be wrong because the scalarized value may not yet have
380 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
381 GetScalarizedOp(OldVec));
384 // Convert to a vector half as long with an element type of twice the width,
385 // for example <4 x i16> -> <2 x i32>.
386 assert(!(OldElts & 1) && "Odd length vectors not supported!");
387 MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT));
388 assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT));
390 SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
391 MVT::getVectorType(NewVT, OldElts / 2),
394 // Extract the element at OldIdx / 2 from the new vector.
395 SDOperand OldIdx = N->getOperand(1);
396 SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
397 DAG.getConstant(1, TLI.getShiftAmountTy()));
398 SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
400 // Select the appropriate half of the element: Lo if OldIdx was even,
403 SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
404 DAG.getConstant(MVT::getSizeInBits(OldVT),
405 TLI.getShiftAmountTy()));
406 if (TLI.isBigEndian())
409 SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
410 DAG.getConstant(1, TLI.getShiftAmountTy()));
411 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
414 //===----------------------------------------------------------------------===//
416 //===----------------------------------------------------------------------===//
418 /// PromoteOperand - This method is called when the specified operand of the
419 /// specified node is found to need promotion. At this point, all of the result
420 /// types of the node are known to be legal, but other operands of the node may
421 /// need promotion or expansion as well as the specified one.
422 bool DAGTypeLegalizer::PromoteOperand(SDNode *N, unsigned OpNo) {
423 DEBUG(cerr << "Promote node operand: "; N->dump(&DAG); cerr << "\n");
425 switch (N->getOpcode()) {
428 cerr << "PromoteOperand Op #" << OpNo << ": ";
429 N->dump(&DAG); cerr << "\n";
431 assert(0 && "Do not know how to promote this operator's operand!");
434 case ISD::ANY_EXTEND: Res = PromoteOperand_ANY_EXTEND(N); break;
435 case ISD::ZERO_EXTEND: Res = PromoteOperand_ZERO_EXTEND(N); break;
436 case ISD::SIGN_EXTEND: Res = PromoteOperand_SIGN_EXTEND(N); break;
437 case ISD::TRUNCATE: Res = PromoteOperand_TRUNCATE(N); break;
438 case ISD::FP_EXTEND: Res = PromoteOperand_FP_EXTEND(N); break;
439 case ISD::FP_ROUND: Res = PromoteOperand_FP_ROUND(N); break;
440 case ISD::SINT_TO_FP:
441 case ISD::UINT_TO_FP: Res = PromoteOperand_INT_TO_FP(N); break;
442 case ISD::BUILD_PAIR: Res = PromoteOperand_BUILD_PAIR(N); break;
444 case ISD::SELECT: Res = PromoteOperand_SELECT(N, OpNo); break;
445 case ISD::BRCOND: Res = PromoteOperand_BRCOND(N, OpNo); break;
446 case ISD::BR_CC: Res = PromoteOperand_BR_CC(N, OpNo); break;
447 case ISD::SETCC: Res = PromoteOperand_SETCC(N, OpNo); break;
449 case ISD::STORE: Res = PromoteOperand_STORE(cast<StoreSDNode>(N),
452 case ISD::BUILD_VECTOR: Res = PromoteOperand_BUILD_VECTOR(N); break;
453 case ISD::INSERT_VECTOR_ELT:
454 Res = PromoteOperand_INSERT_VECTOR_ELT(N, OpNo);
457 case ISD::RET: Res = PromoteOperand_RET(N, OpNo); break;
459 case ISD::MEMBARRIER: Res = PromoteOperand_MEMBARRIER(N); break;
462 // If the result is null, the sub-method took care of registering results etc.
463 if (!Res.Val) return false;
464 // If the result is N, the sub-method updated N in place.
466 // Mark N as new and remark N and its operands. This allows us to correctly
467 // revisit N if it needs another step of promotion and allows us to visit
468 // any new operands to N.
473 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
474 "Invalid operand expansion");
476 ReplaceValueWith(SDOperand(N, 0), Res);
480 SDOperand DAGTypeLegalizer::PromoteOperand_ANY_EXTEND(SDNode *N) {
481 SDOperand Op = GetPromotedOp(N->getOperand(0));
482 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
485 SDOperand DAGTypeLegalizer::PromoteOperand_ZERO_EXTEND(SDNode *N) {
486 SDOperand Op = GetPromotedOp(N->getOperand(0));
487 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
488 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
491 SDOperand DAGTypeLegalizer::PromoteOperand_SIGN_EXTEND(SDNode *N) {
492 SDOperand Op = GetPromotedOp(N->getOperand(0));
493 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
494 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
495 Op, DAG.getValueType(N->getOperand(0).getValueType()));
498 SDOperand DAGTypeLegalizer::PromoteOperand_TRUNCATE(SDNode *N) {
499 SDOperand Op = GetPromotedOp(N->getOperand(0));
500 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
503 SDOperand DAGTypeLegalizer::PromoteOperand_FP_EXTEND(SDNode *N) {
504 SDOperand Op = GetPromotedOp(N->getOperand(0));
505 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
508 SDOperand DAGTypeLegalizer::PromoteOperand_FP_ROUND(SDNode *N) {
509 SDOperand Op = GetPromotedOp(N->getOperand(0));
510 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
511 DAG.getIntPtrConstant(0));
514 SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) {
515 SDOperand In = GetPromotedOp(N->getOperand(0));
516 MVT::ValueType OpVT = N->getOperand(0).getValueType();
517 if (N->getOpcode() == ISD::UINT_TO_FP)
518 In = DAG.getZeroExtendInReg(In, OpVT);
520 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
521 In, DAG.getValueType(OpVT));
523 return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
526 SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_PAIR(SDNode *N) {
527 // Since the result type is legal, the operands must promote to it.
528 MVT::ValueType OVT = N->getOperand(0).getValueType();
529 SDOperand Lo = GetPromotedOp(N->getOperand(0));
530 SDOperand Hi = GetPromotedOp(N->getOperand(1));
531 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
533 Lo = DAG.getZeroExtendInReg(Lo, OVT);
534 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
535 DAG.getConstant(MVT::getSizeInBits(OVT),
536 TLI.getShiftAmountTy()));
537 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
540 SDOperand DAGTypeLegalizer::PromoteOperand_SELECT(SDNode *N, unsigned OpNo) {
541 assert(OpNo == 0 && "Only know how to promote condition");
542 SDOperand Cond = GetPromotedOp(N->getOperand(0)); // Promote the condition.
544 // The top bits of the promoted condition are not necessarily zero, ensure
545 // that the value is properly zero extended.
546 unsigned BitWidth = Cond.getValueSizeInBits();
547 if (!DAG.MaskedValueIsZero(Cond,
548 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
549 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
551 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
552 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
556 SDOperand DAGTypeLegalizer::PromoteOperand_BRCOND(SDNode *N, unsigned OpNo) {
557 assert(OpNo == 1 && "only know how to promote condition");
558 SDOperand Cond = GetPromotedOp(N->getOperand(1)); // Promote the condition.
560 // The top bits of the promoted condition are not necessarily zero, ensure
561 // that the value is properly zero extended.
562 unsigned BitWidth = Cond.getValueSizeInBits();
563 if (!DAG.MaskedValueIsZero(Cond,
564 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
565 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
567 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
568 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
572 SDOperand DAGTypeLegalizer::PromoteOperand_BR_CC(SDNode *N, unsigned OpNo) {
573 assert(OpNo == 2 && "Don't know how to promote this operand");
575 SDOperand LHS = N->getOperand(2);
576 SDOperand RHS = N->getOperand(3);
577 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
579 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
581 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
582 N->getOperand(1), LHS, RHS, N->getOperand(4));
585 SDOperand DAGTypeLegalizer::PromoteOperand_SETCC(SDNode *N, unsigned OpNo) {
586 assert(OpNo == 0 && "Don't know how to promote this operand");
588 SDOperand LHS = N->getOperand(0);
589 SDOperand RHS = N->getOperand(1);
590 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
592 // The CC (#2) is always legal.
593 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
596 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
597 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
598 void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
599 ISD::CondCode CCCode) {
600 MVT::ValueType VT = NewLHS.getValueType();
602 // Get the promoted values.
603 NewLHS = GetPromotedOp(NewLHS);
604 NewRHS = GetPromotedOp(NewRHS);
606 // If this is an FP compare, the operands have already been extended.
607 if (!MVT::isInteger(NewLHS.getValueType()))
610 // Otherwise, we have to insert explicit sign or zero extends. Note
611 // that we could insert sign extends for ALL conditions, but zero extend
612 // is cheaper on many machines (an AND instead of two shifts), so prefer
615 default: assert(0 && "Unknown integer comparison!");
622 // ALL of these operations will work if we either sign or zero extend
623 // the operands (including the unsigned comparisons!). Zero extend is
624 // usually a simpler/cheaper operation, so prefer it.
625 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
626 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
632 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
633 DAG.getValueType(VT));
634 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
635 DAG.getValueType(VT));
640 SDOperand DAGTypeLegalizer::PromoteOperand_STORE(StoreSDNode *N, unsigned OpNo){
641 // FIXME: Add support for indexed stores.
642 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
643 int SVOffset = N->getSrcValueOffset();
644 unsigned Alignment = N->getAlignment();
645 bool isVolatile = N->isVolatile();
647 SDOperand Val = GetPromotedOp(N->getValue()); // Get promoted value.
649 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
651 // Truncate the value and store the result.
652 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
653 SVOffset, N->getMemoryVT(),
654 isVolatile, Alignment);
657 SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_VECTOR(SDNode *N) {
658 // The vector type is legal but the element type is not. This implies
659 // that the vector is a power-of-two in length and that the element
660 // type does not have a strange size (eg: it is not i1).
661 MVT::ValueType VecVT = N->getValueType(0);
662 unsigned NumElts = MVT::getVectorNumElements(VecVT);
663 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
665 // Build a vector of half the length out of elements of twice the bitwidth.
666 // For example <4 x i16> -> <2 x i32>.
667 MVT::ValueType OldVT = N->getOperand(0).getValueType();
668 MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT));
669 assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT));
671 std::vector<SDOperand> NewElts;
672 NewElts.reserve(NumElts/2);
674 for (unsigned i = 0; i < NumElts; i += 2) {
675 // Combine two successive elements into one promoted element.
676 SDOperand Lo = N->getOperand(i);
677 SDOperand Hi = N->getOperand(i+1);
678 if (TLI.isBigEndian())
680 NewElts.push_back(JoinIntegers(Lo, Hi));
683 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
684 MVT::getVectorType(NewVT, NewElts.size()),
685 &NewElts[0], NewElts.size());
687 // Convert the new vector to the old vector type.
688 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
691 SDOperand DAGTypeLegalizer::PromoteOperand_INSERT_VECTOR_ELT(SDNode *N,
694 // Promote the inserted value. This is valid because the type does not
695 // have to match the vector element type.
697 // Check that any extra bits introduced will be truncated away.
698 assert(MVT::getSizeInBits(N->getOperand(1).getValueType()) >=
699 MVT::getSizeInBits(MVT::getVectorElementType(N->getValueType(0))) &&
700 "Type of inserted value narrower than vector element type!");
701 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
702 GetPromotedOp(N->getOperand(1)),
706 assert(OpNo == 2 && "Different operand and result vector types?");
708 // Promote the index.
709 SDOperand Idx = N->getOperand(2);
710 Idx = DAG.getZeroExtendInReg(GetPromotedOp(Idx), Idx.getValueType());
711 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
712 N->getOperand(1), Idx);
715 SDOperand DAGTypeLegalizer::PromoteOperand_RET(SDNode *N, unsigned OpNo) {
716 assert(!(OpNo & 1) && "Return values should be legally typed!");
717 assert((N->getNumOperands() & 1) && "Wrong number of operands!");
719 // It's a flag. Promote all the flags in one hit, as an optimization.
720 SmallVector<SDOperand, 8> NewValues(N->getNumOperands());
721 NewValues[0] = N->getOperand(0); // The chain
722 for (unsigned i = 1, e = N->getNumOperands(); i < e; i += 2) {
724 NewValues[i] = N->getOperand(i);
727 SDOperand Flag = N->getOperand(i + 1);
728 if (getTypeAction(Flag.getValueType()) == Promote)
729 // The promoted value may have rubbish in the new bits, but that
730 // doesn't matter because those bits aren't queried anyway.
731 Flag = GetPromotedOp(Flag);
732 NewValues[i + 1] = Flag;
735 return DAG.UpdateNodeOperands(SDOperand (N, 0),
736 &NewValues[0], NewValues.size());
739 SDOperand DAGTypeLegalizer::PromoteOperand_MEMBARRIER(SDNode *N) {
741 NewOps[0] = N->getOperand(0);
742 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
743 SDOperand Flag = GetPromotedOp(N->getOperand(i));
744 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
746 return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps,
747 array_lengthof(NewOps));