1 //===-- LegalizeTypesSplit.cpp - Vector Splitting for LegalizeTypes -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements vector splitting support for LegalizeTypes. Vector
11 // splitting is the act of changing a computation in an invalid vector type to
12 // be a computation in multiple vectors of a smaller type. For example,
13 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
15 //===----------------------------------------------------------------------===//
17 #include "LegalizeTypes.h"
20 /// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a vector
21 /// type that needs to be split. This handles non-power of two vectors.
22 static void GetSplitDestVTs(MVT::ValueType InVT,
23 MVT::ValueType &Lo, MVT::ValueType &Hi) {
24 MVT::ValueType NewEltVT = MVT::getVectorElementType(InVT);
25 unsigned NumElements = MVT::getVectorNumElements(InVT);
26 if ((NumElements & (NumElements-1)) == 0) { // Simple power of two vector.
28 Lo = Hi = MVT::getVectorType(NewEltVT, NumElements);
29 } else { // Non-power-of-two vectors.
30 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements);
31 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
32 Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
33 Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
38 //===----------------------------------------------------------------------===//
39 // Result Vector Splitting
40 //===----------------------------------------------------------------------===//
42 /// SplitResult - This method is called when the specified result of the
43 /// specified node is found to need vector splitting. At this point, the node
44 /// may also have invalid operands or may have other results that need
45 /// legalization, we just know that (at least) one result needs vector
47 void DAGTypeLegalizer::SplitResult(SDNode *N, unsigned ResNo) {
48 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
52 // See if the target wants to custom expand this node.
53 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
54 TargetLowering::Custom) {
55 // If the target wants to, allow it to lower this itself.
56 if (SDNode *P = TLI.ExpandOperationResult(N, DAG)) {
57 // Everything that once used N now uses P. We are guaranteed that the
58 // result value types of N and the result value types of P match.
59 ReplaceNodeWith(N, P);
65 switch (N->getOpcode()) {
68 cerr << "SplitResult #" << ResNo << ": ";
69 N->dump(&DAG); cerr << "\n";
71 assert(0 && "Do not know how to split the result of this operator!");
74 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
75 case ISD::LOAD: SplitRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
76 case ISD::BUILD_PAIR: SplitRes_BUILD_PAIR(N, Lo, Hi); break;
77 case ISD::INSERT_VECTOR_ELT:SplitRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
78 case ISD::VECTOR_SHUFFLE: SplitRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
79 case ISD::BUILD_VECTOR: SplitRes_BUILD_VECTOR(N, Lo, Hi); break;
80 case ISD::CONCAT_VECTORS: SplitRes_CONCAT_VECTORS(N, Lo, Hi); break;
81 case ISD::BIT_CONVERT: SplitRes_BIT_CONVERT(N, Lo, Hi); break;
93 case ISD::UINT_TO_FP: SplitRes_UnOp(N, Lo, Hi); break;
109 case ISD::FREM: SplitRes_BinOp(N, Lo, Hi); break;
110 case ISD::FPOWI: SplitRes_FPOWI(N, Lo, Hi); break;
111 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
114 // If Lo/Hi is null, the sub-method took care of registering results etc.
116 SetSplitOp(SDOperand(N, ResNo), Lo, Hi);
119 void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
120 MVT::ValueType LoVT, HiVT;
121 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
123 Lo = DAG.getNode(ISD::UNDEF, LoVT);
124 Hi = DAG.getNode(ISD::UNDEF, HiVT);
127 void DAGTypeLegalizer::SplitRes_LOAD(LoadSDNode *LD,
128 SDOperand &Lo, SDOperand &Hi) {
129 // FIXME: Add support for indexed loads.
130 MVT::ValueType LoVT, HiVT;
131 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
133 SDOperand Ch = LD->getChain();
134 SDOperand Ptr = LD->getBasePtr();
135 const Value *SV = LD->getSrcValue();
136 int SVOffset = LD->getSrcValueOffset();
137 unsigned Alignment = LD->getAlignment();
138 bool isVolatile = LD->isVolatile();
140 Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
141 unsigned IncrementSize = MVT::getSizeInBits(LoVT)/8;
142 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
143 DAG.getIntPtrConstant(IncrementSize));
144 SVOffset += IncrementSize;
145 Alignment = MinAlign(Alignment, IncrementSize);
146 Hi = DAG.getLoad(HiVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
148 // Build a factor node to remember that this load is independent of the
150 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
153 // Legalized the chain result - switch anything that used the old chain to
155 ReplaceValueWith(SDOperand(LD, 1), TF);
158 void DAGTypeLegalizer::SplitRes_BUILD_PAIR(SDNode *N, SDOperand &Lo,
160 Lo = N->getOperand(0);
161 Hi = N->getOperand(1);
164 void DAGTypeLegalizer::SplitRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
166 GetSplitOp(N->getOperand(0), Lo, Hi);
167 unsigned Index = cast<ConstantSDNode>(N->getOperand(2))->getValue();
168 SDOperand ScalarOp = N->getOperand(1);
169 unsigned LoNumElts = MVT::getVectorNumElements(Lo.getValueType());
170 if (Index < LoNumElts)
171 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, ScalarOp,
174 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, ScalarOp,
175 DAG.getIntPtrConstant(Index - LoNumElts));
178 void DAGTypeLegalizer::SplitRes_VECTOR_SHUFFLE(SDNode *N,
179 SDOperand &Lo, SDOperand &Hi) {
180 // Build the low part.
181 SDOperand Mask = N->getOperand(2);
182 SmallVector<SDOperand, 16> Ops;
183 MVT::ValueType LoVT, HiVT;
184 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
185 MVT::ValueType EltVT = MVT::getVectorElementType(LoVT);
186 unsigned LoNumElts = MVT::getVectorNumElements(LoVT);
187 unsigned NumElements = Mask.getNumOperands();
189 // Insert all of the elements from the input that are needed. We use
190 // buildvector of extractelement here because the input vectors will have
191 // to be legalized, so this makes the code simpler.
192 for (unsigned i = 0; i != LoNumElts; ++i) {
193 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
194 SDOperand InVec = N->getOperand(0);
195 if (Idx >= NumElements) {
196 InVec = N->getOperand(1);
199 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
200 DAG.getIntPtrConstant(Idx)));
202 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size());
205 for (unsigned i = LoNumElts; i != NumElements; ++i) {
206 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
207 SDOperand InVec = N->getOperand(0);
208 if (Idx >= NumElements) {
209 InVec = N->getOperand(1);
212 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
213 DAG.getIntPtrConstant(Idx)));
215 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
218 void DAGTypeLegalizer::SplitRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo,
220 MVT::ValueType LoVT, HiVT;
221 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
222 unsigned LoNumElts = MVT::getVectorNumElements(LoVT);
223 SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
224 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
226 SmallVector<SDOperand, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
227 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
230 void DAGTypeLegalizer::SplitRes_CONCAT_VECTORS(SDNode *N,
231 SDOperand &Lo, SDOperand &Hi) {
232 // FIXME: Handle non-power-of-two vectors?
233 unsigned NumSubvectors = N->getNumOperands() / 2;
234 if (NumSubvectors == 1) {
235 Lo = N->getOperand(0);
236 Hi = N->getOperand(1);
240 MVT::ValueType LoVT, HiVT;
241 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
243 SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
244 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
246 SmallVector<SDOperand, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
247 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
250 void DAGTypeLegalizer::SplitRes_BIT_CONVERT(SDNode *N,
251 SDOperand &Lo, SDOperand &Hi) {
252 // We know the result is a vector. The input may be either a vector or a
254 MVT::ValueType LoVT, HiVT;
255 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
257 SDOperand InOp = N->getOperand(0);
258 MVT::ValueType InVT = InOp.getValueType();
260 // Handle some special cases efficiently.
261 switch (getTypeAction(InVT)) {
263 assert(false && "Unknown type action!");
270 // A scalar to vector conversion, where the scalar needs expansion.
271 // If the vector is being split in two then we can just convert the
274 GetExpandedOp(InOp, Lo, Hi);
275 if (TLI.isBigEndian())
277 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
278 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
283 // If the input is a vector that needs to be split, convert each split
284 // piece of the input now.
285 GetSplitOp(InOp, Lo, Hi);
286 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
287 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
291 // In the general case, convert the input to an integer and split it by hand.
292 MVT::ValueType LoIntVT = MVT::getIntegerType(MVT::getSizeInBits(LoVT));
293 MVT::ValueType HiIntVT = MVT::getIntegerType(MVT::getSizeInBits(HiVT));
294 if (TLI.isBigEndian())
295 std::swap(LoIntVT, HiIntVT);
297 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
299 if (TLI.isBigEndian())
301 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
302 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
305 void DAGTypeLegalizer::SplitRes_BinOp(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
306 SDOperand LHSLo, LHSHi;
307 GetSplitOp(N->getOperand(0), LHSLo, LHSHi);
308 SDOperand RHSLo, RHSHi;
309 GetSplitOp(N->getOperand(1), RHSLo, RHSHi);
311 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
312 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
315 void DAGTypeLegalizer::SplitRes_UnOp(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
316 // Get the dest types. This doesn't always match input types, e.g. int_to_fp.
317 MVT::ValueType LoVT, HiVT;
318 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
320 GetSplitOp(N->getOperand(0), Lo, Hi);
321 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
322 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
325 void DAGTypeLegalizer::SplitRes_FPOWI(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
326 GetSplitOp(N->getOperand(0), Lo, Hi);
327 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
328 Hi = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Hi, N->getOperand(1));
332 void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDOperand &Lo, SDOperand &Hi){
333 SDOperand LL, LH, RL, RH;
334 GetSplitOp(N->getOperand(1), LL, LH);
335 GetSplitOp(N->getOperand(2), RL, RH);
337 SDOperand Cond = N->getOperand(0);
338 Lo = DAG.getNode(ISD::SELECT, LL.getValueType(), Cond, LL, RL);
339 Hi = DAG.getNode(ISD::SELECT, LH.getValueType(), Cond, LH, RH);
343 //===----------------------------------------------------------------------===//
344 // Operand Vector Splitting
345 //===----------------------------------------------------------------------===//
347 /// SplitOperand - This method is called when the specified operand of the
348 /// specified node is found to need vector splitting. At this point, all of the
349 /// result types of the node are known to be legal, but other operands of the
350 /// node may need legalization as well as the specified one.
351 bool DAGTypeLegalizer::SplitOperand(SDNode *N, unsigned OpNo) {
352 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
356 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
357 TargetLowering::Custom)
358 Res = TLI.LowerOperation(SDOperand(N, 0), DAG);
362 switch (N->getOpcode()) {
365 cerr << "SplitOperand Op #" << OpNo << ": ";
366 N->dump(&DAG); cerr << "\n";
368 assert(0 && "Do not know how to split this operator's operand!");
370 case ISD::STORE: Res = SplitOp_STORE(cast<StoreSDNode>(N), OpNo); break;
371 case ISD::RET: Res = SplitOp_RET(N, OpNo); break;
373 case ISD::BIT_CONVERT: Res = SplitOp_BIT_CONVERT(N); break;
375 case ISD::EXTRACT_VECTOR_ELT: Res = SplitOp_EXTRACT_VECTOR_ELT(N); break;
376 case ISD::EXTRACT_SUBVECTOR: Res = SplitOp_EXTRACT_SUBVECTOR(N); break;
377 case ISD::VECTOR_SHUFFLE: Res = SplitOp_VECTOR_SHUFFLE(N, OpNo); break;
381 // If the result is null, the sub-method took care of registering results etc.
382 if (!Res.Val) return false;
384 // If the result is N, the sub-method updated N in place. Check to see if any
385 // operands are new, and if so, mark them.
387 // Mark N as new and remark N and its operands. This allows us to correctly
388 // revisit N if it needs another step of promotion and allows us to visit
389 // any new operands to N.
394 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
395 "Invalid operand expansion");
397 ReplaceValueWith(SDOperand(N, 0), Res);
401 SDOperand DAGTypeLegalizer::SplitOp_STORE(StoreSDNode *N, unsigned OpNo) {
402 // FIXME: Add support for indexed stores.
403 assert(OpNo == 1 && "Can only split the stored value");
405 SDOperand Ch = N->getChain();
406 SDOperand Ptr = N->getBasePtr();
407 int SVOffset = N->getSrcValueOffset();
408 unsigned Alignment = N->getAlignment();
409 bool isVol = N->isVolatile();
411 GetSplitOp(N->getOperand(1), Lo, Hi);
413 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
415 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, isVol, Alignment);
417 // Increment the pointer to the other half.
418 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
419 DAG.getIntPtrConstant(IncrementSize));
421 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
422 isVol, MinAlign(Alignment, IncrementSize));
423 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
426 SDOperand DAGTypeLegalizer::SplitOp_RET(SDNode *N, unsigned OpNo) {
427 assert(N->getNumOperands() == 3 &&"Can only handle ret of one vector so far");
428 // FIXME: Returns of gcc generic vectors larger than a legal vector
429 // type should be returned by reference!
431 GetSplitOp(N->getOperand(1), Lo, Hi);
433 SDOperand Chain = N->getOperand(0); // The chain.
434 SDOperand Sign = N->getOperand(2); // Signness
436 return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Sign, Hi, Sign);
439 SDOperand DAGTypeLegalizer::SplitOp_BIT_CONVERT(SDNode *N) {
440 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
441 // end up being split all the way down to individual components. Convert the
442 // split pieces into integers and reassemble.
444 GetSplitOp(N->getOperand(0), Lo, Hi);
445 Lo = BitConvertToInteger(Lo);
446 Hi = BitConvertToInteger(Hi);
448 if (TLI.isBigEndian())
451 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
452 JoinIntegers(Lo, Hi));
455 SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_VECTOR_ELT(SDNode *N) {
456 SDOperand Vec = N->getOperand(0);
457 SDOperand Idx = N->getOperand(1);
458 MVT::ValueType VecVT = Vec.getValueType();
460 if (isa<ConstantSDNode>(Idx)) {
461 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
462 assert(IdxVal < MVT::getVectorNumElements(VecVT) &&
463 "Invalid vector index!");
466 GetSplitOp(Vec, Lo, Hi);
468 uint64_t LoElts = MVT::getVectorNumElements(Lo.getValueType());
471 return DAG.UpdateNodeOperands(SDOperand(N, 0), Lo, Idx);
473 return DAG.UpdateNodeOperands(SDOperand(N, 0), Hi,
474 DAG.getConstant(IdxVal - LoElts,
475 Idx.getValueType()));
478 // Store the vector to the stack and load back the required element.
479 SDOperand StackPtr = DAG.CreateStackTemporary(VecVT);
480 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
482 // Add the offset to the index.
483 MVT::ValueType EltVT = MVT::getVectorElementType(VecVT);
484 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; // FIXME: should be ABI size.
485 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
486 DAG.getConstant(EltSize, Idx.getValueType()));
488 if (MVT::getSizeInBits(Idx.getValueType()) >
489 MVT::getSizeInBits(TLI.getPointerTy()))
490 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
492 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
494 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
495 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
498 SDOperand DAGTypeLegalizer::SplitOp_EXTRACT_SUBVECTOR(SDNode *N) {
499 // We know that the extracted result type is legal. For now, assume the index
501 MVT::ValueType SubVT = N->getValueType(0);
502 SDOperand Idx = N->getOperand(1);
504 GetSplitOp(N->getOperand(0), Lo, Hi);
506 uint64_t LoElts = MVT::getVectorNumElements(Lo.getValueType());
507 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
509 if (IdxVal < LoElts) {
510 assert(IdxVal + MVT::getVectorNumElements(SubVT) <= LoElts &&
511 "Extracted subvector crosses vector split!");
512 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
514 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
515 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
519 SDOperand DAGTypeLegalizer::SplitOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
520 assert(OpNo == 2 && "Shuffle source type differs from result type?");
521 SDOperand Mask = N->getOperand(2);
522 unsigned MaskLength = MVT::getVectorNumElements(Mask.getValueType());
523 unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
524 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
526 // Look for a legal vector type to place the mask values in.
527 // Note that there may not be *any* legal vector-of-integer
528 // type for which the element type is legal!
529 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
530 EltVT <= MVT::LAST_INTEGER_VALUETYPE;
531 // Integer values types are consecutively numbered. Exploit this.
532 EltVT = MVT::SimpleValueType(EltVT + 1)) {
534 // Is the element type big enough to hold the values?
535 if (MVT::getSizeInBits(EltVT) < MinimumBitWidth)
539 // Is the vector type legal?
540 MVT::ValueType VecVT = MVT::getVectorType(EltVT, MaskLength);
541 if (!isTypeLegal(VecVT))
545 // If the element type is not legal, find a larger legal type to use for
546 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
547 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
548 // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
549 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
550 // Integer values types are consecutively numbered. Exploit this.
551 OpVT = MVT::SimpleValueType(OpVT + 1)) {
552 if (!isTypeLegal(OpVT))
555 // Success! Rebuild the vector using the legal types.
556 SmallVector<SDOperand, 16> Ops(MaskLength);
557 for (unsigned i = 0; i < MaskLength; ++i) {
559 cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
560 Ops[i] = DAG.getConstant(Idx, OpVT);
562 return DAG.UpdateNodeOperands(SDOperand(N,0),
563 N->getOperand(0), N->getOperand(1),
564 DAG.getNode(ISD::BUILD_VECTOR,
565 VecVT, &Ops[0], Ops.size()));
568 // Continuing is pointless - failure is certain.
571 assert(false && "Failed to find an appropriate mask type!");
572 return SDOperand(N, 0);