1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::LegalizeVectors method.
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/Target/TargetLowering.h"
35 class VectorLegalizer {
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
40 /// For nodes that are of legal width, and that have more than one use, this
41 /// map indicates what regularized operand to use. This allows us to avoid
42 /// legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
45 /// \brief Adds a node to the translation cache.
46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
50 LegalizedNodes.insert(std::make_pair(To, To));
53 /// \brief Legalizes the given node.
54 SDValue LegalizeOp(SDValue Op);
56 /// \brief Assuming the node is legal, "legalize" the results.
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
59 /// \brief Implements unrolling a VSETCC.
60 SDValue UnrollVSETCC(SDValue Op);
62 /// \brief Implement expand-based legalization of vector operations.
64 /// This is just a high-level routine to dispatch to specific code paths for
65 /// operations to legalize them.
66 SDValue Expand(SDValue Op);
68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
71 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
72 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
76 SDValue ExpandSEXTINREG(SDValue Op);
78 /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
80 /// Shuffles the low lanes of the operand into place and bitcasts to the proper
81 /// type. The contents of the bits in the extended part of each element are
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
85 /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
87 /// Shuffles the low lanes of the operand into place, bitcasts to the proper
88 /// type, then shifts left and arithmetic shifts right to introduce a sign
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
92 /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
94 /// Shuffles the low lanes of the operand into place and blends zeros into
95 /// the remaining lanes, finally bitcasting to the proper type.
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
98 /// \brief Expand bswap of vectors into a shuffle if legal.
99 SDValue ExpandBSWAP(SDValue Op);
101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
102 /// supported by the target.
103 SDValue ExpandVSELECT(SDValue Op);
104 SDValue ExpandSELECT(SDValue Op);
105 SDValue ExpandLoad(SDValue Op);
106 SDValue ExpandStore(SDValue Op);
107 SDValue ExpandFNEG(SDValue Op);
109 /// \brief Implements vector promotion.
111 /// This is essentially just bitcasting the operands to a different type and
112 /// bitcasting the result back to the original type.
113 SDValue Promote(SDValue Op);
115 /// \brief Implements [SU]INT_TO_FP vector promotion.
117 /// This is a [zs]ext of the input operand to the next size up.
118 SDValue PromoteINT_TO_FP(SDValue Op);
120 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
122 /// It is promoted to the next size up integer type. The result is then
123 /// truncated back to the original type.
124 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
127 /// \brief Begin legalizer the vector operations in the DAG.
129 VectorLegalizer(SelectionDAG& dag) :
130 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
133 bool VectorLegalizer::Run() {
134 // Before we start legalizing vector nodes, check if there are any vectors.
135 bool HasVectors = false;
136 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
137 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
138 // Check if the values of the nodes contain vectors. We don't need to check
139 // the operands because we are going to check their values at some point.
140 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
142 HasVectors |= J->isVector();
144 // If we found a vector node we can start the legalization.
149 // If this basic block has no vectors then no need to legalize vectors.
153 // The legalize process is inherently a bottom-up recursive process (users
154 // legalize their uses before themselves). Given infinite stack space, we
155 // could just start legalizing on the root and traverse the whole graph. In
156 // practice however, this causes us to run out of stack space on large basic
157 // blocks. To avoid this problem, compute an ordering of the nodes where each
158 // node is only legalized after all of its operands are legalized.
159 DAG.AssignTopologicalOrder();
160 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
161 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
162 LegalizeOp(SDValue(I, 0));
164 // Finally, it's possible the root changed. Get the new root.
165 SDValue OldRoot = DAG.getRoot();
166 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
167 DAG.setRoot(LegalizedNodes[OldRoot]);
169 LegalizedNodes.clear();
171 // Remove dead nodes now.
172 DAG.RemoveDeadNodes();
177 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
178 // Generic legalization: just pass the operand through.
179 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
180 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
181 return Result.getValue(Op.getResNo());
184 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
185 // Note that LegalizeOp may be reentered even from single-use nodes, which
186 // means that we always must cache transformed nodes.
187 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
188 if (I != LegalizedNodes.end()) return I->second;
190 SDNode* Node = Op.getNode();
192 // Legalize the operands
193 SmallVector<SDValue, 8> Ops;
194 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
195 Ops.push_back(LegalizeOp(Node->getOperand(i)));
197 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
199 if (Op.getOpcode() == ISD::LOAD) {
200 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
201 ISD::LoadExtType ExtType = LD->getExtensionType();
202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
203 switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getMemoryVT())) {
204 default: llvm_unreachable("This action is not supported yet!");
205 case TargetLowering::Legal:
206 return TranslateLegalizeResults(Op, Result);
207 case TargetLowering::Custom:
208 if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
210 if (Lowered->getNumValues() != Op->getNumValues()) {
211 // This expanded to something other than the load. Assume the
212 // lowering code took care of any chain values, and just handle the
214 assert(Result.getValue(1).use_empty() &&
215 "There are still live users of the old chain!");
216 return LegalizeOp(Lowered);
218 return TranslateLegalizeResults(Op, Lowered);
221 case TargetLowering::Expand:
223 return LegalizeOp(ExpandLoad(Op));
225 } else if (Op.getOpcode() == ISD::STORE) {
226 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
227 EVT StVT = ST->getMemoryVT();
228 MVT ValVT = ST->getValue().getSimpleValueType();
229 if (StVT.isVector() && ST->isTruncatingStore())
230 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
231 default: llvm_unreachable("This action is not supported yet!");
232 case TargetLowering::Legal:
233 return TranslateLegalizeResults(Op, Result);
234 case TargetLowering::Custom:
236 return TranslateLegalizeResults(Op, TLI.LowerOperation(Result, DAG));
237 case TargetLowering::Expand:
239 return LegalizeOp(ExpandStore(Op));
243 bool HasVectorValue = false;
244 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
247 HasVectorValue |= J->isVector();
249 return TranslateLegalizeResults(Op, Result);
252 switch (Op.getOpcode()) {
254 return TranslateLegalizeResults(Op, Result);
278 case ISD::CTLZ_ZERO_UNDEF:
279 case ISD::CTTZ_ZERO_UNDEF:
285 case ISD::ZERO_EXTEND:
286 case ISD::ANY_EXTEND:
288 case ISD::SIGN_EXTEND:
289 case ISD::FP_TO_SINT:
290 case ISD::FP_TO_UINT:
307 case ISD::FNEARBYINT:
313 case ISD::SIGN_EXTEND_INREG:
314 case ISD::ANY_EXTEND_VECTOR_INREG:
315 case ISD::SIGN_EXTEND_VECTOR_INREG:
316 case ISD::ZERO_EXTEND_VECTOR_INREG:
317 QueryType = Node->getValueType(0);
319 case ISD::FP_ROUND_INREG:
320 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
322 case ISD::SINT_TO_FP:
323 case ISD::UINT_TO_FP:
324 QueryType = Node->getOperand(0).getValueType();
328 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
329 case TargetLowering::Promote:
330 Result = Promote(Op);
333 case TargetLowering::Legal:
335 case TargetLowering::Custom: {
336 SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
337 if (Tmp1.getNode()) {
343 case TargetLowering::Expand:
347 // Make sure that the generated code is itself legal.
349 Result = LegalizeOp(Result);
353 // Note that LegalizeOp may be reentered even from single-use nodes, which
354 // means that we always must cache transformed nodes.
355 AddLegalizedOperand(Op, Result);
359 SDValue VectorLegalizer::Promote(SDValue Op) {
360 // For a few operations there is a specific concept for promotion based on
361 // the operand's type.
362 switch (Op.getOpcode()) {
363 case ISD::SINT_TO_FP:
364 case ISD::UINT_TO_FP:
365 // "Promote" the operation by extending the operand.
366 return PromoteINT_TO_FP(Op);
367 case ISD::FP_TO_UINT:
368 case ISD::FP_TO_SINT:
369 // Promote the operation by extending the operand.
370 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
373 // There are currently two cases of vector promotion:
374 // 1) Bitcasting a vector of integers to a different type to a vector of the
375 // same overall length. For example, x86 promotes ISD::AND on v2i32 to v1i64.
376 // 2) Extending a vector of floats to a vector of the same number oflarger
377 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
378 MVT VT = Op.getSimpleValueType();
379 assert(Op.getNode()->getNumValues() == 1 &&
380 "Can't promote a vector with multiple results!");
381 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
383 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
385 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
386 if (Op.getOperand(j).getValueType().isVector())
389 .getVectorElementType()
391 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
393 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
395 Operands[j] = Op.getOperand(j);
398 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands);
399 if (VT.isFloatingPoint() ||
400 (VT.isVector() && VT.getVectorElementType().isFloatingPoint()))
401 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0));
403 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
406 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
407 // INT_TO_FP operations may require the input operand be promoted even
408 // when the type is otherwise legal.
409 EVT VT = Op.getOperand(0).getValueType();
410 assert(Op.getNode()->getNumValues() == 1 &&
411 "Can't promote a vector with multiple results!");
413 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
414 // by widening the vector w/ the same element width and twice the number
415 // of elements. We want the other way around, the same number of elements,
416 // each twice the width.
418 // Increase the bitwidth of the element to the next pow-of-two
419 // (which is greater than 8 bits).
421 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
422 assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
424 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
426 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
428 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
429 if (Op.getOperand(j).getValueType().isVector())
430 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
432 Operands[j] = Op.getOperand(j);
435 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
438 // For FP_TO_INT we promote the result type to a vector type with wider
439 // elements and then truncate the result. This is different from the default
440 // PromoteVector which uses bitcast to promote thus assumning that the
441 // promoted vector type has the same overall size.
442 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
443 assert(Op.getNode()->getNumValues() == 1 &&
444 "Can't promote a vector with multiple results!");
445 EVT VT = Op.getValueType();
450 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
451 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
452 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
453 NewOpc = ISD::FP_TO_SINT;
456 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
457 NewOpc = ISD::FP_TO_UINT;
463 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
464 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
468 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
470 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
471 SDValue Chain = LD->getChain();
472 SDValue BasePTR = LD->getBasePtr();
473 EVT SrcVT = LD->getMemoryVT();
474 ISD::LoadExtType ExtType = LD->getExtensionType();
476 SmallVector<SDValue, 8> Vals;
477 SmallVector<SDValue, 8> LoadChains;
478 unsigned NumElem = SrcVT.getVectorNumElements();
480 EVT SrcEltVT = SrcVT.getScalarType();
481 EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
483 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
484 // When elements in a vector is not byte-addressable, we cannot directly
485 // load each element by advancing pointer, which could only address bytes.
486 // Instead, we load all significant words, mask bits off, and concatenate
487 // them to form each element. Finally, they are extended to destination
488 // scalar type to build the destination vector.
489 EVT WideVT = TLI.getPointerTy();
491 assert(WideVT.isRound() &&
492 "Could not handle the sophisticated case when the widest integer is"
494 assert(WideVT.bitsGE(SrcEltVT) &&
495 "Type is not legalized?");
497 unsigned WideBytes = WideVT.getStoreSize();
499 unsigned RemainingBytes = SrcVT.getStoreSize();
500 SmallVector<SDValue, 8> LoadVals;
502 while (RemainingBytes > 0) {
504 unsigned LoadBytes = WideBytes;
506 if (RemainingBytes >= LoadBytes) {
507 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
508 LD->getPointerInfo().getWithOffset(Offset),
509 LD->isVolatile(), LD->isNonTemporal(),
510 LD->isInvariant(), LD->getAlignment(),
514 while (RemainingBytes < LoadBytes) {
515 LoadBytes >>= 1; // Reduce the load size by half.
516 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
518 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
519 LD->getPointerInfo().getWithOffset(Offset),
520 LoadVT, LD->isVolatile(),
521 LD->isNonTemporal(), LD->isInvariant(),
522 LD->getAlignment(), LD->getAAInfo());
525 RemainingBytes -= LoadBytes;
527 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
528 DAG.getConstant(LoadBytes, BasePTR.getValueType()));
530 LoadVals.push_back(ScalarLoad.getValue(0));
531 LoadChains.push_back(ScalarLoad.getValue(1));
534 // Extract bits, pack and extend/trunc them into destination type.
535 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
536 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, WideVT);
538 unsigned BitOffset = 0;
539 unsigned WideIdx = 0;
540 unsigned WideBits = WideVT.getSizeInBits();
542 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
543 SDValue Lo, Hi, ShAmt;
545 if (BitOffset < WideBits) {
546 ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
547 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
548 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
551 BitOffset += SrcEltBits;
552 if (BitOffset >= WideBits) {
556 ShAmt = DAG.getConstant(SrcEltBits - Offset,
557 TLI.getShiftAmountTy(WideVT));
558 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
559 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
564 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
567 default: llvm_unreachable("Unknown extended-load op!");
569 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
572 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
575 ShAmt = DAG.getConstant(WideBits - SrcEltBits,
576 TLI.getShiftAmountTy(WideVT));
577 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
578 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
579 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
585 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
587 for (unsigned Idx=0; Idx<NumElem; Idx++) {
588 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
589 Op.getNode()->getValueType(0).getScalarType(),
590 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
591 SrcVT.getScalarType(),
592 LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(),
593 LD->getAlignment(), LD->getAAInfo());
595 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
596 DAG.getConstant(Stride, BasePTR.getValueType()));
598 Vals.push_back(ScalarLoad.getValue(0));
599 LoadChains.push_back(ScalarLoad.getValue(1));
603 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
604 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
605 Op.getNode()->getValueType(0), Vals);
607 AddLegalizedOperand(Op.getValue(0), Value);
608 AddLegalizedOperand(Op.getValue(1), NewChain);
610 return (Op.getResNo() ? NewChain : Value);
613 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
615 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
616 SDValue Chain = ST->getChain();
617 SDValue BasePTR = ST->getBasePtr();
618 SDValue Value = ST->getValue();
619 EVT StVT = ST->getMemoryVT();
621 unsigned Alignment = ST->getAlignment();
622 bool isVolatile = ST->isVolatile();
623 bool isNonTemporal = ST->isNonTemporal();
624 AAMDNodes AAInfo = ST->getAAInfo();
626 unsigned NumElem = StVT.getVectorNumElements();
627 // The type of the data we want to save
628 EVT RegVT = Value.getValueType();
629 EVT RegSclVT = RegVT.getScalarType();
630 // The type of data as saved in memory.
631 EVT MemSclVT = StVT.getScalarType();
633 // Cast floats into integers
634 unsigned ScalarSize = MemSclVT.getSizeInBits();
636 // Round odd types to the next pow of two.
637 if (!isPowerOf2_32(ScalarSize))
638 ScalarSize = NextPowerOf2(ScalarSize);
640 // Store Stride in bytes
641 unsigned Stride = ScalarSize/8;
642 // Extract each of the elements from the original vector
643 // and save them into memory individually.
644 SmallVector<SDValue, 8> Stores;
645 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
646 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
647 RegSclVT, Value, DAG.getConstant(Idx, TLI.getVectorIdxTy()));
649 // This scalar TruncStore may be illegal, but we legalize it later.
650 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
651 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
652 isVolatile, isNonTemporal, Alignment, AAInfo);
654 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
655 DAG.getConstant(Stride, BasePTR.getValueType()));
657 Stores.push_back(Store);
659 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
660 AddLegalizedOperand(Op, TF);
664 SDValue VectorLegalizer::Expand(SDValue Op) {
665 switch (Op->getOpcode()) {
666 case ISD::SIGN_EXTEND_INREG:
667 return ExpandSEXTINREG(Op);
668 case ISD::ANY_EXTEND_VECTOR_INREG:
669 return ExpandANY_EXTEND_VECTOR_INREG(Op);
670 case ISD::SIGN_EXTEND_VECTOR_INREG:
671 return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
672 case ISD::ZERO_EXTEND_VECTOR_INREG:
673 return ExpandZERO_EXTEND_VECTOR_INREG(Op);
675 return ExpandBSWAP(Op);
677 return ExpandVSELECT(Op);
679 return ExpandSELECT(Op);
680 case ISD::UINT_TO_FP:
681 return ExpandUINT_TO_FLOAT(Op);
683 return ExpandFNEG(Op);
685 return UnrollVSETCC(Op);
687 return DAG.UnrollVectorOp(Op.getNode());
691 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
692 // Lower a select instruction where the condition is a scalar and the
693 // operands are vectors. Lower this select to VSELECT and implement it
694 // using XOR AND OR. The selector bit is broadcasted.
695 EVT VT = Op.getValueType();
698 SDValue Mask = Op.getOperand(0);
699 SDValue Op1 = Op.getOperand(1);
700 SDValue Op2 = Op.getOperand(2);
702 assert(VT.isVector() && !Mask.getValueType().isVector()
703 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
705 unsigned NumElem = VT.getVectorNumElements();
707 // If we can't even use the basic vector operations of
708 // AND,OR,XOR, we will have to scalarize the op.
709 // Notice that the operation may be 'promoted' which means that it is
710 // 'bitcasted' to another type which is handled.
711 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
712 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
713 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
714 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
715 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
716 return DAG.UnrollVectorOp(Op.getNode());
718 // Generate a mask operand.
719 EVT MaskTy = VT.changeVectorElementTypeToInteger();
721 // What is the size of each element in the vector mask.
722 EVT BitTy = MaskTy.getScalarType();
724 Mask = DAG.getSelect(DL, BitTy, Mask,
725 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy),
726 DAG.getConstant(0, BitTy));
728 // Broadcast the mask so that the entire vector is all-one or all zero.
729 SmallVector<SDValue, 8> Ops(NumElem, Mask);
730 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
732 // Bitcast the operands to be the same type as the mask.
733 // This is needed when we select between FP types because
734 // the mask is a vector of integers.
735 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
736 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
738 SDValue AllOnes = DAG.getConstant(
739 APInt::getAllOnesValue(BitTy.getSizeInBits()), MaskTy);
740 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
742 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
743 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
744 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
745 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
748 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
749 EVT VT = Op.getValueType();
751 // Make sure that the SRA and SHL instructions are available.
752 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
753 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
754 return DAG.UnrollVectorOp(Op.getNode());
757 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
759 unsigned BW = VT.getScalarType().getSizeInBits();
760 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
761 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT);
763 Op = Op.getOperand(0);
764 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
765 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
768 // Generically expand a vector anyext in register to a shuffle of the relevant
769 // lanes into the appropriate locations, with other lanes left undef.
770 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
772 EVT VT = Op.getValueType();
773 int NumElements = VT.getVectorNumElements();
774 SDValue Src = Op.getOperand(0);
775 EVT SrcVT = Src.getValueType();
776 int NumSrcElements = SrcVT.getVectorNumElements();
778 // Build a base mask of undef shuffles.
779 SmallVector<int, 16> ShuffleMask;
780 ShuffleMask.resize(NumSrcElements, -1);
782 // Place the extended lanes into the correct locations.
783 int ExtLaneScale = NumSrcElements / NumElements;
784 int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0;
785 for (int i = 0; i < NumElements; ++i)
786 ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
789 ISD::BITCAST, DL, VT,
790 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
793 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
795 EVT VT = Op.getValueType();
796 SDValue Src = Op.getOperand(0);
797 EVT SrcVT = Src.getValueType();
799 // First build an any-extend node which can be legalized above when we
800 // recurse through it.
801 Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
803 // Now we need sign extend. Do this by shifting the elements. Even if these
804 // aren't legal operations, they have a better chance of being legalized
805 // without full scalarization than the sign extension does.
806 unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
807 unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
808 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, VT);
809 return DAG.getNode(ISD::SRA, DL, VT,
810 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
814 // Generically expand a vector zext in register to a shuffle of the relevant
815 // lanes into the appropriate locations, a blend of zero into the high bits,
816 // and a bitcast to the wider element type.
817 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
819 EVT VT = Op.getValueType();
820 int NumElements = VT.getVectorNumElements();
821 SDValue Src = Op.getOperand(0);
822 EVT SrcVT = Src.getValueType();
823 int NumSrcElements = SrcVT.getVectorNumElements();
825 // Build up a zero vector to blend into this one.
826 EVT SrcScalarVT = SrcVT.getScalarType();
827 SDValue ScalarZero = DAG.getTargetConstant(0, SrcScalarVT);
828 SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero);
829 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands);
831 // Shuffle the incoming lanes into the correct position, and pull all other
832 // lanes from the zero vector.
833 SmallVector<int, 16> ShuffleMask;
834 ShuffleMask.reserve(NumSrcElements);
835 for (int i = 0; i < NumSrcElements; ++i)
836 ShuffleMask.push_back(i);
838 int ExtLaneScale = NumSrcElements / NumElements;
839 int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0;
840 for (int i = 0; i < NumElements; ++i)
841 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
843 return DAG.getNode(ISD::BITCAST, DL, VT,
844 DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
847 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
848 EVT VT = Op.getValueType();
850 // Generate a byte wise shuffle mask for the BSWAP.
851 SmallVector<int, 16> ShuffleMask;
852 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
853 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
854 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
855 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
857 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
859 // Only emit a shuffle if the mask is legal.
860 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
861 return DAG.UnrollVectorOp(Op.getNode());
864 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
865 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
867 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
870 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
871 // Implement VSELECT in terms of XOR, AND, OR
872 // on platforms which do not support blend natively.
875 SDValue Mask = Op.getOperand(0);
876 SDValue Op1 = Op.getOperand(1);
877 SDValue Op2 = Op.getOperand(2);
879 EVT VT = Mask.getValueType();
881 // If we can't even use the basic vector operations of
882 // AND,OR,XOR, we will have to scalarize the op.
883 // Notice that the operation may be 'promoted' which means that it is
884 // 'bitcasted' to another type which is handled.
885 // This operation also isn't safe with AND, OR, XOR when the boolean
886 // type is 0/1 as we need an all ones vector constant to mask with.
887 // FIXME: Sign extend 1 to all ones if thats legal on the target.
888 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
889 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
890 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
891 TLI.getBooleanContents(Op1.getValueType()) !=
892 TargetLowering::ZeroOrNegativeOneBooleanContent)
893 return DAG.UnrollVectorOp(Op.getNode());
895 // If the mask and the type are different sizes, unroll the vector op. This
896 // can occur when getSetCCResultType returns something that is different in
897 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
898 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
899 return DAG.UnrollVectorOp(Op.getNode());
901 // Bitcast the operands to be the same type as the mask.
902 // This is needed when we select between FP types because
903 // the mask is a vector of integers.
904 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
905 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
907 SDValue AllOnes = DAG.getConstant(
908 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT);
909 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
911 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
912 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
913 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
914 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
917 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
918 EVT VT = Op.getOperand(0).getValueType();
921 // Make sure that the SINT_TO_FP and SRL instructions are available.
922 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
923 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
924 return DAG.UnrollVectorOp(Op.getNode());
926 EVT SVT = VT.getScalarType();
927 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
928 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
930 unsigned BW = SVT.getSizeInBits();
931 SDValue HalfWord = DAG.getConstant(BW/2, VT);
933 // Constants to clear the upper part of the word.
934 // Notice that we can also use SHL+SHR, but using a constant is slightly
936 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
937 SDValue HalfWordMask = DAG.getConstant(HWMask, VT);
939 // Two to the power of half-word-size.
940 SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType());
942 // Clear upper part of LO, lower HI
943 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
944 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
946 // Convert hi and lo to floats
947 // Convert the hi part back to the upper values
948 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
949 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
950 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
952 // Add the two halves
953 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
957 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
958 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
959 SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType());
960 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
961 Zero, Op.getOperand(0));
963 return DAG.UnrollVectorOp(Op.getNode());
966 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
967 EVT VT = Op.getValueType();
968 unsigned NumElems = VT.getVectorNumElements();
969 EVT EltVT = VT.getVectorElementType();
970 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
971 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
973 SmallVector<SDValue, 8> Ops(NumElems);
974 for (unsigned i = 0; i < NumElems; ++i) {
975 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
976 DAG.getConstant(i, TLI.getVectorIdxTy()));
977 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
978 DAG.getConstant(i, TLI.getVectorIdxTy()));
979 Ops[i] = DAG.getNode(ISD::SETCC, dl,
980 TLI.getSetCCResultType(*DAG.getContext(), TmpEltVT),
981 LHSElem, RHSElem, CC);
982 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
983 DAG.getConstant(APInt::getAllOnesValue
984 (EltVT.getSizeInBits()), EltVT),
985 DAG.getConstant(0, EltVT));
987 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
992 bool SelectionDAG::LegalizeVectors() {
993 return VectorLegalizer(*this).Run();