1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::LegalizeVectors method.
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/Target/TargetLowering.h"
35 class VectorLegalizer {
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
40 /// For nodes that are of legal width, and that have more than one use, this
41 /// map indicates what regularized operand to use. This allows us to avoid
42 /// legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
45 /// \brief Adds a node to the translation cache.
46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
50 LegalizedNodes.insert(std::make_pair(To, To));
53 /// \brief Legalizes the given node.
54 SDValue LegalizeOp(SDValue Op);
56 /// \brief Assuming the node is legal, "legalize" the results.
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
59 /// \brief Implements unrolling a VSETCC.
60 SDValue UnrollVSETCC(SDValue Op);
62 /// \brief Implement expand-based legalization of vector operations.
64 /// This is just a high-level routine to dispatch to specific code paths for
65 /// operations to legalize them.
66 SDValue Expand(SDValue Op);
68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
71 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
72 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
76 SDValue ExpandSEXTINREG(SDValue Op);
78 /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
80 /// Shuffles the low lanes of the operand into place and bitcasts to the proper
81 /// type. The contents of the bits in the extended part of each element are
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
85 /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
87 /// Shuffles the low lanes of the operand into place, bitcasts to the proper
88 /// type, then shifts left and arithmetic shifts right to introduce a sign
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
92 /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
94 /// Shuffles the low lanes of the operand into place and blends zeros into
95 /// the remaining lanes, finally bitcasting to the proper type.
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
98 /// \brief Expand bswap of vectors into a shuffle if legal.
99 SDValue ExpandBSWAP(SDValue Op);
101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
102 /// supported by the target.
103 SDValue ExpandVSELECT(SDValue Op);
104 SDValue ExpandSELECT(SDValue Op);
105 SDValue ExpandLoad(SDValue Op);
106 SDValue ExpandStore(SDValue Op);
107 SDValue ExpandFNEG(SDValue Op);
109 /// \brief Implements vector promotion.
111 /// This is essentially just bitcasting the operands to a different type and
112 /// bitcasting the result back to the original type.
113 SDValue Promote(SDValue Op);
115 /// \brief Implements [SU]INT_TO_FP vector promotion.
117 /// This is a [zs]ext of the input operand to the next size up.
118 SDValue PromoteINT_TO_FP(SDValue Op);
120 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
122 /// It is promoted to the next size up integer type. The result is then
123 /// truncated back to the original type.
124 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
127 /// \brief Begin legalizer the vector operations in the DAG.
129 VectorLegalizer(SelectionDAG& dag) :
130 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
133 bool VectorLegalizer::Run() {
134 // Before we start legalizing vector nodes, check if there are any vectors.
135 bool HasVectors = false;
136 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
137 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
138 // Check if the values of the nodes contain vectors. We don't need to check
139 // the operands because we are going to check their values at some point.
140 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
142 HasVectors |= J->isVector();
144 // If we found a vector node we can start the legalization.
149 // If this basic block has no vectors then no need to legalize vectors.
153 // The legalize process is inherently a bottom-up recursive process (users
154 // legalize their uses before themselves). Given infinite stack space, we
155 // could just start legalizing on the root and traverse the whole graph. In
156 // practice however, this causes us to run out of stack space on large basic
157 // blocks. To avoid this problem, compute an ordering of the nodes where each
158 // node is only legalized after all of its operands are legalized.
159 DAG.AssignTopologicalOrder();
160 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
161 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
162 LegalizeOp(SDValue(I, 0));
164 // Finally, it's possible the root changed. Get the new root.
165 SDValue OldRoot = DAG.getRoot();
166 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
167 DAG.setRoot(LegalizedNodes[OldRoot]);
169 LegalizedNodes.clear();
171 // Remove dead nodes now.
172 DAG.RemoveDeadNodes();
177 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
178 // Generic legalization: just pass the operand through.
179 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
180 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
181 return Result.getValue(Op.getResNo());
184 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
185 // Note that LegalizeOp may be reentered even from single-use nodes, which
186 // means that we always must cache transformed nodes.
187 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
188 if (I != LegalizedNodes.end()) return I->second;
190 SDNode* Node = Op.getNode();
192 // Legalize the operands
193 SmallVector<SDValue, 8> Ops;
194 for (const SDValue &Op : Node->op_values())
195 Ops.push_back(LegalizeOp(Op));
197 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
199 bool HasVectorValue = false;
200 if (Op.getOpcode() == ISD::LOAD) {
201 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
202 ISD::LoadExtType ExtType = LD->getExtensionType();
203 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
204 switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
205 LD->getMemoryVT())) {
206 default: llvm_unreachable("This action is not supported yet!");
207 case TargetLowering::Legal:
208 return TranslateLegalizeResults(Op, Result);
209 case TargetLowering::Custom:
210 if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
211 if (Lowered == Result)
212 return TranslateLegalizeResults(Op, Lowered);
214 if (Lowered->getNumValues() != Op->getNumValues()) {
215 // This expanded to something other than the load. Assume the
216 // lowering code took care of any chain values, and just handle the
218 assert(Result.getValue(1).use_empty() &&
219 "There are still live users of the old chain!");
220 return LegalizeOp(Lowered);
222 return TranslateLegalizeResults(Op, Lowered);
225 case TargetLowering::Expand:
227 return LegalizeOp(ExpandLoad(Op));
229 } else if (Op.getOpcode() == ISD::STORE) {
230 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
231 EVT StVT = ST->getMemoryVT();
232 MVT ValVT = ST->getValue().getSimpleValueType();
233 if (StVT.isVector() && ST->isTruncatingStore())
234 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
235 default: llvm_unreachable("This action is not supported yet!");
236 case TargetLowering::Legal:
237 return TranslateLegalizeResults(Op, Result);
238 case TargetLowering::Custom: {
239 SDValue Lowered = TLI.LowerOperation(Result, DAG);
240 Changed = Lowered != Result;
241 return TranslateLegalizeResults(Op, Lowered);
243 case TargetLowering::Expand:
245 return LegalizeOp(ExpandStore(Op));
247 } else if (Op.getOpcode() == ISD::MSCATTER)
248 HasVectorValue = true;
250 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
253 HasVectorValue |= J->isVector();
255 return TranslateLegalizeResults(Op, Result);
258 switch (Op.getOpcode()) {
260 return TranslateLegalizeResults(Op, Result);
284 case ISD::CTLZ_ZERO_UNDEF:
285 case ISD::CTTZ_ZERO_UNDEF:
291 case ISD::ZERO_EXTEND:
292 case ISD::ANY_EXTEND:
294 case ISD::SIGN_EXTEND:
295 case ISD::FP_TO_SINT:
296 case ISD::FP_TO_UINT:
315 case ISD::FNEARBYINT:
321 case ISD::SIGN_EXTEND_INREG:
322 case ISD::ANY_EXTEND_VECTOR_INREG:
323 case ISD::SIGN_EXTEND_VECTOR_INREG:
324 case ISD::ZERO_EXTEND_VECTOR_INREG:
329 QueryType = Node->getValueType(0);
331 case ISD::FP_ROUND_INREG:
332 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
334 case ISD::SINT_TO_FP:
335 case ISD::UINT_TO_FP:
336 QueryType = Node->getOperand(0).getValueType();
339 QueryType = cast<MaskedScatterSDNode>(Node)->getValue().getValueType();
343 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
344 case TargetLowering::Promote:
345 Result = Promote(Op);
348 case TargetLowering::Legal:
350 case TargetLowering::Custom: {
351 SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
352 if (Tmp1.getNode()) {
358 case TargetLowering::Expand:
362 // Make sure that the generated code is itself legal.
364 Result = LegalizeOp(Result);
368 // Note that LegalizeOp may be reentered even from single-use nodes, which
369 // means that we always must cache transformed nodes.
370 AddLegalizedOperand(Op, Result);
374 SDValue VectorLegalizer::Promote(SDValue Op) {
375 // For a few operations there is a specific concept for promotion based on
376 // the operand's type.
377 switch (Op.getOpcode()) {
378 case ISD::SINT_TO_FP:
379 case ISD::UINT_TO_FP:
380 // "Promote" the operation by extending the operand.
381 return PromoteINT_TO_FP(Op);
382 case ISD::FP_TO_UINT:
383 case ISD::FP_TO_SINT:
384 // Promote the operation by extending the operand.
385 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
388 // There are currently two cases of vector promotion:
389 // 1) Bitcasting a vector of integers to a different type to a vector of the
390 // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
391 // 2) Extending a vector of floats to a vector of the same number of larger
392 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
393 MVT VT = Op.getSimpleValueType();
394 assert(Op.getNode()->getNumValues() == 1 &&
395 "Can't promote a vector with multiple results!");
396 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
398 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
400 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
401 if (Op.getOperand(j).getValueType().isVector())
404 .getVectorElementType()
405 .isFloatingPoint() &&
406 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
407 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
409 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
411 Operands[j] = Op.getOperand(j);
414 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands);
415 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
416 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
417 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
418 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
420 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
423 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
424 // INT_TO_FP operations may require the input operand be promoted even
425 // when the type is otherwise legal.
426 EVT VT = Op.getOperand(0).getValueType();
427 assert(Op.getNode()->getNumValues() == 1 &&
428 "Can't promote a vector with multiple results!");
430 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
431 // by widening the vector w/ the same element width and twice the number
432 // of elements. We want the other way around, the same number of elements,
433 // each twice the width.
435 // Increase the bitwidth of the element to the next pow-of-two
436 // (which is greater than 8 bits).
438 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
439 assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
441 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
443 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
445 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
446 if (Op.getOperand(j).getValueType().isVector())
447 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
449 Operands[j] = Op.getOperand(j);
452 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
455 // For FP_TO_INT we promote the result type to a vector type with wider
456 // elements and then truncate the result. This is different from the default
457 // PromoteVector which uses bitcast to promote thus assumning that the
458 // promoted vector type has the same overall size.
459 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
460 assert(Op.getNode()->getNumValues() == 1 &&
461 "Can't promote a vector with multiple results!");
462 EVT VT = Op.getValueType();
467 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
468 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
469 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
470 NewOpc = ISD::FP_TO_SINT;
473 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
474 NewOpc = ISD::FP_TO_UINT;
480 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
481 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
485 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
487 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
488 SDValue Chain = LD->getChain();
489 SDValue BasePTR = LD->getBasePtr();
490 EVT SrcVT = LD->getMemoryVT();
491 ISD::LoadExtType ExtType = LD->getExtensionType();
493 SmallVector<SDValue, 8> Vals;
494 SmallVector<SDValue, 8> LoadChains;
495 unsigned NumElem = SrcVT.getVectorNumElements();
497 EVT SrcEltVT = SrcVT.getScalarType();
498 EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
500 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
501 // When elements in a vector is not byte-addressable, we cannot directly
502 // load each element by advancing pointer, which could only address bytes.
503 // Instead, we load all significant words, mask bits off, and concatenate
504 // them to form each element. Finally, they are extended to destination
505 // scalar type to build the destination vector.
506 EVT WideVT = TLI.getPointerTy(DAG.getDataLayout());
508 assert(WideVT.isRound() &&
509 "Could not handle the sophisticated case when the widest integer is"
511 assert(WideVT.bitsGE(SrcEltVT) &&
512 "Type is not legalized?");
514 unsigned WideBytes = WideVT.getStoreSize();
516 unsigned RemainingBytes = SrcVT.getStoreSize();
517 SmallVector<SDValue, 8> LoadVals;
519 while (RemainingBytes > 0) {
521 unsigned LoadBytes = WideBytes;
523 if (RemainingBytes >= LoadBytes) {
524 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
525 LD->getPointerInfo().getWithOffset(Offset),
526 LD->isVolatile(), LD->isNonTemporal(),
528 MinAlign(LD->getAlignment(), Offset),
532 while (RemainingBytes < LoadBytes) {
533 LoadBytes >>= 1; // Reduce the load size by half.
534 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
536 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
537 LD->getPointerInfo().getWithOffset(Offset),
538 LoadVT, LD->isVolatile(),
539 LD->isNonTemporal(), LD->isInvariant(),
540 MinAlign(LD->getAlignment(), Offset),
544 RemainingBytes -= LoadBytes;
546 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
547 DAG.getConstant(LoadBytes, dl,
548 BasePTR.getValueType()));
550 LoadVals.push_back(ScalarLoad.getValue(0));
551 LoadChains.push_back(ScalarLoad.getValue(1));
554 // Extract bits, pack and extend/trunc them into destination type.
555 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
556 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT);
558 unsigned BitOffset = 0;
559 unsigned WideIdx = 0;
560 unsigned WideBits = WideVT.getSizeInBits();
562 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
563 SDValue Lo, Hi, ShAmt;
565 if (BitOffset < WideBits) {
566 ShAmt = DAG.getConstant(
567 BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
568 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
569 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
572 BitOffset += SrcEltBits;
573 if (BitOffset >= WideBits) {
575 BitOffset -= WideBits;
577 ShAmt = DAG.getConstant(
578 SrcEltBits - BitOffset, dl,
579 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
580 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
581 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
586 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
589 default: llvm_unreachable("Unknown extended-load op!");
591 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
594 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
598 DAG.getConstant(WideBits - SrcEltBits, dl,
599 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
600 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
601 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
602 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
608 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
610 for (unsigned Idx=0; Idx<NumElem; Idx++) {
611 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
612 Op.getNode()->getValueType(0).getScalarType(),
613 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
614 SrcVT.getScalarType(),
615 LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(),
616 MinAlign(LD->getAlignment(), Idx * Stride), LD->getAAInfo());
618 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
619 DAG.getConstant(Stride, dl, BasePTR.getValueType()));
621 Vals.push_back(ScalarLoad.getValue(0));
622 LoadChains.push_back(ScalarLoad.getValue(1));
626 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
627 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
628 Op.getNode()->getValueType(0), Vals);
630 AddLegalizedOperand(Op.getValue(0), Value);
631 AddLegalizedOperand(Op.getValue(1), NewChain);
633 return (Op.getResNo() ? NewChain : Value);
636 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
638 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
639 SDValue Chain = ST->getChain();
640 SDValue BasePTR = ST->getBasePtr();
641 SDValue Value = ST->getValue();
642 EVT StVT = ST->getMemoryVT();
644 unsigned Alignment = ST->getAlignment();
645 bool isVolatile = ST->isVolatile();
646 bool isNonTemporal = ST->isNonTemporal();
647 AAMDNodes AAInfo = ST->getAAInfo();
649 unsigned NumElem = StVT.getVectorNumElements();
650 // The type of the data we want to save
651 EVT RegVT = Value.getValueType();
652 EVT RegSclVT = RegVT.getScalarType();
653 // The type of data as saved in memory.
654 EVT MemSclVT = StVT.getScalarType();
656 // Cast floats into integers
657 unsigned ScalarSize = MemSclVT.getSizeInBits();
659 // Round odd types to the next pow of two.
660 if (!isPowerOf2_32(ScalarSize))
661 ScalarSize = NextPowerOf2(ScalarSize);
663 // Store Stride in bytes
664 unsigned Stride = ScalarSize/8;
665 // Extract each of the elements from the original vector
666 // and save them into memory individually.
667 SmallVector<SDValue, 8> Stores;
668 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
669 SDValue Ex = DAG.getNode(
670 ISD::EXTRACT_VECTOR_ELT, dl, RegSclVT, Value,
671 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
673 // This scalar TruncStore may be illegal, but we legalize it later.
674 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
675 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
676 isVolatile, isNonTemporal, MinAlign(Alignment, Idx*Stride),
679 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
680 DAG.getConstant(Stride, dl, BasePTR.getValueType()));
682 Stores.push_back(Store);
684 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
685 AddLegalizedOperand(Op, TF);
689 SDValue VectorLegalizer::Expand(SDValue Op) {
690 switch (Op->getOpcode()) {
691 case ISD::SIGN_EXTEND_INREG:
692 return ExpandSEXTINREG(Op);
693 case ISD::ANY_EXTEND_VECTOR_INREG:
694 return ExpandANY_EXTEND_VECTOR_INREG(Op);
695 case ISD::SIGN_EXTEND_VECTOR_INREG:
696 return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
697 case ISD::ZERO_EXTEND_VECTOR_INREG:
698 return ExpandZERO_EXTEND_VECTOR_INREG(Op);
700 return ExpandBSWAP(Op);
702 return ExpandVSELECT(Op);
704 return ExpandSELECT(Op);
705 case ISD::UINT_TO_FP:
706 return ExpandUINT_TO_FLOAT(Op);
708 return ExpandFNEG(Op);
710 return UnrollVSETCC(Op);
712 return DAG.UnrollVectorOp(Op.getNode());
716 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
717 // Lower a select instruction where the condition is a scalar and the
718 // operands are vectors. Lower this select to VSELECT and implement it
719 // using XOR AND OR. The selector bit is broadcasted.
720 EVT VT = Op.getValueType();
723 SDValue Mask = Op.getOperand(0);
724 SDValue Op1 = Op.getOperand(1);
725 SDValue Op2 = Op.getOperand(2);
727 assert(VT.isVector() && !Mask.getValueType().isVector()
728 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
730 unsigned NumElem = VT.getVectorNumElements();
732 // If we can't even use the basic vector operations of
733 // AND,OR,XOR, we will have to scalarize the op.
734 // Notice that the operation may be 'promoted' which means that it is
735 // 'bitcasted' to another type which is handled.
736 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
737 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
738 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
739 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
740 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
741 return DAG.UnrollVectorOp(Op.getNode());
743 // Generate a mask operand.
744 EVT MaskTy = VT.changeVectorElementTypeToInteger();
746 // What is the size of each element in the vector mask.
747 EVT BitTy = MaskTy.getScalarType();
749 Mask = DAG.getSelect(DL, BitTy, Mask,
750 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
752 DAG.getConstant(0, DL, BitTy));
754 // Broadcast the mask so that the entire vector is all-one or all zero.
755 SmallVector<SDValue, 8> Ops(NumElem, Mask);
756 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
758 // Bitcast the operands to be the same type as the mask.
759 // This is needed when we select between FP types because
760 // the mask is a vector of integers.
761 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
762 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
764 SDValue AllOnes = DAG.getConstant(
765 APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy);
766 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
768 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
769 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
770 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
771 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
774 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
775 EVT VT = Op.getValueType();
777 // Make sure that the SRA and SHL instructions are available.
778 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
779 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
780 return DAG.UnrollVectorOp(Op.getNode());
783 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
785 unsigned BW = VT.getScalarType().getSizeInBits();
786 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
787 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
789 Op = Op.getOperand(0);
790 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
791 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
794 // Generically expand a vector anyext in register to a shuffle of the relevant
795 // lanes into the appropriate locations, with other lanes left undef.
796 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
798 EVT VT = Op.getValueType();
799 int NumElements = VT.getVectorNumElements();
800 SDValue Src = Op.getOperand(0);
801 EVT SrcVT = Src.getValueType();
802 int NumSrcElements = SrcVT.getVectorNumElements();
804 // Build a base mask of undef shuffles.
805 SmallVector<int, 16> ShuffleMask;
806 ShuffleMask.resize(NumSrcElements, -1);
808 // Place the extended lanes into the correct locations.
809 int ExtLaneScale = NumSrcElements / NumElements;
810 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
811 for (int i = 0; i < NumElements; ++i)
812 ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
815 ISD::BITCAST, DL, VT,
816 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
819 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
821 EVT VT = Op.getValueType();
822 SDValue Src = Op.getOperand(0);
823 EVT SrcVT = Src.getValueType();
825 // First build an any-extend node which can be legalized above when we
826 // recurse through it.
827 Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
829 // Now we need sign extend. Do this by shifting the elements. Even if these
830 // aren't legal operations, they have a better chance of being legalized
831 // without full scalarization than the sign extension does.
832 unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
833 unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
834 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
835 return DAG.getNode(ISD::SRA, DL, VT,
836 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
840 // Generically expand a vector zext in register to a shuffle of the relevant
841 // lanes into the appropriate locations, a blend of zero into the high bits,
842 // and a bitcast to the wider element type.
843 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
845 EVT VT = Op.getValueType();
846 int NumElements = VT.getVectorNumElements();
847 SDValue Src = Op.getOperand(0);
848 EVT SrcVT = Src.getValueType();
849 int NumSrcElements = SrcVT.getVectorNumElements();
851 // Build up a zero vector to blend into this one.
852 EVT SrcScalarVT = SrcVT.getScalarType();
853 SDValue ScalarZero = DAG.getTargetConstant(0, DL, SrcScalarVT);
854 SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero);
855 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands);
857 // Shuffle the incoming lanes into the correct position, and pull all other
858 // lanes from the zero vector.
859 SmallVector<int, 16> ShuffleMask;
860 ShuffleMask.reserve(NumSrcElements);
861 for (int i = 0; i < NumSrcElements; ++i)
862 ShuffleMask.push_back(i);
864 int ExtLaneScale = NumSrcElements / NumElements;
865 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
866 for (int i = 0; i < NumElements; ++i)
867 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
869 return DAG.getNode(ISD::BITCAST, DL, VT,
870 DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
873 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
874 EVT VT = Op.getValueType();
876 // Generate a byte wise shuffle mask for the BSWAP.
877 SmallVector<int, 16> ShuffleMask;
878 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
879 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
880 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
881 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
883 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
885 // Only emit a shuffle if the mask is legal.
886 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
887 return DAG.UnrollVectorOp(Op.getNode());
890 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
891 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
893 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
896 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
897 // Implement VSELECT in terms of XOR, AND, OR
898 // on platforms which do not support blend natively.
901 SDValue Mask = Op.getOperand(0);
902 SDValue Op1 = Op.getOperand(1);
903 SDValue Op2 = Op.getOperand(2);
905 EVT VT = Mask.getValueType();
907 // If we can't even use the basic vector operations of
908 // AND,OR,XOR, we will have to scalarize the op.
909 // Notice that the operation may be 'promoted' which means that it is
910 // 'bitcasted' to another type which is handled.
911 // This operation also isn't safe with AND, OR, XOR when the boolean
912 // type is 0/1 as we need an all ones vector constant to mask with.
913 // FIXME: Sign extend 1 to all ones if thats legal on the target.
914 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
915 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
916 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
917 TLI.getBooleanContents(Op1.getValueType()) !=
918 TargetLowering::ZeroOrNegativeOneBooleanContent)
919 return DAG.UnrollVectorOp(Op.getNode());
921 // If the mask and the type are different sizes, unroll the vector op. This
922 // can occur when getSetCCResultType returns something that is different in
923 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
924 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
925 return DAG.UnrollVectorOp(Op.getNode());
927 // Bitcast the operands to be the same type as the mask.
928 // This is needed when we select between FP types because
929 // the mask is a vector of integers.
930 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
931 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
933 SDValue AllOnes = DAG.getConstant(
934 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), DL, VT);
935 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
937 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
938 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
939 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
940 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
943 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
944 EVT VT = Op.getOperand(0).getValueType();
947 // Make sure that the SINT_TO_FP and SRL instructions are available.
948 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
949 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
950 return DAG.UnrollVectorOp(Op.getNode());
952 EVT SVT = VT.getScalarType();
953 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
954 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
956 unsigned BW = SVT.getSizeInBits();
957 SDValue HalfWord = DAG.getConstant(BW/2, DL, VT);
959 // Constants to clear the upper part of the word.
960 // Notice that we can also use SHL+SHR, but using a constant is slightly
962 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
963 SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
965 // Two to the power of half-word-size.
966 SDValue TWOHW = DAG.getConstantFP(1 << (BW/2), DL, Op.getValueType());
968 // Clear upper part of LO, lower HI
969 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
970 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
972 // Convert hi and lo to floats
973 // Convert the hi part back to the upper values
974 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
975 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
976 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
978 // Add the two halves
979 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
983 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
984 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
986 SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
987 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
988 Zero, Op.getOperand(0));
990 return DAG.UnrollVectorOp(Op.getNode());
993 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
994 EVT VT = Op.getValueType();
995 unsigned NumElems = VT.getVectorNumElements();
996 EVT EltVT = VT.getVectorElementType();
997 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
998 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
1000 SmallVector<SDValue, 8> Ops(NumElems);
1001 for (unsigned i = 0; i < NumElems; ++i) {
1002 SDValue LHSElem = DAG.getNode(
1003 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
1004 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1005 SDValue RHSElem = DAG.getNode(
1006 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
1007 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1008 Ops[i] = DAG.getNode(ISD::SETCC, dl,
1009 TLI.getSetCCResultType(DAG.getDataLayout(),
1010 *DAG.getContext(), TmpEltVT),
1011 LHSElem, RHSElem, CC);
1012 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
1013 DAG.getConstant(APInt::getAllOnesValue
1014 (EltVT.getSizeInBits()), dl, EltVT),
1015 DAG.getConstant(0, dl, EltVT));
1017 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1022 bool SelectionDAG::LegalizeVectors() {
1023 return VectorLegalizer(*this).Run();