1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::LegalizeVectors method.
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/Target/TargetLowering.h"
35 class VectorLegalizer {
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
40 /// For nodes that are of legal width, and that have more than one use, this
41 /// map indicates what regularized operand to use. This allows us to avoid
42 /// legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
45 /// \brief Adds a node to the translation cache.
46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
50 LegalizedNodes.insert(std::make_pair(To, To));
53 /// \brief Legalizes the given node.
54 SDValue LegalizeOp(SDValue Op);
56 /// \brief Assuming the node is legal, "legalize" the results.
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
59 /// \brief Implements unrolling a VSETCC.
60 SDValue UnrollVSETCC(SDValue Op);
62 /// \brief Implement expand-based legalization of vector operations.
64 /// This is just a high-level routine to dispatch to specific code paths for
65 /// operations to legalize them.
66 SDValue Expand(SDValue Op);
68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
71 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
72 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
76 SDValue ExpandSEXTINREG(SDValue Op);
78 /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
80 /// Shuffles the low lanes of the operand into place and bitcasts to the proper
81 /// type. The contents of the bits in the extended part of each element are
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
85 /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
87 /// Shuffles the low lanes of the operand into place, bitcasts to the proper
88 /// type, then shifts left and arithmetic shifts right to introduce a sign
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
92 /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
94 /// Shuffles the low lanes of the operand into place and blends zeros into
95 /// the remaining lanes, finally bitcasting to the proper type.
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
98 /// \brief Expand bswap of vectors into a shuffle if legal.
99 SDValue ExpandBSWAP(SDValue Op);
101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
102 /// supported by the target.
103 SDValue ExpandVSELECT(SDValue Op);
104 SDValue ExpandSELECT(SDValue Op);
105 SDValue ExpandLoad(SDValue Op);
106 SDValue ExpandStore(SDValue Op);
107 SDValue ExpandFNEG(SDValue Op);
109 /// \brief Implements vector promotion.
111 /// This is essentially just bitcasting the operands to a different type and
112 /// bitcasting the result back to the original type.
113 SDValue Promote(SDValue Op);
115 /// \brief Implements [SU]INT_TO_FP vector promotion.
117 /// This is a [zs]ext of the input operand to the next size up.
118 SDValue PromoteINT_TO_FP(SDValue Op);
120 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
122 /// It is promoted to the next size up integer type. The result is then
123 /// truncated back to the original type.
124 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
127 /// \brief Begin legalizer the vector operations in the DAG.
129 VectorLegalizer(SelectionDAG& dag) :
130 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
133 bool VectorLegalizer::Run() {
134 // Before we start legalizing vector nodes, check if there are any vectors.
135 bool HasVectors = false;
136 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
137 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
138 // Check if the values of the nodes contain vectors. We don't need to check
139 // the operands because we are going to check their values at some point.
140 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
142 HasVectors |= J->isVector();
144 // If we found a vector node we can start the legalization.
149 // If this basic block has no vectors then no need to legalize vectors.
153 // The legalize process is inherently a bottom-up recursive process (users
154 // legalize their uses before themselves). Given infinite stack space, we
155 // could just start legalizing on the root and traverse the whole graph. In
156 // practice however, this causes us to run out of stack space on large basic
157 // blocks. To avoid this problem, compute an ordering of the nodes where each
158 // node is only legalized after all of its operands are legalized.
159 DAG.AssignTopologicalOrder();
160 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
161 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
162 LegalizeOp(SDValue(I, 0));
164 // Finally, it's possible the root changed. Get the new root.
165 SDValue OldRoot = DAG.getRoot();
166 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
167 DAG.setRoot(LegalizedNodes[OldRoot]);
169 LegalizedNodes.clear();
171 // Remove dead nodes now.
172 DAG.RemoveDeadNodes();
177 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
178 // Generic legalization: just pass the operand through.
179 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
180 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
181 return Result.getValue(Op.getResNo());
184 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
185 // Note that LegalizeOp may be reentered even from single-use nodes, which
186 // means that we always must cache transformed nodes.
187 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
188 if (I != LegalizedNodes.end()) return I->second;
190 SDNode* Node = Op.getNode();
192 // Legalize the operands
193 SmallVector<SDValue, 8> Ops;
194 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
195 Ops.push_back(LegalizeOp(Node->getOperand(i)));
197 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
199 if (Op.getOpcode() == ISD::LOAD) {
200 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
201 ISD::LoadExtType ExtType = LD->getExtensionType();
202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
203 switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
204 LD->getMemoryVT())) {
205 default: llvm_unreachable("This action is not supported yet!");
206 case TargetLowering::Legal:
207 return TranslateLegalizeResults(Op, Result);
208 case TargetLowering::Custom:
209 if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
210 if (Lowered == Result)
211 return TranslateLegalizeResults(Op, Lowered);
213 if (Lowered->getNumValues() != Op->getNumValues()) {
214 // This expanded to something other than the load. Assume the
215 // lowering code took care of any chain values, and just handle the
217 assert(Result.getValue(1).use_empty() &&
218 "There are still live users of the old chain!");
219 return LegalizeOp(Lowered);
221 return TranslateLegalizeResults(Op, Lowered);
224 case TargetLowering::Expand:
226 return LegalizeOp(ExpandLoad(Op));
228 } else if (Op.getOpcode() == ISD::STORE) {
229 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
230 EVT StVT = ST->getMemoryVT();
231 MVT ValVT = ST->getValue().getSimpleValueType();
232 if (StVT.isVector() && ST->isTruncatingStore())
233 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
234 default: llvm_unreachable("This action is not supported yet!");
235 case TargetLowering::Legal:
236 return TranslateLegalizeResults(Op, Result);
237 case TargetLowering::Custom: {
238 SDValue Lowered = TLI.LowerOperation(Result, DAG);
239 Changed = Lowered != Result;
240 return TranslateLegalizeResults(Op, Lowered);
242 case TargetLowering::Expand:
244 return LegalizeOp(ExpandStore(Op));
248 bool HasVectorValue = false;
249 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
252 HasVectorValue |= J->isVector();
254 return TranslateLegalizeResults(Op, Result);
257 switch (Op.getOpcode()) {
259 return TranslateLegalizeResults(Op, Result);
283 case ISD::CTLZ_ZERO_UNDEF:
284 case ISD::CTTZ_ZERO_UNDEF:
290 case ISD::ZERO_EXTEND:
291 case ISD::ANY_EXTEND:
293 case ISD::SIGN_EXTEND:
294 case ISD::FP_TO_SINT:
295 case ISD::FP_TO_UINT:
314 case ISD::FNEARBYINT:
320 case ISD::SIGN_EXTEND_INREG:
321 case ISD::ANY_EXTEND_VECTOR_INREG:
322 case ISD::SIGN_EXTEND_VECTOR_INREG:
323 case ISD::ZERO_EXTEND_VECTOR_INREG:
324 QueryType = Node->getValueType(0);
326 case ISD::FP_ROUND_INREG:
327 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
329 case ISD::SINT_TO_FP:
330 case ISD::UINT_TO_FP:
331 QueryType = Node->getOperand(0).getValueType();
335 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
336 case TargetLowering::Promote:
337 Result = Promote(Op);
340 case TargetLowering::Legal:
342 case TargetLowering::Custom: {
343 SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
344 if (Tmp1.getNode()) {
350 case TargetLowering::Expand:
354 // Make sure that the generated code is itself legal.
356 Result = LegalizeOp(Result);
360 // Note that LegalizeOp may be reentered even from single-use nodes, which
361 // means that we always must cache transformed nodes.
362 AddLegalizedOperand(Op, Result);
366 SDValue VectorLegalizer::Promote(SDValue Op) {
367 // For a few operations there is a specific concept for promotion based on
368 // the operand's type.
369 switch (Op.getOpcode()) {
370 case ISD::SINT_TO_FP:
371 case ISD::UINT_TO_FP:
372 // "Promote" the operation by extending the operand.
373 return PromoteINT_TO_FP(Op);
374 case ISD::FP_TO_UINT:
375 case ISD::FP_TO_SINT:
376 // Promote the operation by extending the operand.
377 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
380 // There are currently two cases of vector promotion:
381 // 1) Bitcasting a vector of integers to a different type to a vector of the
382 // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
383 // 2) Extending a vector of floats to a vector of the same number of larger
384 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
385 MVT VT = Op.getSimpleValueType();
386 assert(Op.getNode()->getNumValues() == 1 &&
387 "Can't promote a vector with multiple results!");
388 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
390 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
392 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
393 if (Op.getOperand(j).getValueType().isVector())
396 .getVectorElementType()
397 .isFloatingPoint() &&
398 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
399 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
401 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
403 Operands[j] = Op.getOperand(j);
406 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands);
407 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
408 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
409 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
410 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
412 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
415 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
416 // INT_TO_FP operations may require the input operand be promoted even
417 // when the type is otherwise legal.
418 EVT VT = Op.getOperand(0).getValueType();
419 assert(Op.getNode()->getNumValues() == 1 &&
420 "Can't promote a vector with multiple results!");
422 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
423 // by widening the vector w/ the same element width and twice the number
424 // of elements. We want the other way around, the same number of elements,
425 // each twice the width.
427 // Increase the bitwidth of the element to the next pow-of-two
428 // (which is greater than 8 bits).
430 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
431 assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
433 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
435 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
437 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
438 if (Op.getOperand(j).getValueType().isVector())
439 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
441 Operands[j] = Op.getOperand(j);
444 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
447 // For FP_TO_INT we promote the result type to a vector type with wider
448 // elements and then truncate the result. This is different from the default
449 // PromoteVector which uses bitcast to promote thus assumning that the
450 // promoted vector type has the same overall size.
451 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
452 assert(Op.getNode()->getNumValues() == 1 &&
453 "Can't promote a vector with multiple results!");
454 EVT VT = Op.getValueType();
459 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
460 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
461 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
462 NewOpc = ISD::FP_TO_SINT;
465 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
466 NewOpc = ISD::FP_TO_UINT;
472 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
473 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
477 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
479 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
480 SDValue Chain = LD->getChain();
481 SDValue BasePTR = LD->getBasePtr();
482 EVT SrcVT = LD->getMemoryVT();
483 ISD::LoadExtType ExtType = LD->getExtensionType();
485 SmallVector<SDValue, 8> Vals;
486 SmallVector<SDValue, 8> LoadChains;
487 unsigned NumElem = SrcVT.getVectorNumElements();
489 EVT SrcEltVT = SrcVT.getScalarType();
490 EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
492 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
493 // When elements in a vector is not byte-addressable, we cannot directly
494 // load each element by advancing pointer, which could only address bytes.
495 // Instead, we load all significant words, mask bits off, and concatenate
496 // them to form each element. Finally, they are extended to destination
497 // scalar type to build the destination vector.
498 EVT WideVT = TLI.getPointerTy();
500 assert(WideVT.isRound() &&
501 "Could not handle the sophisticated case when the widest integer is"
503 assert(WideVT.bitsGE(SrcEltVT) &&
504 "Type is not legalized?");
506 unsigned WideBytes = WideVT.getStoreSize();
508 unsigned RemainingBytes = SrcVT.getStoreSize();
509 SmallVector<SDValue, 8> LoadVals;
511 while (RemainingBytes > 0) {
513 unsigned LoadBytes = WideBytes;
515 if (RemainingBytes >= LoadBytes) {
516 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
517 LD->getPointerInfo().getWithOffset(Offset),
518 LD->isVolatile(), LD->isNonTemporal(),
520 MinAlign(LD->getAlignment(), Offset),
524 while (RemainingBytes < LoadBytes) {
525 LoadBytes >>= 1; // Reduce the load size by half.
526 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
528 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
529 LD->getPointerInfo().getWithOffset(Offset),
530 LoadVT, LD->isVolatile(),
531 LD->isNonTemporal(), LD->isInvariant(),
532 MinAlign(LD->getAlignment(), Offset),
536 RemainingBytes -= LoadBytes;
538 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
539 DAG.getConstant(LoadBytes, dl,
540 BasePTR.getValueType()));
542 LoadVals.push_back(ScalarLoad.getValue(0));
543 LoadChains.push_back(ScalarLoad.getValue(1));
546 // Extract bits, pack and extend/trunc them into destination type.
547 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
548 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT);
550 unsigned BitOffset = 0;
551 unsigned WideIdx = 0;
552 unsigned WideBits = WideVT.getSizeInBits();
554 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
555 SDValue Lo, Hi, ShAmt;
557 if (BitOffset < WideBits) {
558 ShAmt = DAG.getConstant(BitOffset, dl, TLI.getShiftAmountTy(WideVT));
559 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
560 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
563 BitOffset += SrcEltBits;
564 if (BitOffset >= WideBits) {
566 BitOffset -= WideBits;
568 ShAmt = DAG.getConstant(SrcEltBits - BitOffset, dl,
569 TLI.getShiftAmountTy(WideVT));
570 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
571 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
576 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
579 default: llvm_unreachable("Unknown extended-load op!");
581 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
584 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
587 ShAmt = DAG.getConstant(WideBits - SrcEltBits, dl,
588 TLI.getShiftAmountTy(WideVT));
589 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
590 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
591 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
597 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
599 for (unsigned Idx=0; Idx<NumElem; Idx++) {
600 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
601 Op.getNode()->getValueType(0).getScalarType(),
602 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
603 SrcVT.getScalarType(),
604 LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(),
605 MinAlign(LD->getAlignment(), Idx * Stride), LD->getAAInfo());
607 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
608 DAG.getConstant(Stride, dl, BasePTR.getValueType()));
610 Vals.push_back(ScalarLoad.getValue(0));
611 LoadChains.push_back(ScalarLoad.getValue(1));
615 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
616 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
617 Op.getNode()->getValueType(0), Vals);
619 AddLegalizedOperand(Op.getValue(0), Value);
620 AddLegalizedOperand(Op.getValue(1), NewChain);
622 return (Op.getResNo() ? NewChain : Value);
625 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
627 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
628 SDValue Chain = ST->getChain();
629 SDValue BasePTR = ST->getBasePtr();
630 SDValue Value = ST->getValue();
631 EVT StVT = ST->getMemoryVT();
633 unsigned Alignment = ST->getAlignment();
634 bool isVolatile = ST->isVolatile();
635 bool isNonTemporal = ST->isNonTemporal();
636 AAMDNodes AAInfo = ST->getAAInfo();
638 unsigned NumElem = StVT.getVectorNumElements();
639 // The type of the data we want to save
640 EVT RegVT = Value.getValueType();
641 EVT RegSclVT = RegVT.getScalarType();
642 // The type of data as saved in memory.
643 EVT MemSclVT = StVT.getScalarType();
645 // Cast floats into integers
646 unsigned ScalarSize = MemSclVT.getSizeInBits();
648 // Round odd types to the next pow of two.
649 if (!isPowerOf2_32(ScalarSize))
650 ScalarSize = NextPowerOf2(ScalarSize);
652 // Store Stride in bytes
653 unsigned Stride = ScalarSize/8;
654 // Extract each of the elements from the original vector
655 // and save them into memory individually.
656 SmallVector<SDValue, 8> Stores;
657 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
658 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
659 RegSclVT, Value, DAG.getConstant(Idx, dl, TLI.getVectorIdxTy()));
661 // This scalar TruncStore may be illegal, but we legalize it later.
662 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
663 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
664 isVolatile, isNonTemporal, MinAlign(Alignment, Idx*Stride),
667 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
668 DAG.getConstant(Stride, dl, BasePTR.getValueType()));
670 Stores.push_back(Store);
672 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
673 AddLegalizedOperand(Op, TF);
677 SDValue VectorLegalizer::Expand(SDValue Op) {
678 switch (Op->getOpcode()) {
679 case ISD::SIGN_EXTEND_INREG:
680 return ExpandSEXTINREG(Op);
681 case ISD::ANY_EXTEND_VECTOR_INREG:
682 return ExpandANY_EXTEND_VECTOR_INREG(Op);
683 case ISD::SIGN_EXTEND_VECTOR_INREG:
684 return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
685 case ISD::ZERO_EXTEND_VECTOR_INREG:
686 return ExpandZERO_EXTEND_VECTOR_INREG(Op);
688 return ExpandBSWAP(Op);
690 return ExpandVSELECT(Op);
692 return ExpandSELECT(Op);
693 case ISD::UINT_TO_FP:
694 return ExpandUINT_TO_FLOAT(Op);
696 return ExpandFNEG(Op);
698 return UnrollVSETCC(Op);
700 return DAG.UnrollVectorOp(Op.getNode());
704 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
705 // Lower a select instruction where the condition is a scalar and the
706 // operands are vectors. Lower this select to VSELECT and implement it
707 // using XOR AND OR. The selector bit is broadcasted.
708 EVT VT = Op.getValueType();
711 SDValue Mask = Op.getOperand(0);
712 SDValue Op1 = Op.getOperand(1);
713 SDValue Op2 = Op.getOperand(2);
715 assert(VT.isVector() && !Mask.getValueType().isVector()
716 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
718 unsigned NumElem = VT.getVectorNumElements();
720 // If we can't even use the basic vector operations of
721 // AND,OR,XOR, we will have to scalarize the op.
722 // Notice that the operation may be 'promoted' which means that it is
723 // 'bitcasted' to another type which is handled.
724 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
725 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
726 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
727 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
728 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
729 return DAG.UnrollVectorOp(Op.getNode());
731 // Generate a mask operand.
732 EVT MaskTy = VT.changeVectorElementTypeToInteger();
734 // What is the size of each element in the vector mask.
735 EVT BitTy = MaskTy.getScalarType();
737 Mask = DAG.getSelect(DL, BitTy, Mask,
738 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
740 DAG.getConstant(0, DL, BitTy));
742 // Broadcast the mask so that the entire vector is all-one or all zero.
743 SmallVector<SDValue, 8> Ops(NumElem, Mask);
744 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
746 // Bitcast the operands to be the same type as the mask.
747 // This is needed when we select between FP types because
748 // the mask is a vector of integers.
749 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
750 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
752 SDValue AllOnes = DAG.getConstant(
753 APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy);
754 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
756 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
757 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
758 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
759 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
762 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
763 EVT VT = Op.getValueType();
765 // Make sure that the SRA and SHL instructions are available.
766 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
767 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
768 return DAG.UnrollVectorOp(Op.getNode());
771 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
773 unsigned BW = VT.getScalarType().getSizeInBits();
774 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
775 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
777 Op = Op.getOperand(0);
778 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
779 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
782 // Generically expand a vector anyext in register to a shuffle of the relevant
783 // lanes into the appropriate locations, with other lanes left undef.
784 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
786 EVT VT = Op.getValueType();
787 int NumElements = VT.getVectorNumElements();
788 SDValue Src = Op.getOperand(0);
789 EVT SrcVT = Src.getValueType();
790 int NumSrcElements = SrcVT.getVectorNumElements();
792 // Build a base mask of undef shuffles.
793 SmallVector<int, 16> ShuffleMask;
794 ShuffleMask.resize(NumSrcElements, -1);
796 // Place the extended lanes into the correct locations.
797 int ExtLaneScale = NumSrcElements / NumElements;
798 int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0;
799 for (int i = 0; i < NumElements; ++i)
800 ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
803 ISD::BITCAST, DL, VT,
804 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
807 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
809 EVT VT = Op.getValueType();
810 SDValue Src = Op.getOperand(0);
811 EVT SrcVT = Src.getValueType();
813 // First build an any-extend node which can be legalized above when we
814 // recurse through it.
815 Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
817 // Now we need sign extend. Do this by shifting the elements. Even if these
818 // aren't legal operations, they have a better chance of being legalized
819 // without full scalarization than the sign extension does.
820 unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
821 unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
822 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
823 return DAG.getNode(ISD::SRA, DL, VT,
824 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
828 // Generically expand a vector zext in register to a shuffle of the relevant
829 // lanes into the appropriate locations, a blend of zero into the high bits,
830 // and a bitcast to the wider element type.
831 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
833 EVT VT = Op.getValueType();
834 int NumElements = VT.getVectorNumElements();
835 SDValue Src = Op.getOperand(0);
836 EVT SrcVT = Src.getValueType();
837 int NumSrcElements = SrcVT.getVectorNumElements();
839 // Build up a zero vector to blend into this one.
840 EVT SrcScalarVT = SrcVT.getScalarType();
841 SDValue ScalarZero = DAG.getTargetConstant(0, DL, SrcScalarVT);
842 SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero);
843 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands);
845 // Shuffle the incoming lanes into the correct position, and pull all other
846 // lanes from the zero vector.
847 SmallVector<int, 16> ShuffleMask;
848 ShuffleMask.reserve(NumSrcElements);
849 for (int i = 0; i < NumSrcElements; ++i)
850 ShuffleMask.push_back(i);
852 int ExtLaneScale = NumSrcElements / NumElements;
853 int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0;
854 for (int i = 0; i < NumElements; ++i)
855 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
857 return DAG.getNode(ISD::BITCAST, DL, VT,
858 DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
861 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
862 EVT VT = Op.getValueType();
864 // Generate a byte wise shuffle mask for the BSWAP.
865 SmallVector<int, 16> ShuffleMask;
866 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
867 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
868 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
869 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
871 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
873 // Only emit a shuffle if the mask is legal.
874 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
875 return DAG.UnrollVectorOp(Op.getNode());
878 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
879 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
881 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
884 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
885 // Implement VSELECT in terms of XOR, AND, OR
886 // on platforms which do not support blend natively.
889 SDValue Mask = Op.getOperand(0);
890 SDValue Op1 = Op.getOperand(1);
891 SDValue Op2 = Op.getOperand(2);
893 EVT VT = Mask.getValueType();
895 // If we can't even use the basic vector operations of
896 // AND,OR,XOR, we will have to scalarize the op.
897 // Notice that the operation may be 'promoted' which means that it is
898 // 'bitcasted' to another type which is handled.
899 // This operation also isn't safe with AND, OR, XOR when the boolean
900 // type is 0/1 as we need an all ones vector constant to mask with.
901 // FIXME: Sign extend 1 to all ones if thats legal on the target.
902 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
903 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
904 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
905 TLI.getBooleanContents(Op1.getValueType()) !=
906 TargetLowering::ZeroOrNegativeOneBooleanContent)
907 return DAG.UnrollVectorOp(Op.getNode());
909 // If the mask and the type are different sizes, unroll the vector op. This
910 // can occur when getSetCCResultType returns something that is different in
911 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
912 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
913 return DAG.UnrollVectorOp(Op.getNode());
915 // Bitcast the operands to be the same type as the mask.
916 // This is needed when we select between FP types because
917 // the mask is a vector of integers.
918 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
919 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
921 SDValue AllOnes = DAG.getConstant(
922 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), DL, VT);
923 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
925 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
926 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
927 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
928 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
931 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
932 EVT VT = Op.getOperand(0).getValueType();
935 // Make sure that the SINT_TO_FP and SRL instructions are available.
936 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
937 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
938 return DAG.UnrollVectorOp(Op.getNode());
940 EVT SVT = VT.getScalarType();
941 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
942 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
944 unsigned BW = SVT.getSizeInBits();
945 SDValue HalfWord = DAG.getConstant(BW/2, DL, VT);
947 // Constants to clear the upper part of the word.
948 // Notice that we can also use SHL+SHR, but using a constant is slightly
950 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
951 SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
953 // Two to the power of half-word-size.
954 SDValue TWOHW = DAG.getConstantFP(1 << (BW/2), DL, Op.getValueType());
956 // Clear upper part of LO, lower HI
957 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
958 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
960 // Convert hi and lo to floats
961 // Convert the hi part back to the upper values
962 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
963 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
964 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
966 // Add the two halves
967 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
971 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
972 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
974 SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
975 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
976 Zero, Op.getOperand(0));
978 return DAG.UnrollVectorOp(Op.getNode());
981 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
982 EVT VT = Op.getValueType();
983 unsigned NumElems = VT.getVectorNumElements();
984 EVT EltVT = VT.getVectorElementType();
985 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
986 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
988 SmallVector<SDValue, 8> Ops(NumElems);
989 for (unsigned i = 0; i < NumElems; ++i) {
990 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
991 DAG.getConstant(i, dl, TLI.getVectorIdxTy()));
992 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
993 DAG.getConstant(i, dl, TLI.getVectorIdxTy()));
994 Ops[i] = DAG.getNode(ISD::SETCC, dl,
995 TLI.getSetCCResultType(*DAG.getContext(), TmpEltVT),
996 LHSElem, RHSElem, CC);
997 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
998 DAG.getConstant(APInt::getAllOnesValue
999 (EltVT.getSizeInBits()), dl, EltVT),
1000 DAG.getConstant(0, dl, EltVT));
1002 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1007 bool SelectionDAG::LegalizeVectors() {
1008 return VectorLegalizer(*this).Run();