1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::LegalizeVectors method.
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/Target/TargetLowering.h"
35 class VectorLegalizer {
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
40 /// For nodes that are of legal width, and that have more than one use, this
41 /// map indicates what regularized operand to use. This allows us to avoid
42 /// legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
45 /// \brief Adds a node to the translation cache.
46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
50 LegalizedNodes.insert(std::make_pair(To, To));
53 /// \brief Legalizes the given node.
54 SDValue LegalizeOp(SDValue Op);
56 /// \brief Assuming the node is legal, "legalize" the results.
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
59 /// \brief Implements unrolling a VSETCC.
60 SDValue UnrollVSETCC(SDValue Op);
62 /// \brief Implement expand-based legalization of vector operations.
64 /// This is just a high-level routine to dispatch to specific code paths for
65 /// operations to legalize them.
66 SDValue Expand(SDValue Op);
68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
71 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
72 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
76 SDValue ExpandSEXTINREG(SDValue Op);
78 /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
80 /// Shuffles the low lanes of the operand into place and bitcasts to the proper
81 /// type. The contents of the bits in the extended part of each element are
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
85 /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
87 /// Shuffles the low lanes of the operand into place, bitcasts to the proper
88 /// type, then shifts left and arithmetic shifts right to introduce a sign
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
92 /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
94 /// Shuffles the low lanes of the operand into place and blends zeros into
95 /// the remaining lanes, finally bitcasting to the proper type.
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
98 /// \brief Expand bswap of vectors into a shuffle if legal.
99 SDValue ExpandBSWAP(SDValue Op);
101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
102 /// supported by the target.
103 SDValue ExpandVSELECT(SDValue Op);
104 SDValue ExpandSELECT(SDValue Op);
105 SDValue ExpandLoad(SDValue Op);
106 SDValue ExpandStore(SDValue Op);
107 SDValue ExpandFNEG(SDValue Op);
109 /// \brief Implements vector promotion.
111 /// This is essentially just bitcasting the operands to a different type and
112 /// bitcasting the result back to the original type.
113 SDValue Promote(SDValue Op);
115 /// \brief Implements [SU]INT_TO_FP vector promotion.
117 /// This is a [zs]ext of the input operand to the next size up.
118 SDValue PromoteINT_TO_FP(SDValue Op);
120 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
122 /// It is promoted to the next size up integer type. The result is then
123 /// truncated back to the original type.
124 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
127 /// \brief Begin legalizer the vector operations in the DAG.
129 VectorLegalizer(SelectionDAG& dag) :
130 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
133 bool VectorLegalizer::Run() {
134 // Before we start legalizing vector nodes, check if there are any vectors.
135 bool HasVectors = false;
136 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
137 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
138 // Check if the values of the nodes contain vectors. We don't need to check
139 // the operands because we are going to check their values at some point.
140 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
142 HasVectors |= J->isVector();
144 // If we found a vector node we can start the legalization.
149 // If this basic block has no vectors then no need to legalize vectors.
153 // The legalize process is inherently a bottom-up recursive process (users
154 // legalize their uses before themselves). Given infinite stack space, we
155 // could just start legalizing on the root and traverse the whole graph. In
156 // practice however, this causes us to run out of stack space on large basic
157 // blocks. To avoid this problem, compute an ordering of the nodes where each
158 // node is only legalized after all of its operands are legalized.
159 DAG.AssignTopologicalOrder();
160 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
161 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
162 LegalizeOp(SDValue(I, 0));
164 // Finally, it's possible the root changed. Get the new root.
165 SDValue OldRoot = DAG.getRoot();
166 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
167 DAG.setRoot(LegalizedNodes[OldRoot]);
169 LegalizedNodes.clear();
171 // Remove dead nodes now.
172 DAG.RemoveDeadNodes();
177 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
178 // Generic legalization: just pass the operand through.
179 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
180 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
181 return Result.getValue(Op.getResNo());
184 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
185 // Note that LegalizeOp may be reentered even from single-use nodes, which
186 // means that we always must cache transformed nodes.
187 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
188 if (I != LegalizedNodes.end()) return I->second;
190 SDNode* Node = Op.getNode();
192 // Legalize the operands
193 SmallVector<SDValue, 8> Ops;
194 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
195 Ops.push_back(LegalizeOp(Node->getOperand(i)));
197 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
199 if (Op.getOpcode() == ISD::LOAD) {
200 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
201 ISD::LoadExtType ExtType = LD->getExtensionType();
202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
203 switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
204 LD->getMemoryVT())) {
205 default: llvm_unreachable("This action is not supported yet!");
206 case TargetLowering::Legal:
207 return TranslateLegalizeResults(Op, Result);
208 case TargetLowering::Custom:
209 if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
211 if (Lowered->getNumValues() != Op->getNumValues()) {
212 // This expanded to something other than the load. Assume the
213 // lowering code took care of any chain values, and just handle the
215 assert(Result.getValue(1).use_empty() &&
216 "There are still live users of the old chain!");
217 return LegalizeOp(Lowered);
219 return TranslateLegalizeResults(Op, Lowered);
222 case TargetLowering::Expand:
224 return LegalizeOp(ExpandLoad(Op));
226 } else if (Op.getOpcode() == ISD::STORE) {
227 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
228 EVT StVT = ST->getMemoryVT();
229 MVT ValVT = ST->getValue().getSimpleValueType();
230 if (StVT.isVector() && ST->isTruncatingStore())
231 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
232 default: llvm_unreachable("This action is not supported yet!");
233 case TargetLowering::Legal:
234 return TranslateLegalizeResults(Op, Result);
235 case TargetLowering::Custom:
237 return TranslateLegalizeResults(Op, TLI.LowerOperation(Result, DAG));
238 case TargetLowering::Expand:
240 return LegalizeOp(ExpandStore(Op));
244 bool HasVectorValue = false;
245 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
248 HasVectorValue |= J->isVector();
250 return TranslateLegalizeResults(Op, Result);
253 switch (Op.getOpcode()) {
255 return TranslateLegalizeResults(Op, Result);
279 case ISD::CTLZ_ZERO_UNDEF:
280 case ISD::CTTZ_ZERO_UNDEF:
286 case ISD::ZERO_EXTEND:
287 case ISD::ANY_EXTEND:
289 case ISD::SIGN_EXTEND:
290 case ISD::FP_TO_SINT:
291 case ISD::FP_TO_UINT:
310 case ISD::FNEARBYINT:
316 case ISD::SIGN_EXTEND_INREG:
317 case ISD::ANY_EXTEND_VECTOR_INREG:
318 case ISD::SIGN_EXTEND_VECTOR_INREG:
319 case ISD::ZERO_EXTEND_VECTOR_INREG:
320 QueryType = Node->getValueType(0);
322 case ISD::FP_ROUND_INREG:
323 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
325 case ISD::SINT_TO_FP:
326 case ISD::UINT_TO_FP:
327 QueryType = Node->getOperand(0).getValueType();
331 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
332 case TargetLowering::Promote:
333 Result = Promote(Op);
336 case TargetLowering::Legal:
338 case TargetLowering::Custom: {
339 SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
340 if (Tmp1.getNode()) {
346 case TargetLowering::Expand:
350 // Make sure that the generated code is itself legal.
352 Result = LegalizeOp(Result);
356 // Note that LegalizeOp may be reentered even from single-use nodes, which
357 // means that we always must cache transformed nodes.
358 AddLegalizedOperand(Op, Result);
362 SDValue VectorLegalizer::Promote(SDValue Op) {
363 // For a few operations there is a specific concept for promotion based on
364 // the operand's type.
365 switch (Op.getOpcode()) {
366 case ISD::SINT_TO_FP:
367 case ISD::UINT_TO_FP:
368 // "Promote" the operation by extending the operand.
369 return PromoteINT_TO_FP(Op);
370 case ISD::FP_TO_UINT:
371 case ISD::FP_TO_SINT:
372 // Promote the operation by extending the operand.
373 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
376 // There are currently two cases of vector promotion:
377 // 1) Bitcasting a vector of integers to a different type to a vector of the
378 // same overall length. For example, x86 promotes ISD::AND on v2i32 to v1i64.
379 // 2) Extending a vector of floats to a vector of the same number oflarger
380 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
381 MVT VT = Op.getSimpleValueType();
382 assert(Op.getNode()->getNumValues() == 1 &&
383 "Can't promote a vector with multiple results!");
384 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
386 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
388 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
389 if (Op.getOperand(j).getValueType().isVector())
392 .getVectorElementType()
393 .isFloatingPoint() &&
394 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
395 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
397 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
399 Operands[j] = Op.getOperand(j);
402 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands);
403 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
404 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
405 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
406 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0));
408 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
411 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
412 // INT_TO_FP operations may require the input operand be promoted even
413 // when the type is otherwise legal.
414 EVT VT = Op.getOperand(0).getValueType();
415 assert(Op.getNode()->getNumValues() == 1 &&
416 "Can't promote a vector with multiple results!");
418 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
419 // by widening the vector w/ the same element width and twice the number
420 // of elements. We want the other way around, the same number of elements,
421 // each twice the width.
423 // Increase the bitwidth of the element to the next pow-of-two
424 // (which is greater than 8 bits).
426 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
427 assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
429 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
431 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
433 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
434 if (Op.getOperand(j).getValueType().isVector())
435 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
437 Operands[j] = Op.getOperand(j);
440 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
443 // For FP_TO_INT we promote the result type to a vector type with wider
444 // elements and then truncate the result. This is different from the default
445 // PromoteVector which uses bitcast to promote thus assumning that the
446 // promoted vector type has the same overall size.
447 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
448 assert(Op.getNode()->getNumValues() == 1 &&
449 "Can't promote a vector with multiple results!");
450 EVT VT = Op.getValueType();
455 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
456 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
457 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
458 NewOpc = ISD::FP_TO_SINT;
461 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
462 NewOpc = ISD::FP_TO_UINT;
468 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
469 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
473 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
475 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
476 SDValue Chain = LD->getChain();
477 SDValue BasePTR = LD->getBasePtr();
478 EVT SrcVT = LD->getMemoryVT();
479 ISD::LoadExtType ExtType = LD->getExtensionType();
481 SmallVector<SDValue, 8> Vals;
482 SmallVector<SDValue, 8> LoadChains;
483 unsigned NumElem = SrcVT.getVectorNumElements();
485 EVT SrcEltVT = SrcVT.getScalarType();
486 EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
488 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
489 // When elements in a vector is not byte-addressable, we cannot directly
490 // load each element by advancing pointer, which could only address bytes.
491 // Instead, we load all significant words, mask bits off, and concatenate
492 // them to form each element. Finally, they are extended to destination
493 // scalar type to build the destination vector.
494 EVT WideVT = TLI.getPointerTy();
496 assert(WideVT.isRound() &&
497 "Could not handle the sophisticated case when the widest integer is"
499 assert(WideVT.bitsGE(SrcEltVT) &&
500 "Type is not legalized?");
502 unsigned WideBytes = WideVT.getStoreSize();
504 unsigned RemainingBytes = SrcVT.getStoreSize();
505 SmallVector<SDValue, 8> LoadVals;
507 while (RemainingBytes > 0) {
509 unsigned LoadBytes = WideBytes;
511 if (RemainingBytes >= LoadBytes) {
512 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
513 LD->getPointerInfo().getWithOffset(Offset),
514 LD->isVolatile(), LD->isNonTemporal(),
516 MinAlign(LD->getAlignment(), Offset),
520 while (RemainingBytes < LoadBytes) {
521 LoadBytes >>= 1; // Reduce the load size by half.
522 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
524 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
525 LD->getPointerInfo().getWithOffset(Offset),
526 LoadVT, LD->isVolatile(),
527 LD->isNonTemporal(), LD->isInvariant(),
528 MinAlign(LD->getAlignment(), Offset),
532 RemainingBytes -= LoadBytes;
534 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
535 DAG.getConstant(LoadBytes, BasePTR.getValueType()));
537 LoadVals.push_back(ScalarLoad.getValue(0));
538 LoadChains.push_back(ScalarLoad.getValue(1));
541 // Extract bits, pack and extend/trunc them into destination type.
542 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
543 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, WideVT);
545 unsigned BitOffset = 0;
546 unsigned WideIdx = 0;
547 unsigned WideBits = WideVT.getSizeInBits();
549 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
550 SDValue Lo, Hi, ShAmt;
552 if (BitOffset < WideBits) {
553 ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
554 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
555 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
558 BitOffset += SrcEltBits;
559 if (BitOffset >= WideBits) {
561 BitOffset -= WideBits;
563 ShAmt = DAG.getConstant(SrcEltBits - BitOffset,
564 TLI.getShiftAmountTy(WideVT));
565 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
566 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
571 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
574 default: llvm_unreachable("Unknown extended-load op!");
576 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
579 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
582 ShAmt = DAG.getConstant(WideBits - SrcEltBits,
583 TLI.getShiftAmountTy(WideVT));
584 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
585 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
586 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
592 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
594 for (unsigned Idx=0; Idx<NumElem; Idx++) {
595 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
596 Op.getNode()->getValueType(0).getScalarType(),
597 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
598 SrcVT.getScalarType(),
599 LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(),
600 MinAlign(LD->getAlignment(), Idx * Stride), LD->getAAInfo());
602 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
603 DAG.getConstant(Stride, BasePTR.getValueType()));
605 Vals.push_back(ScalarLoad.getValue(0));
606 LoadChains.push_back(ScalarLoad.getValue(1));
610 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
611 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
612 Op.getNode()->getValueType(0), Vals);
614 AddLegalizedOperand(Op.getValue(0), Value);
615 AddLegalizedOperand(Op.getValue(1), NewChain);
617 return (Op.getResNo() ? NewChain : Value);
620 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
622 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
623 SDValue Chain = ST->getChain();
624 SDValue BasePTR = ST->getBasePtr();
625 SDValue Value = ST->getValue();
626 EVT StVT = ST->getMemoryVT();
628 unsigned Alignment = ST->getAlignment();
629 bool isVolatile = ST->isVolatile();
630 bool isNonTemporal = ST->isNonTemporal();
631 AAMDNodes AAInfo = ST->getAAInfo();
633 unsigned NumElem = StVT.getVectorNumElements();
634 // The type of the data we want to save
635 EVT RegVT = Value.getValueType();
636 EVT RegSclVT = RegVT.getScalarType();
637 // The type of data as saved in memory.
638 EVT MemSclVT = StVT.getScalarType();
640 // Cast floats into integers
641 unsigned ScalarSize = MemSclVT.getSizeInBits();
643 // Round odd types to the next pow of two.
644 if (!isPowerOf2_32(ScalarSize))
645 ScalarSize = NextPowerOf2(ScalarSize);
647 // Store Stride in bytes
648 unsigned Stride = ScalarSize/8;
649 // Extract each of the elements from the original vector
650 // and save them into memory individually.
651 SmallVector<SDValue, 8> Stores;
652 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
653 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
654 RegSclVT, Value, DAG.getConstant(Idx, TLI.getVectorIdxTy()));
656 // This scalar TruncStore may be illegal, but we legalize it later.
657 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
658 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
659 isVolatile, isNonTemporal, MinAlign(Alignment, Idx*Stride),
662 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
663 DAG.getConstant(Stride, BasePTR.getValueType()));
665 Stores.push_back(Store);
667 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
668 AddLegalizedOperand(Op, TF);
672 SDValue VectorLegalizer::Expand(SDValue Op) {
673 switch (Op->getOpcode()) {
674 case ISD::SIGN_EXTEND_INREG:
675 return ExpandSEXTINREG(Op);
676 case ISD::ANY_EXTEND_VECTOR_INREG:
677 return ExpandANY_EXTEND_VECTOR_INREG(Op);
678 case ISD::SIGN_EXTEND_VECTOR_INREG:
679 return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
680 case ISD::ZERO_EXTEND_VECTOR_INREG:
681 return ExpandZERO_EXTEND_VECTOR_INREG(Op);
683 return ExpandBSWAP(Op);
685 return ExpandVSELECT(Op);
687 return ExpandSELECT(Op);
688 case ISD::UINT_TO_FP:
689 return ExpandUINT_TO_FLOAT(Op);
691 return ExpandFNEG(Op);
693 return UnrollVSETCC(Op);
695 return DAG.UnrollVectorOp(Op.getNode());
699 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
700 // Lower a select instruction where the condition is a scalar and the
701 // operands are vectors. Lower this select to VSELECT and implement it
702 // using XOR AND OR. The selector bit is broadcasted.
703 EVT VT = Op.getValueType();
706 SDValue Mask = Op.getOperand(0);
707 SDValue Op1 = Op.getOperand(1);
708 SDValue Op2 = Op.getOperand(2);
710 assert(VT.isVector() && !Mask.getValueType().isVector()
711 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
713 unsigned NumElem = VT.getVectorNumElements();
715 // If we can't even use the basic vector operations of
716 // AND,OR,XOR, we will have to scalarize the op.
717 // Notice that the operation may be 'promoted' which means that it is
718 // 'bitcasted' to another type which is handled.
719 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
720 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
721 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
722 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
723 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
724 return DAG.UnrollVectorOp(Op.getNode());
726 // Generate a mask operand.
727 EVT MaskTy = VT.changeVectorElementTypeToInteger();
729 // What is the size of each element in the vector mask.
730 EVT BitTy = MaskTy.getScalarType();
732 Mask = DAG.getSelect(DL, BitTy, Mask,
733 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy),
734 DAG.getConstant(0, BitTy));
736 // Broadcast the mask so that the entire vector is all-one or all zero.
737 SmallVector<SDValue, 8> Ops(NumElem, Mask);
738 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
740 // Bitcast the operands to be the same type as the mask.
741 // This is needed when we select between FP types because
742 // the mask is a vector of integers.
743 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
744 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
746 SDValue AllOnes = DAG.getConstant(
747 APInt::getAllOnesValue(BitTy.getSizeInBits()), MaskTy);
748 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
750 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
751 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
752 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
753 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
756 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
757 EVT VT = Op.getValueType();
759 // Make sure that the SRA and SHL instructions are available.
760 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
761 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
762 return DAG.UnrollVectorOp(Op.getNode());
765 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
767 unsigned BW = VT.getScalarType().getSizeInBits();
768 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
769 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT);
771 Op = Op.getOperand(0);
772 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
773 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
776 // Generically expand a vector anyext in register to a shuffle of the relevant
777 // lanes into the appropriate locations, with other lanes left undef.
778 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
780 EVT VT = Op.getValueType();
781 int NumElements = VT.getVectorNumElements();
782 SDValue Src = Op.getOperand(0);
783 EVT SrcVT = Src.getValueType();
784 int NumSrcElements = SrcVT.getVectorNumElements();
786 // Build a base mask of undef shuffles.
787 SmallVector<int, 16> ShuffleMask;
788 ShuffleMask.resize(NumSrcElements, -1);
790 // Place the extended lanes into the correct locations.
791 int ExtLaneScale = NumSrcElements / NumElements;
792 int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0;
793 for (int i = 0; i < NumElements; ++i)
794 ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
797 ISD::BITCAST, DL, VT,
798 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
801 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
803 EVT VT = Op.getValueType();
804 SDValue Src = Op.getOperand(0);
805 EVT SrcVT = Src.getValueType();
807 // First build an any-extend node which can be legalized above when we
808 // recurse through it.
809 Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
811 // Now we need sign extend. Do this by shifting the elements. Even if these
812 // aren't legal operations, they have a better chance of being legalized
813 // without full scalarization than the sign extension does.
814 unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
815 unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
816 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, VT);
817 return DAG.getNode(ISD::SRA, DL, VT,
818 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
822 // Generically expand a vector zext in register to a shuffle of the relevant
823 // lanes into the appropriate locations, a blend of zero into the high bits,
824 // and a bitcast to the wider element type.
825 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
827 EVT VT = Op.getValueType();
828 int NumElements = VT.getVectorNumElements();
829 SDValue Src = Op.getOperand(0);
830 EVT SrcVT = Src.getValueType();
831 int NumSrcElements = SrcVT.getVectorNumElements();
833 // Build up a zero vector to blend into this one.
834 EVT SrcScalarVT = SrcVT.getScalarType();
835 SDValue ScalarZero = DAG.getTargetConstant(0, SrcScalarVT);
836 SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero);
837 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands);
839 // Shuffle the incoming lanes into the correct position, and pull all other
840 // lanes from the zero vector.
841 SmallVector<int, 16> ShuffleMask;
842 ShuffleMask.reserve(NumSrcElements);
843 for (int i = 0; i < NumSrcElements; ++i)
844 ShuffleMask.push_back(i);
846 int ExtLaneScale = NumSrcElements / NumElements;
847 int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0;
848 for (int i = 0; i < NumElements; ++i)
849 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
851 return DAG.getNode(ISD::BITCAST, DL, VT,
852 DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
855 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
856 EVT VT = Op.getValueType();
858 // Generate a byte wise shuffle mask for the BSWAP.
859 SmallVector<int, 16> ShuffleMask;
860 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
861 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
862 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
863 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
865 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
867 // Only emit a shuffle if the mask is legal.
868 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
869 return DAG.UnrollVectorOp(Op.getNode());
872 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
873 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
875 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
878 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
879 // Implement VSELECT in terms of XOR, AND, OR
880 // on platforms which do not support blend natively.
883 SDValue Mask = Op.getOperand(0);
884 SDValue Op1 = Op.getOperand(1);
885 SDValue Op2 = Op.getOperand(2);
887 EVT VT = Mask.getValueType();
889 // If we can't even use the basic vector operations of
890 // AND,OR,XOR, we will have to scalarize the op.
891 // Notice that the operation may be 'promoted' which means that it is
892 // 'bitcasted' to another type which is handled.
893 // This operation also isn't safe with AND, OR, XOR when the boolean
894 // type is 0/1 as we need an all ones vector constant to mask with.
895 // FIXME: Sign extend 1 to all ones if thats legal on the target.
896 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
897 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
898 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
899 TLI.getBooleanContents(Op1.getValueType()) !=
900 TargetLowering::ZeroOrNegativeOneBooleanContent)
901 return DAG.UnrollVectorOp(Op.getNode());
903 // If the mask and the type are different sizes, unroll the vector op. This
904 // can occur when getSetCCResultType returns something that is different in
905 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
906 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
907 return DAG.UnrollVectorOp(Op.getNode());
909 // Bitcast the operands to be the same type as the mask.
910 // This is needed when we select between FP types because
911 // the mask is a vector of integers.
912 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
913 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
915 SDValue AllOnes = DAG.getConstant(
916 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT);
917 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
919 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
920 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
921 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
922 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
925 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
926 EVT VT = Op.getOperand(0).getValueType();
929 // Make sure that the SINT_TO_FP and SRL instructions are available.
930 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
931 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
932 return DAG.UnrollVectorOp(Op.getNode());
934 EVT SVT = VT.getScalarType();
935 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
936 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
938 unsigned BW = SVT.getSizeInBits();
939 SDValue HalfWord = DAG.getConstant(BW/2, VT);
941 // Constants to clear the upper part of the word.
942 // Notice that we can also use SHL+SHR, but using a constant is slightly
944 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
945 SDValue HalfWordMask = DAG.getConstant(HWMask, VT);
947 // Two to the power of half-word-size.
948 SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType());
950 // Clear upper part of LO, lower HI
951 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
952 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
954 // Convert hi and lo to floats
955 // Convert the hi part back to the upper values
956 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
957 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
958 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
960 // Add the two halves
961 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
965 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
966 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
967 SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType());
968 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
969 Zero, Op.getOperand(0));
971 return DAG.UnrollVectorOp(Op.getNode());
974 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
975 EVT VT = Op.getValueType();
976 unsigned NumElems = VT.getVectorNumElements();
977 EVT EltVT = VT.getVectorElementType();
978 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
979 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
981 SmallVector<SDValue, 8> Ops(NumElems);
982 for (unsigned i = 0; i < NumElems; ++i) {
983 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
984 DAG.getConstant(i, TLI.getVectorIdxTy()));
985 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
986 DAG.getConstant(i, TLI.getVectorIdxTy()));
987 Ops[i] = DAG.getNode(ISD::SETCC, dl,
988 TLI.getSetCCResultType(*DAG.getContext(), TmpEltVT),
989 LHSElem, RHSElem, CC);
990 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
991 DAG.getConstant(APInt::getAllOnesValue
992 (EltVT.getSizeInBits()), EltVT),
993 DAG.getConstant(0, EltVT));
995 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1000 bool SelectionDAG::LegalizeVectors() {
1001 return VectorLegalizer(*this).Run();