1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::LegalizeVectors method.
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/Target/TargetLowering.h"
35 class VectorLegalizer {
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
40 /// LegalizedNodes - For nodes that are of legal width, and that have more
41 /// than one use, this map indicates what regularized operand to use. This
42 /// allows us to avoid legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
45 // Adds a node to the translation cache
46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
50 LegalizedNodes.insert(std::make_pair(To, To));
53 // Legalizes the given node
54 SDValue LegalizeOp(SDValue Op);
55 // Assuming the node is legal, "legalize" the results
56 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
57 // Implements unrolling a VSETCC.
58 SDValue UnrollVSETCC(SDValue Op);
59 // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB
61 // Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
62 // SINT_TO_FLOAT and SHR on vectors isn't legal.
63 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
64 // Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
65 SDValue ExpandSEXTINREG(SDValue Op);
66 // Implement vselect in terms of XOR, AND, OR when blend is not supported
68 SDValue ExpandVSELECT(SDValue Op);
69 SDValue ExpandSELECT(SDValue Op);
70 SDValue ExpandLoad(SDValue Op);
71 SDValue ExpandStore(SDValue Op);
72 SDValue ExpandFNEG(SDValue Op);
73 // Implements vector promotion; this is essentially just bitcasting the
74 // operands to a different type and bitcasting the result back to the
76 SDValue PromoteVectorOp(SDValue Op);
77 // Implements [SU]INT_TO_FP vector promotion; this is a [zs]ext of the input
78 // operand to the next size up.
79 SDValue PromoteVectorOpINT_TO_FP(SDValue Op);
83 VectorLegalizer(SelectionDAG& dag) :
84 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
87 bool VectorLegalizer::Run() {
88 // Before we start legalizing vector nodes, check if there are any vectors.
89 bool HasVectors = false;
90 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
91 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) {
92 // Check if the values of the nodes contain vectors. We don't need to check
93 // the operands because we are going to check their values at some point.
94 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
96 HasVectors |= J->isVector();
98 // If we found a vector node we can start the legalization.
103 // If this basic block has no vectors then no need to legalize vectors.
107 // The legalize process is inherently a bottom-up recursive process (users
108 // legalize their uses before themselves). Given infinite stack space, we
109 // could just start legalizing on the root and traverse the whole graph. In
110 // practice however, this causes us to run out of stack space on large basic
111 // blocks. To avoid this problem, compute an ordering of the nodes where each
112 // node is only legalized after all of its operands are legalized.
113 DAG.AssignTopologicalOrder();
114 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
115 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
116 LegalizeOp(SDValue(I, 0));
118 // Finally, it's possible the root changed. Get the new root.
119 SDValue OldRoot = DAG.getRoot();
120 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
121 DAG.setRoot(LegalizedNodes[OldRoot]);
123 LegalizedNodes.clear();
125 // Remove dead nodes now.
126 DAG.RemoveDeadNodes();
131 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
132 // Generic legalization: just pass the operand through.
133 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
134 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
135 return Result.getValue(Op.getResNo());
138 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
139 // Note that LegalizeOp may be reentered even from single-use nodes, which
140 // means that we always must cache transformed nodes.
141 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
142 if (I != LegalizedNodes.end()) return I->second;
144 SDNode* Node = Op.getNode();
146 // Legalize the operands
147 SmallVector<SDValue, 8> Ops;
148 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
149 Ops.push_back(LegalizeOp(Node->getOperand(i)));
152 SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops.data(), Ops.size()), 0);
154 if (Op.getOpcode() == ISD::LOAD) {
155 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
156 ISD::LoadExtType ExtType = LD->getExtensionType();
157 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
158 if (TLI.isLoadExtLegal(LD->getExtensionType(), LD->getMemoryVT()))
159 return TranslateLegalizeResults(Op, Result);
161 return LegalizeOp(ExpandLoad(Op));
163 } else if (Op.getOpcode() == ISD::STORE) {
164 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
165 EVT StVT = ST->getMemoryVT();
166 MVT ValVT = ST->getValue().getSimpleValueType();
167 if (StVT.isVector() && ST->isTruncatingStore())
168 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
169 default: llvm_unreachable("This action is not supported yet!");
170 case TargetLowering::Legal:
171 return TranslateLegalizeResults(Op, Result);
172 case TargetLowering::Custom:
174 return LegalizeOp(TLI.LowerOperation(Result, DAG));
175 case TargetLowering::Expand:
177 return LegalizeOp(ExpandStore(Op));
181 bool HasVectorValue = false;
182 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
185 HasVectorValue |= J->isVector();
187 return TranslateLegalizeResults(Op, Result);
190 switch (Op.getOpcode()) {
192 return TranslateLegalizeResults(Op, Result);
215 case ISD::CTLZ_ZERO_UNDEF:
216 case ISD::CTTZ_ZERO_UNDEF:
222 case ISD::ZERO_EXTEND:
223 case ISD::ANY_EXTEND:
225 case ISD::SIGN_EXTEND:
226 case ISD::FP_TO_SINT:
227 case ISD::FP_TO_UINT:
243 case ISD::FNEARBYINT:
248 case ISD::SIGN_EXTEND_INREG:
249 QueryType = Node->getValueType(0);
251 case ISD::FP_ROUND_INREG:
252 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
254 case ISD::SINT_TO_FP:
255 case ISD::UINT_TO_FP:
256 QueryType = Node->getOperand(0).getValueType();
260 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
261 case TargetLowering::Promote:
262 switch (Op.getOpcode()) {
264 // "Promote" the operation by bitcasting
265 Result = PromoteVectorOp(Op);
268 case ISD::SINT_TO_FP:
269 case ISD::UINT_TO_FP:
270 // "Promote" the operation by extending the operand.
271 Result = PromoteVectorOpINT_TO_FP(Op);
276 case TargetLowering::Legal: break;
277 case TargetLowering::Custom: {
278 SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
279 if (Tmp1.getNode()) {
285 case TargetLowering::Expand:
286 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG)
287 Result = ExpandSEXTINREG(Op);
288 else if (Node->getOpcode() == ISD::VSELECT)
289 Result = ExpandVSELECT(Op);
290 else if (Node->getOpcode() == ISD::SELECT)
291 Result = ExpandSELECT(Op);
292 else if (Node->getOpcode() == ISD::UINT_TO_FP)
293 Result = ExpandUINT_TO_FLOAT(Op);
294 else if (Node->getOpcode() == ISD::FNEG)
295 Result = ExpandFNEG(Op);
296 else if (Node->getOpcode() == ISD::SETCC)
297 Result = UnrollVSETCC(Op);
299 Result = DAG.UnrollVectorOp(Op.getNode());
303 // Make sure that the generated code is itself legal.
305 Result = LegalizeOp(Result);
309 // Note that LegalizeOp may be reentered even from single-use nodes, which
310 // means that we always must cache transformed nodes.
311 AddLegalizedOperand(Op, Result);
315 SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
316 // Vector "promotion" is basically just bitcasting and doing the operation
317 // in a different type. For example, x86 promotes ISD::AND on v2i32 to
319 MVT VT = Op.getSimpleValueType();
320 assert(Op.getNode()->getNumValues() == 1 &&
321 "Can't promote a vector with multiple results!");
322 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
324 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
326 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
327 if (Op.getOperand(j).getValueType().isVector())
328 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
330 Operands[j] = Op.getOperand(j);
333 Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size());
335 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
338 SDValue VectorLegalizer::PromoteVectorOpINT_TO_FP(SDValue Op) {
339 // INT_TO_FP operations may require the input operand be promoted even
340 // when the type is otherwise legal.
341 EVT VT = Op.getOperand(0).getValueType();
342 assert(Op.getNode()->getNumValues() == 1 &&
343 "Can't promote a vector with multiple results!");
345 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
346 // by widening the vector w/ the same element width and twice the number
347 // of elements. We want the other way around, the same number of elements,
348 // each twice the width.
350 // Increase the bitwidth of the element to the next pow-of-two
351 // (which is greater than 8 bits).
352 unsigned NumElts = VT.getVectorNumElements();
353 EVT EltVT = VT.getVectorElementType();
354 EltVT = EVT::getIntegerVT(*DAG.getContext(), 2 * EltVT.getSizeInBits());
355 assert(EltVT.isSimple() && "Promoting to a non-simple vector type!");
357 // Build a new vector type and check if it is legal.
358 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
361 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
363 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
365 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
366 if (Op.getOperand(j).getValueType().isVector())
367 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
369 Operands[j] = Op.getOperand(j);
372 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), &Operands[0],
377 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
379 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
380 SDValue Chain = LD->getChain();
381 SDValue BasePTR = LD->getBasePtr();
382 EVT SrcVT = LD->getMemoryVT();
383 ISD::LoadExtType ExtType = LD->getExtensionType();
385 SmallVector<SDValue, 8> Vals;
386 SmallVector<SDValue, 8> LoadChains;
387 unsigned NumElem = SrcVT.getVectorNumElements();
389 EVT SrcEltVT = SrcVT.getScalarType();
390 EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
392 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
393 // When elements in a vector is not byte-addressable, we cannot directly
394 // load each element by advancing pointer, which could only address bytes.
395 // Instead, we load all significant words, mask bits off, and concatenate
396 // them to form each element. Finally, they are extended to destination
397 // scalar type to build the destination vector.
398 EVT WideVT = TLI.getPointerTy();
400 assert(WideVT.isRound() &&
401 "Could not handle the sophisticated case when the widest integer is"
403 assert(WideVT.bitsGE(SrcEltVT) &&
404 "Type is not legalized?");
406 unsigned WideBytes = WideVT.getStoreSize();
408 unsigned RemainingBytes = SrcVT.getStoreSize();
409 SmallVector<SDValue, 8> LoadVals;
411 while (RemainingBytes > 0) {
413 unsigned LoadBytes = WideBytes;
415 if (RemainingBytes >= LoadBytes) {
416 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
417 LD->getPointerInfo().getWithOffset(Offset),
418 LD->isVolatile(), LD->isNonTemporal(),
419 LD->isInvariant(), LD->getAlignment());
422 while (RemainingBytes < LoadBytes) {
423 LoadBytes >>= 1; // Reduce the load size by half.
424 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
426 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
427 LD->getPointerInfo().getWithOffset(Offset),
428 LoadVT, LD->isVolatile(),
429 LD->isNonTemporal(), LD->getAlignment());
432 RemainingBytes -= LoadBytes;
434 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
435 DAG.getIntPtrConstant(LoadBytes));
437 LoadVals.push_back(ScalarLoad.getValue(0));
438 LoadChains.push_back(ScalarLoad.getValue(1));
441 // Extract bits, pack and extend/trunc them into destination type.
442 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
443 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, WideVT);
445 unsigned BitOffset = 0;
446 unsigned WideIdx = 0;
447 unsigned WideBits = WideVT.getSizeInBits();
449 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
450 SDValue Lo, Hi, ShAmt;
452 if (BitOffset < WideBits) {
453 ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
454 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
455 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
458 BitOffset += SrcEltBits;
459 if (BitOffset >= WideBits) {
463 ShAmt = DAG.getConstant(SrcEltBits - Offset,
464 TLI.getShiftAmountTy(WideVT));
465 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
466 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
471 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
474 default: llvm_unreachable("Unknown extended-load op!");
476 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
479 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
482 ShAmt = DAG.getConstant(WideBits - SrcEltBits,
483 TLI.getShiftAmountTy(WideVT));
484 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
485 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
486 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
492 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
494 for (unsigned Idx=0; Idx<NumElem; Idx++) {
495 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
496 Op.getNode()->getValueType(0).getScalarType(),
497 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
498 SrcVT.getScalarType(),
499 LD->isVolatile(), LD->isNonTemporal(),
502 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
503 DAG.getIntPtrConstant(Stride));
505 Vals.push_back(ScalarLoad.getValue(0));
506 LoadChains.push_back(ScalarLoad.getValue(1));
510 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
511 &LoadChains[0], LoadChains.size());
512 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
513 Op.getNode()->getValueType(0), &Vals[0], Vals.size());
515 AddLegalizedOperand(Op.getValue(0), Value);
516 AddLegalizedOperand(Op.getValue(1), NewChain);
518 return (Op.getResNo() ? NewChain : Value);
521 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
523 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
524 SDValue Chain = ST->getChain();
525 SDValue BasePTR = ST->getBasePtr();
526 SDValue Value = ST->getValue();
527 EVT StVT = ST->getMemoryVT();
529 unsigned Alignment = ST->getAlignment();
530 bool isVolatile = ST->isVolatile();
531 bool isNonTemporal = ST->isNonTemporal();
533 unsigned NumElem = StVT.getVectorNumElements();
534 // The type of the data we want to save
535 EVT RegVT = Value.getValueType();
536 EVT RegSclVT = RegVT.getScalarType();
537 // The type of data as saved in memory.
538 EVT MemSclVT = StVT.getScalarType();
540 // Cast floats into integers
541 unsigned ScalarSize = MemSclVT.getSizeInBits();
543 // Round odd types to the next pow of two.
544 if (!isPowerOf2_32(ScalarSize))
545 ScalarSize = NextPowerOf2(ScalarSize);
547 // Store Stride in bytes
548 unsigned Stride = ScalarSize/8;
549 // Extract each of the elements from the original vector
550 // and save them into memory individually.
551 SmallVector<SDValue, 8> Stores;
552 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
553 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
554 RegSclVT, Value, DAG.getConstant(Idx, TLI.getVectorIdxTy()));
556 // This scalar TruncStore may be illegal, but we legalize it later.
557 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
558 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
559 isVolatile, isNonTemporal, Alignment);
561 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
562 DAG.getIntPtrConstant(Stride));
564 Stores.push_back(Store);
566 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
567 &Stores[0], Stores.size());
568 AddLegalizedOperand(Op, TF);
572 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
573 // Lower a select instruction where the condition is a scalar and the
574 // operands are vectors. Lower this select to VSELECT and implement it
575 // using XOR AND OR. The selector bit is broadcasted.
576 EVT VT = Op.getValueType();
579 SDValue Mask = Op.getOperand(0);
580 SDValue Op1 = Op.getOperand(1);
581 SDValue Op2 = Op.getOperand(2);
583 assert(VT.isVector() && !Mask.getValueType().isVector()
584 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
586 unsigned NumElem = VT.getVectorNumElements();
588 // If we can't even use the basic vector operations of
589 // AND,OR,XOR, we will have to scalarize the op.
590 // Notice that the operation may be 'promoted' which means that it is
591 // 'bitcasted' to another type which is handled.
592 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
593 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
594 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
595 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
596 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
597 return DAG.UnrollVectorOp(Op.getNode());
599 // Generate a mask operand.
600 EVT MaskTy = TLI.getSetCCResultType(*DAG.getContext(), VT);
601 assert(MaskTy.isVector() && "Invalid CC type");
602 assert(MaskTy.getSizeInBits() == Op1.getValueType().getSizeInBits()
603 && "Invalid mask size");
605 // What is the size of each element in the vector mask.
606 EVT BitTy = MaskTy.getScalarType();
608 Mask = DAG.getSelect(DL, BitTy, Mask,
609 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy),
610 DAG.getConstant(0, BitTy));
612 // Broadcast the mask so that the entire vector is all-one or all zero.
613 SmallVector<SDValue, 8> Ops(NumElem, Mask);
614 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, &Ops[0], Ops.size());
616 // Bitcast the operands to be the same type as the mask.
617 // This is needed when we select between FP types because
618 // the mask is a vector of integers.
619 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
620 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
622 SDValue AllOnes = DAG.getConstant(
623 APInt::getAllOnesValue(BitTy.getSizeInBits()), MaskTy);
624 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
626 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
627 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
628 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
629 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
632 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
633 EVT VT = Op.getValueType();
635 // Make sure that the SRA and SHL instructions are available.
636 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
637 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
638 return DAG.UnrollVectorOp(Op.getNode());
641 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
643 unsigned BW = VT.getScalarType().getSizeInBits();
644 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
645 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT);
647 Op = Op.getOperand(0);
648 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
649 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
652 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
653 // Implement VSELECT in terms of XOR, AND, OR
654 // on platforms which do not support blend natively.
657 SDValue Mask = Op.getOperand(0);
658 SDValue Op1 = Op.getOperand(1);
659 SDValue Op2 = Op.getOperand(2);
661 EVT VT = Mask.getValueType();
663 // If we can't even use the basic vector operations of
664 // AND,OR,XOR, we will have to scalarize the op.
665 // Notice that the operation may be 'promoted' which means that it is
666 // 'bitcasted' to another type which is handled.
667 // This operation also isn't safe with AND, OR, XOR when the boolean
668 // type is 0/1 as we need an all ones vector constant to mask with.
669 // FIXME: Sign extend 1 to all ones if thats legal on the target.
670 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
671 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
672 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
673 TLI.getBooleanContents(true) !=
674 TargetLowering::ZeroOrNegativeOneBooleanContent)
675 return DAG.UnrollVectorOp(Op.getNode());
677 // If the mask and the type are different sizes, unroll the vector op. This
678 // can occur when getSetCCResultType returns something that is different in
679 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
680 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
681 return DAG.UnrollVectorOp(Op.getNode());
683 // Bitcast the operands to be the same type as the mask.
684 // This is needed when we select between FP types because
685 // the mask is a vector of integers.
686 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
687 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
689 SDValue AllOnes = DAG.getConstant(
690 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT);
691 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
693 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
694 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
695 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
696 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
699 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
700 EVT VT = Op.getOperand(0).getValueType();
703 // Make sure that the SINT_TO_FP and SRL instructions are available.
704 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
705 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
706 return DAG.UnrollVectorOp(Op.getNode());
708 EVT SVT = VT.getScalarType();
709 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
710 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
712 unsigned BW = SVT.getSizeInBits();
713 SDValue HalfWord = DAG.getConstant(BW/2, VT);
715 // Constants to clear the upper part of the word.
716 // Notice that we can also use SHL+SHR, but using a constant is slightly
718 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
719 SDValue HalfWordMask = DAG.getConstant(HWMask, VT);
721 // Two to the power of half-word-size.
722 SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType());
724 // Clear upper part of LO, lower HI
725 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
726 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
728 // Convert hi and lo to floats
729 // Convert the hi part back to the upper values
730 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
731 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
732 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
734 // Add the two halves
735 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
739 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
740 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
741 SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType());
742 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
743 Zero, Op.getOperand(0));
745 return DAG.UnrollVectorOp(Op.getNode());
748 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
749 EVT VT = Op.getValueType();
750 unsigned NumElems = VT.getVectorNumElements();
751 EVT EltVT = VT.getVectorElementType();
752 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
753 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
755 SmallVector<SDValue, 8> Ops(NumElems);
756 for (unsigned i = 0; i < NumElems; ++i) {
757 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
758 DAG.getConstant(i, TLI.getVectorIdxTy()));
759 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
760 DAG.getConstant(i, TLI.getVectorIdxTy()));
761 Ops[i] = DAG.getNode(ISD::SETCC, dl,
762 TLI.getSetCCResultType(*DAG.getContext(), TmpEltVT),
763 LHSElem, RHSElem, CC);
764 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
765 DAG.getConstant(APInt::getAllOnesValue
766 (EltVT.getSizeInBits()), EltVT),
767 DAG.getConstant(0, EltVT));
769 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
774 bool SelectionDAG::LegalizeVectors() {
775 return VectorLegalizer(*this).Run();