1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::LegalizeVectors method.
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/Target/TargetLowering.h"
35 class VectorLegalizer {
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
40 /// For nodes that are of legal width, and that have more than one use, this
41 /// map indicates what regularized operand to use. This allows us to avoid
42 /// legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
45 /// \brief Adds a node to the translation cache.
46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
50 LegalizedNodes.insert(std::make_pair(To, To));
53 /// \brief Legalizes the given node.
54 SDValue LegalizeOp(SDValue Op);
56 /// \brief Assuming the node is legal, "legalize" the results.
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
59 /// \brief Implements unrolling a VSETCC.
60 SDValue UnrollVSETCC(SDValue Op);
62 /// \brief Implement expand-based legalization of vector operations.
64 /// This is just a high-level routine to dispatch to specific code paths for
65 /// operations to legalize them.
66 SDValue Expand(SDValue Op);
68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
71 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
72 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
76 SDValue ExpandSEXTINREG(SDValue Op);
78 /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
80 /// Shuffles the low lanes of the operand into place and bitcasts to the proper
81 /// type. The contents of the bits in the extended part of each element are
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
85 /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
87 /// Shuffles the low lanes of the operand into place, bitcasts to the proper
88 /// type, then shifts left and arithmetic shifts right to introduce a sign
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
92 /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
94 /// Shuffles the low lanes of the operand into place and blends zeros into
95 /// the remaining lanes, finally bitcasting to the proper type.
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
98 /// \brief Expand bswap of vectors into a shuffle if legal.
99 SDValue ExpandBSWAP(SDValue Op);
101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
102 /// supported by the target.
103 SDValue ExpandVSELECT(SDValue Op);
104 SDValue ExpandSELECT(SDValue Op);
105 SDValue ExpandLoad(SDValue Op);
106 SDValue ExpandStore(SDValue Op);
107 SDValue ExpandFNEG(SDValue Op);
109 /// \brief Implements vector promotion.
111 /// This is essentially just bitcasting the operands to a different type and
112 /// bitcasting the result back to the original type.
113 SDValue Promote(SDValue Op);
115 /// \brief Implements [SU]INT_TO_FP vector promotion.
117 /// This is a [zs]ext of the input operand to the next size up.
118 SDValue PromoteINT_TO_FP(SDValue Op);
120 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
122 /// It is promoted to the next size up integer type. The result is then
123 /// truncated back to the original type.
124 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
127 /// \brief Begin legalizer the vector operations in the DAG.
129 VectorLegalizer(SelectionDAG& dag) :
130 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
133 bool VectorLegalizer::Run() {
134 // Before we start legalizing vector nodes, check if there are any vectors.
135 bool HasVectors = false;
136 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
137 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
138 // Check if the values of the nodes contain vectors. We don't need to check
139 // the operands because we are going to check their values at some point.
140 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
142 HasVectors |= J->isVector();
144 // If we found a vector node we can start the legalization.
149 // If this basic block has no vectors then no need to legalize vectors.
153 // The legalize process is inherently a bottom-up recursive process (users
154 // legalize their uses before themselves). Given infinite stack space, we
155 // could just start legalizing on the root and traverse the whole graph. In
156 // practice however, this causes us to run out of stack space on large basic
157 // blocks. To avoid this problem, compute an ordering of the nodes where each
158 // node is only legalized after all of its operands are legalized.
159 DAG.AssignTopologicalOrder();
160 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
161 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
162 LegalizeOp(SDValue(I, 0));
164 // Finally, it's possible the root changed. Get the new root.
165 SDValue OldRoot = DAG.getRoot();
166 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
167 DAG.setRoot(LegalizedNodes[OldRoot]);
169 LegalizedNodes.clear();
171 // Remove dead nodes now.
172 DAG.RemoveDeadNodes();
177 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
178 // Generic legalization: just pass the operand through.
179 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
180 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
181 return Result.getValue(Op.getResNo());
184 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
185 // Note that LegalizeOp may be reentered even from single-use nodes, which
186 // means that we always must cache transformed nodes.
187 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
188 if (I != LegalizedNodes.end()) return I->second;
190 SDNode* Node = Op.getNode();
192 // Legalize the operands
193 SmallVector<SDValue, 8> Ops;
194 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
195 Ops.push_back(LegalizeOp(Node->getOperand(i)));
197 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
199 if (Op.getOpcode() == ISD::LOAD) {
200 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
201 ISD::LoadExtType ExtType = LD->getExtensionType();
202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
203 switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
204 LD->getMemoryVT())) {
205 default: llvm_unreachable("This action is not supported yet!");
206 case TargetLowering::Legal:
207 return TranslateLegalizeResults(Op, Result);
208 case TargetLowering::Custom:
209 if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
211 if (Lowered->getNumValues() != Op->getNumValues()) {
212 // This expanded to something other than the load. Assume the
213 // lowering code took care of any chain values, and just handle the
215 assert(Result.getValue(1).use_empty() &&
216 "There are still live users of the old chain!");
217 return LegalizeOp(Lowered);
219 return TranslateLegalizeResults(Op, Lowered);
222 case TargetLowering::Expand:
224 return LegalizeOp(ExpandLoad(Op));
226 } else if (Op.getOpcode() == ISD::STORE) {
227 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
228 EVT StVT = ST->getMemoryVT();
229 MVT ValVT = ST->getValue().getSimpleValueType();
230 if (StVT.isVector() && ST->isTruncatingStore())
231 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
232 default: llvm_unreachable("This action is not supported yet!");
233 case TargetLowering::Legal:
234 return TranslateLegalizeResults(Op, Result);
235 case TargetLowering::Custom:
237 return TranslateLegalizeResults(Op, TLI.LowerOperation(Result, DAG));
238 case TargetLowering::Expand:
240 return LegalizeOp(ExpandStore(Op));
244 bool HasVectorValue = false;
245 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
248 HasVectorValue |= J->isVector();
250 return TranslateLegalizeResults(Op, Result);
253 switch (Op.getOpcode()) {
255 return TranslateLegalizeResults(Op, Result);
279 case ISD::CTLZ_ZERO_UNDEF:
280 case ISD::CTTZ_ZERO_UNDEF:
286 case ISD::ZERO_EXTEND:
287 case ISD::ANY_EXTEND:
289 case ISD::SIGN_EXTEND:
290 case ISD::FP_TO_SINT:
291 case ISD::FP_TO_UINT:
310 case ISD::FNEARBYINT:
316 case ISD::SIGN_EXTEND_INREG:
317 case ISD::ANY_EXTEND_VECTOR_INREG:
318 case ISD::SIGN_EXTEND_VECTOR_INREG:
319 case ISD::ZERO_EXTEND_VECTOR_INREG:
320 QueryType = Node->getValueType(0);
322 case ISD::FP_ROUND_INREG:
323 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
325 case ISD::SINT_TO_FP:
326 case ISD::UINT_TO_FP:
327 QueryType = Node->getOperand(0).getValueType();
331 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
332 case TargetLowering::Promote:
333 Result = Promote(Op);
336 case TargetLowering::Legal:
338 case TargetLowering::Custom: {
339 SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
340 if (Tmp1.getNode()) {
346 case TargetLowering::Expand:
350 // Make sure that the generated code is itself legal.
352 Result = LegalizeOp(Result);
356 // Note that LegalizeOp may be reentered even from single-use nodes, which
357 // means that we always must cache transformed nodes.
358 AddLegalizedOperand(Op, Result);
362 SDValue VectorLegalizer::Promote(SDValue Op) {
363 // For a few operations there is a specific concept for promotion based on
364 // the operand's type.
365 switch (Op.getOpcode()) {
366 case ISD::SINT_TO_FP:
367 case ISD::UINT_TO_FP:
368 // "Promote" the operation by extending the operand.
369 return PromoteINT_TO_FP(Op);
370 case ISD::FP_TO_UINT:
371 case ISD::FP_TO_SINT:
372 // Promote the operation by extending the operand.
373 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
376 // There are currently two cases of vector promotion:
377 // 1) Bitcasting a vector of integers to a different type to a vector of the
378 // same overall length. For example, x86 promotes ISD::AND on v2i32 to v1i64.
379 // 2) Extending a vector of floats to a vector of the same number oflarger
380 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
381 MVT VT = Op.getSimpleValueType();
382 assert(Op.getNode()->getNumValues() == 1 &&
383 "Can't promote a vector with multiple results!");
384 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
386 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
388 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
389 if (Op.getOperand(j).getValueType().isVector())
392 .getVectorElementType()
394 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
396 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
398 Operands[j] = Op.getOperand(j);
401 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands);
402 if (VT.isFloatingPoint() ||
403 (VT.isVector() && VT.getVectorElementType().isFloatingPoint()))
404 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0));
406 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
409 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
410 // INT_TO_FP operations may require the input operand be promoted even
411 // when the type is otherwise legal.
412 EVT VT = Op.getOperand(0).getValueType();
413 assert(Op.getNode()->getNumValues() == 1 &&
414 "Can't promote a vector with multiple results!");
416 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
417 // by widening the vector w/ the same element width and twice the number
418 // of elements. We want the other way around, the same number of elements,
419 // each twice the width.
421 // Increase the bitwidth of the element to the next pow-of-two
422 // (which is greater than 8 bits).
424 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
425 assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
427 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
429 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
431 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
432 if (Op.getOperand(j).getValueType().isVector())
433 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
435 Operands[j] = Op.getOperand(j);
438 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
441 // For FP_TO_INT we promote the result type to a vector type with wider
442 // elements and then truncate the result. This is different from the default
443 // PromoteVector which uses bitcast to promote thus assumning that the
444 // promoted vector type has the same overall size.
445 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
446 assert(Op.getNode()->getNumValues() == 1 &&
447 "Can't promote a vector with multiple results!");
448 EVT VT = Op.getValueType();
453 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
454 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
455 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
456 NewOpc = ISD::FP_TO_SINT;
459 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
460 NewOpc = ISD::FP_TO_UINT;
466 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
467 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
471 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
473 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
474 SDValue Chain = LD->getChain();
475 SDValue BasePTR = LD->getBasePtr();
476 EVT SrcVT = LD->getMemoryVT();
477 ISD::LoadExtType ExtType = LD->getExtensionType();
479 SmallVector<SDValue, 8> Vals;
480 SmallVector<SDValue, 8> LoadChains;
481 unsigned NumElem = SrcVT.getVectorNumElements();
483 EVT SrcEltVT = SrcVT.getScalarType();
484 EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
486 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
487 // When elements in a vector is not byte-addressable, we cannot directly
488 // load each element by advancing pointer, which could only address bytes.
489 // Instead, we load all significant words, mask bits off, and concatenate
490 // them to form each element. Finally, they are extended to destination
491 // scalar type to build the destination vector.
492 EVT WideVT = TLI.getPointerTy();
494 assert(WideVT.isRound() &&
495 "Could not handle the sophisticated case when the widest integer is"
497 assert(WideVT.bitsGE(SrcEltVT) &&
498 "Type is not legalized?");
500 unsigned WideBytes = WideVT.getStoreSize();
502 unsigned RemainingBytes = SrcVT.getStoreSize();
503 SmallVector<SDValue, 8> LoadVals;
505 while (RemainingBytes > 0) {
507 unsigned LoadBytes = WideBytes;
509 if (RemainingBytes >= LoadBytes) {
510 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
511 LD->getPointerInfo().getWithOffset(Offset),
512 LD->isVolatile(), LD->isNonTemporal(),
513 LD->isInvariant(), LD->getAlignment(),
517 while (RemainingBytes < LoadBytes) {
518 LoadBytes >>= 1; // Reduce the load size by half.
519 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
521 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
522 LD->getPointerInfo().getWithOffset(Offset),
523 LoadVT, LD->isVolatile(),
524 LD->isNonTemporal(), LD->isInvariant(),
525 LD->getAlignment(), LD->getAAInfo());
528 RemainingBytes -= LoadBytes;
530 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
531 DAG.getConstant(LoadBytes, BasePTR.getValueType()));
533 LoadVals.push_back(ScalarLoad.getValue(0));
534 LoadChains.push_back(ScalarLoad.getValue(1));
537 // Extract bits, pack and extend/trunc them into destination type.
538 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
539 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, WideVT);
541 unsigned BitOffset = 0;
542 unsigned WideIdx = 0;
543 unsigned WideBits = WideVT.getSizeInBits();
545 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
546 SDValue Lo, Hi, ShAmt;
548 if (BitOffset < WideBits) {
549 ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
550 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
551 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
554 BitOffset += SrcEltBits;
555 if (BitOffset >= WideBits) {
559 ShAmt = DAG.getConstant(SrcEltBits - Offset,
560 TLI.getShiftAmountTy(WideVT));
561 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
562 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
567 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
570 default: llvm_unreachable("Unknown extended-load op!");
572 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
575 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
578 ShAmt = DAG.getConstant(WideBits - SrcEltBits,
579 TLI.getShiftAmountTy(WideVT));
580 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
581 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
582 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
588 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
590 for (unsigned Idx=0; Idx<NumElem; Idx++) {
591 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
592 Op.getNode()->getValueType(0).getScalarType(),
593 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
594 SrcVT.getScalarType(),
595 LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(),
596 LD->getAlignment(), LD->getAAInfo());
598 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
599 DAG.getConstant(Stride, BasePTR.getValueType()));
601 Vals.push_back(ScalarLoad.getValue(0));
602 LoadChains.push_back(ScalarLoad.getValue(1));
606 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
607 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
608 Op.getNode()->getValueType(0), Vals);
610 AddLegalizedOperand(Op.getValue(0), Value);
611 AddLegalizedOperand(Op.getValue(1), NewChain);
613 return (Op.getResNo() ? NewChain : Value);
616 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
618 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
619 SDValue Chain = ST->getChain();
620 SDValue BasePTR = ST->getBasePtr();
621 SDValue Value = ST->getValue();
622 EVT StVT = ST->getMemoryVT();
624 unsigned Alignment = ST->getAlignment();
625 bool isVolatile = ST->isVolatile();
626 bool isNonTemporal = ST->isNonTemporal();
627 AAMDNodes AAInfo = ST->getAAInfo();
629 unsigned NumElem = StVT.getVectorNumElements();
630 // The type of the data we want to save
631 EVT RegVT = Value.getValueType();
632 EVT RegSclVT = RegVT.getScalarType();
633 // The type of data as saved in memory.
634 EVT MemSclVT = StVT.getScalarType();
636 // Cast floats into integers
637 unsigned ScalarSize = MemSclVT.getSizeInBits();
639 // Round odd types to the next pow of two.
640 if (!isPowerOf2_32(ScalarSize))
641 ScalarSize = NextPowerOf2(ScalarSize);
643 // Store Stride in bytes
644 unsigned Stride = ScalarSize/8;
645 // Extract each of the elements from the original vector
646 // and save them into memory individually.
647 SmallVector<SDValue, 8> Stores;
648 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
649 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
650 RegSclVT, Value, DAG.getConstant(Idx, TLI.getVectorIdxTy()));
652 // This scalar TruncStore may be illegal, but we legalize it later.
653 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
654 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
655 isVolatile, isNonTemporal, Alignment, AAInfo);
657 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
658 DAG.getConstant(Stride, BasePTR.getValueType()));
660 Stores.push_back(Store);
662 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
663 AddLegalizedOperand(Op, TF);
667 SDValue VectorLegalizer::Expand(SDValue Op) {
668 switch (Op->getOpcode()) {
669 case ISD::SIGN_EXTEND_INREG:
670 return ExpandSEXTINREG(Op);
671 case ISD::ANY_EXTEND_VECTOR_INREG:
672 return ExpandANY_EXTEND_VECTOR_INREG(Op);
673 case ISD::SIGN_EXTEND_VECTOR_INREG:
674 return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
675 case ISD::ZERO_EXTEND_VECTOR_INREG:
676 return ExpandZERO_EXTEND_VECTOR_INREG(Op);
678 return ExpandBSWAP(Op);
680 return ExpandVSELECT(Op);
682 return ExpandSELECT(Op);
683 case ISD::UINT_TO_FP:
684 return ExpandUINT_TO_FLOAT(Op);
686 return ExpandFNEG(Op);
688 return UnrollVSETCC(Op);
690 return DAG.UnrollVectorOp(Op.getNode());
694 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
695 // Lower a select instruction where the condition is a scalar and the
696 // operands are vectors. Lower this select to VSELECT and implement it
697 // using XOR AND OR. The selector bit is broadcasted.
698 EVT VT = Op.getValueType();
701 SDValue Mask = Op.getOperand(0);
702 SDValue Op1 = Op.getOperand(1);
703 SDValue Op2 = Op.getOperand(2);
705 assert(VT.isVector() && !Mask.getValueType().isVector()
706 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
708 unsigned NumElem = VT.getVectorNumElements();
710 // If we can't even use the basic vector operations of
711 // AND,OR,XOR, we will have to scalarize the op.
712 // Notice that the operation may be 'promoted' which means that it is
713 // 'bitcasted' to another type which is handled.
714 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
715 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
716 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
717 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
718 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
719 return DAG.UnrollVectorOp(Op.getNode());
721 // Generate a mask operand.
722 EVT MaskTy = VT.changeVectorElementTypeToInteger();
724 // What is the size of each element in the vector mask.
725 EVT BitTy = MaskTy.getScalarType();
727 Mask = DAG.getSelect(DL, BitTy, Mask,
728 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy),
729 DAG.getConstant(0, BitTy));
731 // Broadcast the mask so that the entire vector is all-one or all zero.
732 SmallVector<SDValue, 8> Ops(NumElem, Mask);
733 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
735 // Bitcast the operands to be the same type as the mask.
736 // This is needed when we select between FP types because
737 // the mask is a vector of integers.
738 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
739 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
741 SDValue AllOnes = DAG.getConstant(
742 APInt::getAllOnesValue(BitTy.getSizeInBits()), MaskTy);
743 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
745 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
746 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
747 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
748 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
751 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
752 EVT VT = Op.getValueType();
754 // Make sure that the SRA and SHL instructions are available.
755 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
756 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
757 return DAG.UnrollVectorOp(Op.getNode());
760 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
762 unsigned BW = VT.getScalarType().getSizeInBits();
763 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
764 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT);
766 Op = Op.getOperand(0);
767 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
768 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
771 // Generically expand a vector anyext in register to a shuffle of the relevant
772 // lanes into the appropriate locations, with other lanes left undef.
773 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
775 EVT VT = Op.getValueType();
776 int NumElements = VT.getVectorNumElements();
777 SDValue Src = Op.getOperand(0);
778 EVT SrcVT = Src.getValueType();
779 int NumSrcElements = SrcVT.getVectorNumElements();
781 // Build a base mask of undef shuffles.
782 SmallVector<int, 16> ShuffleMask;
783 ShuffleMask.resize(NumSrcElements, -1);
785 // Place the extended lanes into the correct locations.
786 int ExtLaneScale = NumSrcElements / NumElements;
787 int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0;
788 for (int i = 0; i < NumElements; ++i)
789 ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
792 ISD::BITCAST, DL, VT,
793 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
796 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
798 EVT VT = Op.getValueType();
799 SDValue Src = Op.getOperand(0);
800 EVT SrcVT = Src.getValueType();
802 // First build an any-extend node which can be legalized above when we
803 // recurse through it.
804 Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
806 // Now we need sign extend. Do this by shifting the elements. Even if these
807 // aren't legal operations, they have a better chance of being legalized
808 // without full scalarization than the sign extension does.
809 unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
810 unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
811 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, VT);
812 return DAG.getNode(ISD::SRA, DL, VT,
813 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
817 // Generically expand a vector zext in register to a shuffle of the relevant
818 // lanes into the appropriate locations, a blend of zero into the high bits,
819 // and a bitcast to the wider element type.
820 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
822 EVT VT = Op.getValueType();
823 int NumElements = VT.getVectorNumElements();
824 SDValue Src = Op.getOperand(0);
825 EVT SrcVT = Src.getValueType();
826 int NumSrcElements = SrcVT.getVectorNumElements();
828 // Build up a zero vector to blend into this one.
829 EVT SrcScalarVT = SrcVT.getScalarType();
830 SDValue ScalarZero = DAG.getTargetConstant(0, SrcScalarVT);
831 SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero);
832 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands);
834 // Shuffle the incoming lanes into the correct position, and pull all other
835 // lanes from the zero vector.
836 SmallVector<int, 16> ShuffleMask;
837 ShuffleMask.reserve(NumSrcElements);
838 for (int i = 0; i < NumSrcElements; ++i)
839 ShuffleMask.push_back(i);
841 int ExtLaneScale = NumSrcElements / NumElements;
842 int EndianOffset = TLI.isBigEndian() ? ExtLaneScale - 1 : 0;
843 for (int i = 0; i < NumElements; ++i)
844 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
846 return DAG.getNode(ISD::BITCAST, DL, VT,
847 DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
850 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
851 EVT VT = Op.getValueType();
853 // Generate a byte wise shuffle mask for the BSWAP.
854 SmallVector<int, 16> ShuffleMask;
855 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
856 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
857 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
858 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
860 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
862 // Only emit a shuffle if the mask is legal.
863 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
864 return DAG.UnrollVectorOp(Op.getNode());
867 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
868 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
870 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
873 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
874 // Implement VSELECT in terms of XOR, AND, OR
875 // on platforms which do not support blend natively.
878 SDValue Mask = Op.getOperand(0);
879 SDValue Op1 = Op.getOperand(1);
880 SDValue Op2 = Op.getOperand(2);
882 EVT VT = Mask.getValueType();
884 // If we can't even use the basic vector operations of
885 // AND,OR,XOR, we will have to scalarize the op.
886 // Notice that the operation may be 'promoted' which means that it is
887 // 'bitcasted' to another type which is handled.
888 // This operation also isn't safe with AND, OR, XOR when the boolean
889 // type is 0/1 as we need an all ones vector constant to mask with.
890 // FIXME: Sign extend 1 to all ones if thats legal on the target.
891 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
892 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
893 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
894 TLI.getBooleanContents(Op1.getValueType()) !=
895 TargetLowering::ZeroOrNegativeOneBooleanContent)
896 return DAG.UnrollVectorOp(Op.getNode());
898 // If the mask and the type are different sizes, unroll the vector op. This
899 // can occur when getSetCCResultType returns something that is different in
900 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
901 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
902 return DAG.UnrollVectorOp(Op.getNode());
904 // Bitcast the operands to be the same type as the mask.
905 // This is needed when we select between FP types because
906 // the mask is a vector of integers.
907 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
908 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
910 SDValue AllOnes = DAG.getConstant(
911 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT);
912 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
914 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
915 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
916 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
917 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
920 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
921 EVT VT = Op.getOperand(0).getValueType();
924 // Make sure that the SINT_TO_FP and SRL instructions are available.
925 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
926 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
927 return DAG.UnrollVectorOp(Op.getNode());
929 EVT SVT = VT.getScalarType();
930 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
931 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
933 unsigned BW = SVT.getSizeInBits();
934 SDValue HalfWord = DAG.getConstant(BW/2, VT);
936 // Constants to clear the upper part of the word.
937 // Notice that we can also use SHL+SHR, but using a constant is slightly
939 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
940 SDValue HalfWordMask = DAG.getConstant(HWMask, VT);
942 // Two to the power of half-word-size.
943 SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType());
945 // Clear upper part of LO, lower HI
946 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
947 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
949 // Convert hi and lo to floats
950 // Convert the hi part back to the upper values
951 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
952 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
953 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
955 // Add the two halves
956 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
960 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
961 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
962 SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType());
963 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
964 Zero, Op.getOperand(0));
966 return DAG.UnrollVectorOp(Op.getNode());
969 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
970 EVT VT = Op.getValueType();
971 unsigned NumElems = VT.getVectorNumElements();
972 EVT EltVT = VT.getVectorElementType();
973 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
974 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
976 SmallVector<SDValue, 8> Ops(NumElems);
977 for (unsigned i = 0; i < NumElems; ++i) {
978 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
979 DAG.getConstant(i, TLI.getVectorIdxTy()));
980 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
981 DAG.getConstant(i, TLI.getVectorIdxTy()));
982 Ops[i] = DAG.getNode(ISD::SETCC, dl,
983 TLI.getSetCCResultType(*DAG.getContext(), TmpEltVT),
984 LHSElem, RHSElem, CC);
985 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
986 DAG.getConstant(APInt::getAllOnesValue
987 (EltVT.getSizeInBits()), EltVT),
988 DAG.getConstant(0, EltVT));
990 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
995 bool SelectionDAG::LegalizeVectors() {
996 return VectorLegalizer(*this).Run();