1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::LegalizeVectors method.
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/Target/TargetLowering.h"
35 class VectorLegalizer {
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
40 /// For nodes that are of legal width, and that have more than one use, this
41 /// map indicates what regularized operand to use. This allows us to avoid
42 /// legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
45 /// \brief Adds a node to the translation cache.
46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
50 LegalizedNodes.insert(std::make_pair(To, To));
53 /// \brief Legalizes the given node.
54 SDValue LegalizeOp(SDValue Op);
56 /// \brief Assuming the node is legal, "legalize" the results.
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
59 /// \brief Implements unrolling a VSETCC.
60 SDValue UnrollVSETCC(SDValue Op);
62 /// \brief Implement expand-based legalization of vector operations.
64 /// This is just a high-level routine to dispatch to specific code paths for
65 /// operations to legalize them.
66 SDValue Expand(SDValue Op);
68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
71 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
72 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
76 SDValue ExpandSEXTINREG(SDValue Op);
78 /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
80 /// Shuffles the low lanes of the operand into place and bitcasts to the proper
81 /// type. The contents of the bits in the extended part of each element are
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
85 /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
87 /// Shuffles the low lanes of the operand into place, bitcasts to the proper
88 /// type, then shifts left and arithmetic shifts right to introduce a sign
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
92 /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
94 /// Shuffles the low lanes of the operand into place and blends zeros into
95 /// the remaining lanes, finally bitcasting to the proper type.
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
98 /// \brief Expand bswap of vectors into a shuffle if legal.
99 SDValue ExpandBSWAP(SDValue Op);
101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
102 /// supported by the target.
103 SDValue ExpandVSELECT(SDValue Op);
104 SDValue ExpandSELECT(SDValue Op);
105 SDValue ExpandLoad(SDValue Op);
106 SDValue ExpandStore(SDValue Op);
107 SDValue ExpandFNEG(SDValue Op);
108 SDValue ExpandBITREVERSE(SDValue Op);
109 SDValue ExpandCTLZ_CTTZ_ZERO_UNDEF(SDValue Op);
111 /// \brief Implements vector promotion.
113 /// This is essentially just bitcasting the operands to a different type and
114 /// bitcasting the result back to the original type.
115 SDValue Promote(SDValue Op);
117 /// \brief Implements [SU]INT_TO_FP vector promotion.
119 /// This is a [zs]ext of the input operand to the next size up.
120 SDValue PromoteINT_TO_FP(SDValue Op);
122 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
124 /// It is promoted to the next size up integer type. The result is then
125 /// truncated back to the original type.
126 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
129 /// \brief Begin legalizer the vector operations in the DAG.
131 VectorLegalizer(SelectionDAG& dag) :
132 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
135 bool VectorLegalizer::Run() {
136 // Before we start legalizing vector nodes, check if there are any vectors.
137 bool HasVectors = false;
138 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
139 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
140 // Check if the values of the nodes contain vectors. We don't need to check
141 // the operands because we are going to check their values at some point.
142 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
144 HasVectors |= J->isVector();
146 // If we found a vector node we can start the legalization.
151 // If this basic block has no vectors then no need to legalize vectors.
155 // The legalize process is inherently a bottom-up recursive process (users
156 // legalize their uses before themselves). Given infinite stack space, we
157 // could just start legalizing on the root and traverse the whole graph. In
158 // practice however, this causes us to run out of stack space on large basic
159 // blocks. To avoid this problem, compute an ordering of the nodes where each
160 // node is only legalized after all of its operands are legalized.
161 DAG.AssignTopologicalOrder();
162 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
163 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
164 LegalizeOp(SDValue(&*I, 0));
166 // Finally, it's possible the root changed. Get the new root.
167 SDValue OldRoot = DAG.getRoot();
168 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
169 DAG.setRoot(LegalizedNodes[OldRoot]);
171 LegalizedNodes.clear();
173 // Remove dead nodes now.
174 DAG.RemoveDeadNodes();
179 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
180 // Generic legalization: just pass the operand through.
181 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
182 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
183 return Result.getValue(Op.getResNo());
186 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
187 // Note that LegalizeOp may be reentered even from single-use nodes, which
188 // means that we always must cache transformed nodes.
189 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
190 if (I != LegalizedNodes.end()) return I->second;
192 SDNode* Node = Op.getNode();
194 // Legalize the operands
195 SmallVector<SDValue, 8> Ops;
196 for (const SDValue &Op : Node->op_values())
197 Ops.push_back(LegalizeOp(Op));
199 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
201 bool HasVectorValue = false;
202 if (Op.getOpcode() == ISD::LOAD) {
203 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
204 ISD::LoadExtType ExtType = LD->getExtensionType();
205 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
206 switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
207 LD->getMemoryVT())) {
208 default: llvm_unreachable("This action is not supported yet!");
209 case TargetLowering::Legal:
210 return TranslateLegalizeResults(Op, Result);
211 case TargetLowering::Custom:
212 if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
213 if (Lowered == Result)
214 return TranslateLegalizeResults(Op, Lowered);
216 if (Lowered->getNumValues() != Op->getNumValues()) {
217 // This expanded to something other than the load. Assume the
218 // lowering code took care of any chain values, and just handle the
220 assert(Result.getValue(1).use_empty() &&
221 "There are still live users of the old chain!");
222 return LegalizeOp(Lowered);
224 return TranslateLegalizeResults(Op, Lowered);
226 case TargetLowering::Expand:
228 return LegalizeOp(ExpandLoad(Op));
230 } else if (Op.getOpcode() == ISD::STORE) {
231 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
232 EVT StVT = ST->getMemoryVT();
233 MVT ValVT = ST->getValue().getSimpleValueType();
234 if (StVT.isVector() && ST->isTruncatingStore())
235 switch (TLI.getTruncStoreAction(ValVT, StVT)) {
236 default: llvm_unreachable("This action is not supported yet!");
237 case TargetLowering::Legal:
238 return TranslateLegalizeResults(Op, Result);
239 case TargetLowering::Custom: {
240 SDValue Lowered = TLI.LowerOperation(Result, DAG);
241 Changed = Lowered != Result;
242 return TranslateLegalizeResults(Op, Lowered);
244 case TargetLowering::Expand:
246 return LegalizeOp(ExpandStore(Op));
248 } else if (Op.getOpcode() == ISD::MSCATTER || Op.getOpcode() == ISD::MSTORE)
249 HasVectorValue = true;
251 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
254 HasVectorValue |= J->isVector();
256 return TranslateLegalizeResults(Op, Result);
259 switch (Op.getOpcode()) {
261 return TranslateLegalizeResults(Op, Result);
285 case ISD::BITREVERSE:
288 case ISD::CTLZ_ZERO_UNDEF:
289 case ISD::CTTZ_ZERO_UNDEF:
295 case ISD::ZERO_EXTEND:
296 case ISD::ANY_EXTEND:
298 case ISD::SIGN_EXTEND:
299 case ISD::FP_TO_SINT:
300 case ISD::FP_TO_UINT:
321 case ISD::FNEARBYINT:
327 case ISD::SIGN_EXTEND_INREG:
328 case ISD::ANY_EXTEND_VECTOR_INREG:
329 case ISD::SIGN_EXTEND_VECTOR_INREG:
330 case ISD::ZERO_EXTEND_VECTOR_INREG:
335 QueryType = Node->getValueType(0);
337 case ISD::FP_ROUND_INREG:
338 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
340 case ISD::SINT_TO_FP:
341 case ISD::UINT_TO_FP:
342 QueryType = Node->getOperand(0).getValueType();
345 QueryType = cast<MaskedScatterSDNode>(Node)->getValue().getValueType();
348 QueryType = cast<MaskedStoreSDNode>(Node)->getValue().getValueType();
352 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
353 default: llvm_unreachable("This action is not supported yet!");
354 case TargetLowering::Promote:
355 Result = Promote(Op);
358 case TargetLowering::Legal:
360 case TargetLowering::Custom: {
361 SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
362 if (Tmp1.getNode()) {
368 case TargetLowering::Expand:
372 // Make sure that the generated code is itself legal.
374 Result = LegalizeOp(Result);
378 // Note that LegalizeOp may be reentered even from single-use nodes, which
379 // means that we always must cache transformed nodes.
380 AddLegalizedOperand(Op, Result);
384 SDValue VectorLegalizer::Promote(SDValue Op) {
385 // For a few operations there is a specific concept for promotion based on
386 // the operand's type.
387 switch (Op.getOpcode()) {
388 case ISD::SINT_TO_FP:
389 case ISD::UINT_TO_FP:
390 // "Promote" the operation by extending the operand.
391 return PromoteINT_TO_FP(Op);
392 case ISD::FP_TO_UINT:
393 case ISD::FP_TO_SINT:
394 // Promote the operation by extending the operand.
395 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
398 // There are currently two cases of vector promotion:
399 // 1) Bitcasting a vector of integers to a different type to a vector of the
400 // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
401 // 2) Extending a vector of floats to a vector of the same number of larger
402 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
403 MVT VT = Op.getSimpleValueType();
404 assert(Op.getNode()->getNumValues() == 1 &&
405 "Can't promote a vector with multiple results!");
406 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
408 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
410 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
411 if (Op.getOperand(j).getValueType().isVector())
414 .getVectorElementType()
415 .isFloatingPoint() &&
416 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
417 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
419 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
421 Operands[j] = Op.getOperand(j);
424 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
425 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
426 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
427 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
428 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
430 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
433 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
434 // INT_TO_FP operations may require the input operand be promoted even
435 // when the type is otherwise legal.
436 EVT VT = Op.getOperand(0).getValueType();
437 assert(Op.getNode()->getNumValues() == 1 &&
438 "Can't promote a vector with multiple results!");
440 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
441 // by widening the vector w/ the same element width and twice the number
442 // of elements. We want the other way around, the same number of elements,
443 // each twice the width.
445 // Increase the bitwidth of the element to the next pow-of-two
446 // (which is greater than 8 bits).
448 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
449 assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
451 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
453 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
455 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
456 if (Op.getOperand(j).getValueType().isVector())
457 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
459 Operands[j] = Op.getOperand(j);
462 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
465 // For FP_TO_INT we promote the result type to a vector type with wider
466 // elements and then truncate the result. This is different from the default
467 // PromoteVector which uses bitcast to promote thus assumning that the
468 // promoted vector type has the same overall size.
469 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
470 assert(Op.getNode()->getNumValues() == 1 &&
471 "Can't promote a vector with multiple results!");
472 EVT VT = Op.getValueType();
477 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
478 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
479 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
480 NewOpc = ISD::FP_TO_SINT;
483 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
484 NewOpc = ISD::FP_TO_UINT;
490 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
491 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
495 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
497 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
498 SDValue Chain = LD->getChain();
499 SDValue BasePTR = LD->getBasePtr();
500 EVT SrcVT = LD->getMemoryVT();
501 ISD::LoadExtType ExtType = LD->getExtensionType();
503 SmallVector<SDValue, 8> Vals;
504 SmallVector<SDValue, 8> LoadChains;
505 unsigned NumElem = SrcVT.getVectorNumElements();
507 EVT SrcEltVT = SrcVT.getScalarType();
508 EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
510 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
511 // When elements in a vector is not byte-addressable, we cannot directly
512 // load each element by advancing pointer, which could only address bytes.
513 // Instead, we load all significant words, mask bits off, and concatenate
514 // them to form each element. Finally, they are extended to destination
515 // scalar type to build the destination vector.
516 EVT WideVT = TLI.getPointerTy(DAG.getDataLayout());
518 assert(WideVT.isRound() &&
519 "Could not handle the sophisticated case when the widest integer is"
521 assert(WideVT.bitsGE(SrcEltVT) &&
522 "Type is not legalized?");
524 unsigned WideBytes = WideVT.getStoreSize();
526 unsigned RemainingBytes = SrcVT.getStoreSize();
527 SmallVector<SDValue, 8> LoadVals;
529 while (RemainingBytes > 0) {
531 unsigned LoadBytes = WideBytes;
533 if (RemainingBytes >= LoadBytes) {
534 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
535 LD->getPointerInfo().getWithOffset(Offset),
536 LD->isVolatile(), LD->isNonTemporal(),
538 MinAlign(LD->getAlignment(), Offset),
542 while (RemainingBytes < LoadBytes) {
543 LoadBytes >>= 1; // Reduce the load size by half.
544 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
546 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
547 LD->getPointerInfo().getWithOffset(Offset),
548 LoadVT, LD->isVolatile(),
549 LD->isNonTemporal(), LD->isInvariant(),
550 MinAlign(LD->getAlignment(), Offset),
554 RemainingBytes -= LoadBytes;
556 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
557 DAG.getConstant(LoadBytes, dl,
558 BasePTR.getValueType()));
560 LoadVals.push_back(ScalarLoad.getValue(0));
561 LoadChains.push_back(ScalarLoad.getValue(1));
564 // Extract bits, pack and extend/trunc them into destination type.
565 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
566 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT);
568 unsigned BitOffset = 0;
569 unsigned WideIdx = 0;
570 unsigned WideBits = WideVT.getSizeInBits();
572 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
573 SDValue Lo, Hi, ShAmt;
575 if (BitOffset < WideBits) {
576 ShAmt = DAG.getConstant(
577 BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
578 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
579 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
582 BitOffset += SrcEltBits;
583 if (BitOffset >= WideBits) {
585 BitOffset -= WideBits;
587 ShAmt = DAG.getConstant(
588 SrcEltBits - BitOffset, dl,
589 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
590 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
591 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
596 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
599 default: llvm_unreachable("Unknown extended-load op!");
601 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
604 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
608 DAG.getConstant(WideBits - SrcEltBits, dl,
609 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
610 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
611 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
612 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
618 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
620 for (unsigned Idx=0; Idx<NumElem; Idx++) {
621 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
622 Op.getNode()->getValueType(0).getScalarType(),
623 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
624 SrcVT.getScalarType(),
625 LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(),
626 MinAlign(LD->getAlignment(), Idx * Stride), LD->getAAInfo());
628 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
629 DAG.getConstant(Stride, dl, BasePTR.getValueType()));
631 Vals.push_back(ScalarLoad.getValue(0));
632 LoadChains.push_back(ScalarLoad.getValue(1));
636 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
637 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
638 Op.getNode()->getValueType(0), Vals);
640 AddLegalizedOperand(Op.getValue(0), Value);
641 AddLegalizedOperand(Op.getValue(1), NewChain);
643 return (Op.getResNo() ? NewChain : Value);
646 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
648 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
649 SDValue Chain = ST->getChain();
650 SDValue BasePTR = ST->getBasePtr();
651 SDValue Value = ST->getValue();
652 EVT StVT = ST->getMemoryVT();
654 unsigned Alignment = ST->getAlignment();
655 bool isVolatile = ST->isVolatile();
656 bool isNonTemporal = ST->isNonTemporal();
657 AAMDNodes AAInfo = ST->getAAInfo();
659 unsigned NumElem = StVT.getVectorNumElements();
660 // The type of the data we want to save
661 EVT RegVT = Value.getValueType();
662 EVT RegSclVT = RegVT.getScalarType();
663 // The type of data as saved in memory.
664 EVT MemSclVT = StVT.getScalarType();
666 // Cast floats into integers
667 unsigned ScalarSize = MemSclVT.getSizeInBits();
669 // Round odd types to the next pow of two.
670 if (!isPowerOf2_32(ScalarSize))
671 ScalarSize = NextPowerOf2(ScalarSize);
673 // Store Stride in bytes
674 unsigned Stride = ScalarSize/8;
675 // Extract each of the elements from the original vector
676 // and save them into memory individually.
677 SmallVector<SDValue, 8> Stores;
678 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
679 SDValue Ex = DAG.getNode(
680 ISD::EXTRACT_VECTOR_ELT, dl, RegSclVT, Value,
681 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
683 // This scalar TruncStore may be illegal, but we legalize it later.
684 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
685 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
686 isVolatile, isNonTemporal, MinAlign(Alignment, Idx*Stride),
689 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
690 DAG.getConstant(Stride, dl, BasePTR.getValueType()));
692 Stores.push_back(Store);
694 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
695 AddLegalizedOperand(Op, TF);
699 SDValue VectorLegalizer::Expand(SDValue Op) {
700 switch (Op->getOpcode()) {
701 case ISD::SIGN_EXTEND_INREG:
702 return ExpandSEXTINREG(Op);
703 case ISD::ANY_EXTEND_VECTOR_INREG:
704 return ExpandANY_EXTEND_VECTOR_INREG(Op);
705 case ISD::SIGN_EXTEND_VECTOR_INREG:
706 return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
707 case ISD::ZERO_EXTEND_VECTOR_INREG:
708 return ExpandZERO_EXTEND_VECTOR_INREG(Op);
710 return ExpandBSWAP(Op);
712 return ExpandVSELECT(Op);
714 return ExpandSELECT(Op);
715 case ISD::UINT_TO_FP:
716 return ExpandUINT_TO_FLOAT(Op);
718 return ExpandFNEG(Op);
720 return UnrollVSETCC(Op);
721 case ISD::BITREVERSE:
722 return ExpandBITREVERSE(Op);
723 case ISD::CTLZ_ZERO_UNDEF:
724 case ISD::CTTZ_ZERO_UNDEF:
725 return ExpandCTLZ_CTTZ_ZERO_UNDEF(Op);
727 return DAG.UnrollVectorOp(Op.getNode());
731 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
732 // Lower a select instruction where the condition is a scalar and the
733 // operands are vectors. Lower this select to VSELECT and implement it
734 // using XOR AND OR. The selector bit is broadcasted.
735 EVT VT = Op.getValueType();
738 SDValue Mask = Op.getOperand(0);
739 SDValue Op1 = Op.getOperand(1);
740 SDValue Op2 = Op.getOperand(2);
742 assert(VT.isVector() && !Mask.getValueType().isVector()
743 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
745 unsigned NumElem = VT.getVectorNumElements();
747 // If we can't even use the basic vector operations of
748 // AND,OR,XOR, we will have to scalarize the op.
749 // Notice that the operation may be 'promoted' which means that it is
750 // 'bitcasted' to another type which is handled.
751 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
752 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
753 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
754 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
755 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
756 return DAG.UnrollVectorOp(Op.getNode());
758 // Generate a mask operand.
759 EVT MaskTy = VT.changeVectorElementTypeToInteger();
761 // What is the size of each element in the vector mask.
762 EVT BitTy = MaskTy.getScalarType();
764 Mask = DAG.getSelect(DL, BitTy, Mask,
765 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
767 DAG.getConstant(0, DL, BitTy));
769 // Broadcast the mask so that the entire vector is all-one or all zero.
770 SmallVector<SDValue, 8> Ops(NumElem, Mask);
771 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
773 // Bitcast the operands to be the same type as the mask.
774 // This is needed when we select between FP types because
775 // the mask is a vector of integers.
776 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
777 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
779 SDValue AllOnes = DAG.getConstant(
780 APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy);
781 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
783 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
784 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
785 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
786 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
789 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
790 EVT VT = Op.getValueType();
792 // Make sure that the SRA and SHL instructions are available.
793 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
794 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
795 return DAG.UnrollVectorOp(Op.getNode());
798 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
800 unsigned BW = VT.getScalarType().getSizeInBits();
801 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
802 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
804 Op = Op.getOperand(0);
805 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
806 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
809 // Generically expand a vector anyext in register to a shuffle of the relevant
810 // lanes into the appropriate locations, with other lanes left undef.
811 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
813 EVT VT = Op.getValueType();
814 int NumElements = VT.getVectorNumElements();
815 SDValue Src = Op.getOperand(0);
816 EVT SrcVT = Src.getValueType();
817 int NumSrcElements = SrcVT.getVectorNumElements();
819 // Build a base mask of undef shuffles.
820 SmallVector<int, 16> ShuffleMask;
821 ShuffleMask.resize(NumSrcElements, -1);
823 // Place the extended lanes into the correct locations.
824 int ExtLaneScale = NumSrcElements / NumElements;
825 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
826 for (int i = 0; i < NumElements; ++i)
827 ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
830 ISD::BITCAST, DL, VT,
831 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
834 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
836 EVT VT = Op.getValueType();
837 SDValue Src = Op.getOperand(0);
838 EVT SrcVT = Src.getValueType();
840 // First build an any-extend node which can be legalized above when we
841 // recurse through it.
842 Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
844 // Now we need sign extend. Do this by shifting the elements. Even if these
845 // aren't legal operations, they have a better chance of being legalized
846 // without full scalarization than the sign extension does.
847 unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
848 unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
849 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
850 return DAG.getNode(ISD::SRA, DL, VT,
851 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
855 // Generically expand a vector zext in register to a shuffle of the relevant
856 // lanes into the appropriate locations, a blend of zero into the high bits,
857 // and a bitcast to the wider element type.
858 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
860 EVT VT = Op.getValueType();
861 int NumElements = VT.getVectorNumElements();
862 SDValue Src = Op.getOperand(0);
863 EVT SrcVT = Src.getValueType();
864 int NumSrcElements = SrcVT.getVectorNumElements();
866 // Build up a zero vector to blend into this one.
867 EVT SrcScalarVT = SrcVT.getScalarType();
868 SDValue ScalarZero = DAG.getTargetConstant(0, DL, SrcScalarVT);
869 SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero);
870 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands);
872 // Shuffle the incoming lanes into the correct position, and pull all other
873 // lanes from the zero vector.
874 SmallVector<int, 16> ShuffleMask;
875 ShuffleMask.reserve(NumSrcElements);
876 for (int i = 0; i < NumSrcElements; ++i)
877 ShuffleMask.push_back(i);
879 int ExtLaneScale = NumSrcElements / NumElements;
880 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
881 for (int i = 0; i < NumElements; ++i)
882 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
884 return DAG.getNode(ISD::BITCAST, DL, VT,
885 DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
888 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
889 EVT VT = Op.getValueType();
891 // Generate a byte wise shuffle mask for the BSWAP.
892 SmallVector<int, 16> ShuffleMask;
893 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
894 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
895 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
896 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
898 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
900 // Only emit a shuffle if the mask is legal.
901 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
902 return DAG.UnrollVectorOp(Op.getNode());
905 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
906 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
908 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
911 SDValue VectorLegalizer::ExpandBITREVERSE(SDValue Op) {
912 EVT VT = Op.getValueType();
914 // If we have the scalar operation, it's probably cheaper to unroll it.
915 if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType()))
916 return DAG.UnrollVectorOp(Op.getNode());
918 // If we have the appropriate vector bit operations, it is better to use them
919 // than unrolling and expanding each component.
920 if (!TLI.isOperationLegalOrCustom(ISD::SHL, VT) ||
921 !TLI.isOperationLegalOrCustom(ISD::SRL, VT) ||
922 !TLI.isOperationLegalOrCustom(ISD::AND, VT) ||
923 !TLI.isOperationLegalOrCustom(ISD::OR, VT))
924 return DAG.UnrollVectorOp(Op.getNode());
926 // Let LegalizeDAG handle this later.
930 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
931 // Implement VSELECT in terms of XOR, AND, OR
932 // on platforms which do not support blend natively.
935 SDValue Mask = Op.getOperand(0);
936 SDValue Op1 = Op.getOperand(1);
937 SDValue Op2 = Op.getOperand(2);
939 EVT VT = Mask.getValueType();
941 // If we can't even use the basic vector operations of
942 // AND,OR,XOR, we will have to scalarize the op.
943 // Notice that the operation may be 'promoted' which means that it is
944 // 'bitcasted' to another type which is handled.
945 // This operation also isn't safe with AND, OR, XOR when the boolean
946 // type is 0/1 as we need an all ones vector constant to mask with.
947 // FIXME: Sign extend 1 to all ones if thats legal on the target.
948 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
949 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
950 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
951 TLI.getBooleanContents(Op1.getValueType()) !=
952 TargetLowering::ZeroOrNegativeOneBooleanContent)
953 return DAG.UnrollVectorOp(Op.getNode());
955 // If the mask and the type are different sizes, unroll the vector op. This
956 // can occur when getSetCCResultType returns something that is different in
957 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
958 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
959 return DAG.UnrollVectorOp(Op.getNode());
961 // Bitcast the operands to be the same type as the mask.
962 // This is needed when we select between FP types because
963 // the mask is a vector of integers.
964 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
965 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
967 SDValue AllOnes = DAG.getConstant(
968 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), DL, VT);
969 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
971 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
972 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
973 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
974 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
977 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
978 EVT VT = Op.getOperand(0).getValueType();
981 // Make sure that the SINT_TO_FP and SRL instructions are available.
982 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
983 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
984 return DAG.UnrollVectorOp(Op.getNode());
986 EVT SVT = VT.getScalarType();
987 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
988 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
990 unsigned BW = SVT.getSizeInBits();
991 SDValue HalfWord = DAG.getConstant(BW/2, DL, VT);
993 // Constants to clear the upper part of the word.
994 // Notice that we can also use SHL+SHR, but using a constant is slightly
996 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
997 SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
999 // Two to the power of half-word-size.
1000 SDValue TWOHW = DAG.getConstantFP(1 << (BW/2), DL, Op.getValueType());
1002 // Clear upper part of LO, lower HI
1003 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
1004 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
1006 // Convert hi and lo to floats
1007 // Convert the hi part back to the upper values
1008 // TODO: Can any fast-math-flags be set on these nodes?
1009 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
1010 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
1011 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
1013 // Add the two halves
1014 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
1018 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
1019 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
1021 SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
1022 // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
1023 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
1024 Zero, Op.getOperand(0));
1026 return DAG.UnrollVectorOp(Op.getNode());
1029 SDValue VectorLegalizer::ExpandCTLZ_CTTZ_ZERO_UNDEF(SDValue Op) {
1030 // If the non-ZERO_UNDEF version is supported we can let LegalizeDAG handle.
1031 unsigned Opc = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF ? ISD::CTLZ : ISD::CTTZ;
1032 if (TLI.isOperationLegalOrCustom(Opc, Op.getValueType()))
1035 // Otherwise go ahead and unroll.
1036 return DAG.UnrollVectorOp(Op.getNode());
1039 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
1040 EVT VT = Op.getValueType();
1041 unsigned NumElems = VT.getVectorNumElements();
1042 EVT EltVT = VT.getVectorElementType();
1043 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
1044 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
1046 SmallVector<SDValue, 8> Ops(NumElems);
1047 for (unsigned i = 0; i < NumElems; ++i) {
1048 SDValue LHSElem = DAG.getNode(
1049 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
1050 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1051 SDValue RHSElem = DAG.getNode(
1052 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
1053 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1054 Ops[i] = DAG.getNode(ISD::SETCC, dl,
1055 TLI.getSetCCResultType(DAG.getDataLayout(),
1056 *DAG.getContext(), TmpEltVT),
1057 LHSElem, RHSElem, CC);
1058 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
1059 DAG.getConstant(APInt::getAllOnesValue
1060 (EltVT.getSizeInBits()), dl, EltVT),
1061 DAG.getConstant(0, dl, EltVT));
1063 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1068 bool SelectionDAG::LegalizeVectors() {
1069 return VectorLegalizer(*this).Run();