1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::LegalizeVectors method.
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/Target/TargetLowering.h"
35 class VectorLegalizer {
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
40 /// For nodes that are of legal width, and that have more than one use, this
41 /// map indicates what regularized operand to use. This allows us to avoid
42 /// legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
45 /// \brief Adds a node to the translation cache.
46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
50 LegalizedNodes.insert(std::make_pair(To, To));
53 /// \brief Legalizes the given node.
54 SDValue LegalizeOp(SDValue Op);
56 /// \brief Assuming the node is legal, "legalize" the results.
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
59 /// \brief Implements unrolling a VSETCC.
60 SDValue UnrollVSETCC(SDValue Op);
62 /// \brief Implement expand-based legalization of vector operations.
64 /// This is just a high-level routine to dispatch to specific code paths for
65 /// operations to legalize them.
66 SDValue Expand(SDValue Op);
68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
71 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
72 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
76 SDValue ExpandSEXTINREG(SDValue Op);
78 /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
80 /// Shuffles the low lanes of the operand into place and bitcasts to the proper
81 /// type. The contents of the bits in the extended part of each element are
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
85 /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
87 /// Shuffles the low lanes of the operand into place, bitcasts to the proper
88 /// type, then shifts left and arithmetic shifts right to introduce a sign
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
92 /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
94 /// Shuffles the low lanes of the operand into place and blends zeros into
95 /// the remaining lanes, finally bitcasting to the proper type.
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
98 /// \brief Expand bswap of vectors into a shuffle if legal.
99 SDValue ExpandBSWAP(SDValue Op);
101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
102 /// supported by the target.
103 SDValue ExpandVSELECT(SDValue Op);
104 SDValue ExpandSELECT(SDValue Op);
105 SDValue ExpandLoad(SDValue Op);
106 SDValue ExpandStore(SDValue Op);
107 SDValue ExpandFNEG(SDValue Op);
108 SDValue ExpandABSDIFF(SDValue Op);
110 /// \brief Implements vector promotion.
112 /// This is essentially just bitcasting the operands to a different type and
113 /// bitcasting the result back to the original type.
114 SDValue Promote(SDValue Op);
116 /// \brief Implements [SU]INT_TO_FP vector promotion.
118 /// This is a [zs]ext of the input operand to the next size up.
119 SDValue PromoteINT_TO_FP(SDValue Op);
121 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
123 /// It is promoted to the next size up integer type. The result is then
124 /// truncated back to the original type.
125 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
128 /// \brief Begin legalizer the vector operations in the DAG.
130 VectorLegalizer(SelectionDAG& dag) :
131 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
134 bool VectorLegalizer::Run() {
135 // Before we start legalizing vector nodes, check if there are any vectors.
136 bool HasVectors = false;
137 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
138 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
139 // Check if the values of the nodes contain vectors. We don't need to check
140 // the operands because we are going to check their values at some point.
141 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
143 HasVectors |= J->isVector();
145 // If we found a vector node we can start the legalization.
150 // If this basic block has no vectors then no need to legalize vectors.
154 // The legalize process is inherently a bottom-up recursive process (users
155 // legalize their uses before themselves). Given infinite stack space, we
156 // could just start legalizing on the root and traverse the whole graph. In
157 // practice however, this causes us to run out of stack space on large basic
158 // blocks. To avoid this problem, compute an ordering of the nodes where each
159 // node is only legalized after all of its operands are legalized.
160 DAG.AssignTopologicalOrder();
161 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
162 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
163 LegalizeOp(SDValue(&*I, 0));
165 // Finally, it's possible the root changed. Get the new root.
166 SDValue OldRoot = DAG.getRoot();
167 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
168 DAG.setRoot(LegalizedNodes[OldRoot]);
170 LegalizedNodes.clear();
172 // Remove dead nodes now.
173 DAG.RemoveDeadNodes();
178 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
179 // Generic legalization: just pass the operand through.
180 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
181 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
182 return Result.getValue(Op.getResNo());
185 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
186 // Note that LegalizeOp may be reentered even from single-use nodes, which
187 // means that we always must cache transformed nodes.
188 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
189 if (I != LegalizedNodes.end()) return I->second;
191 SDNode* Node = Op.getNode();
193 // Legalize the operands
194 SmallVector<SDValue, 8> Ops;
195 for (const SDValue &Op : Node->op_values())
196 Ops.push_back(LegalizeOp(Op));
198 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
200 bool HasVectorValue = false;
201 if (Op.getOpcode() == ISD::LOAD) {
202 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
203 ISD::LoadExtType ExtType = LD->getExtensionType();
204 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
205 switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
206 LD->getMemoryVT())) {
207 default: llvm_unreachable("This action is not supported yet!");
208 case TargetLowering::Legal:
209 return TranslateLegalizeResults(Op, Result);
210 case TargetLowering::Custom:
211 if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
212 if (Lowered == Result)
213 return TranslateLegalizeResults(Op, Lowered);
215 if (Lowered->getNumValues() != Op->getNumValues()) {
216 // This expanded to something other than the load. Assume the
217 // lowering code took care of any chain values, and just handle the
219 assert(Result.getValue(1).use_empty() &&
220 "There are still live users of the old chain!");
221 return LegalizeOp(Lowered);
223 return TranslateLegalizeResults(Op, Lowered);
225 case TargetLowering::Expand:
227 return LegalizeOp(ExpandLoad(Op));
229 } else if (Op.getOpcode() == ISD::STORE) {
230 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
231 EVT StVT = ST->getMemoryVT();
232 MVT ValVT = ST->getValue().getSimpleValueType();
233 if (StVT.isVector() && ST->isTruncatingStore())
234 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
235 default: llvm_unreachable("This action is not supported yet!");
236 case TargetLowering::Legal:
237 return TranslateLegalizeResults(Op, Result);
238 case TargetLowering::Custom: {
239 SDValue Lowered = TLI.LowerOperation(Result, DAG);
240 Changed = Lowered != Result;
241 return TranslateLegalizeResults(Op, Lowered);
243 case TargetLowering::Expand:
245 return LegalizeOp(ExpandStore(Op));
247 } else if (Op.getOpcode() == ISD::MSCATTER)
248 HasVectorValue = true;
250 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
253 HasVectorValue |= J->isVector();
255 return TranslateLegalizeResults(Op, Result);
258 switch (Op.getOpcode()) {
260 return TranslateLegalizeResults(Op, Result);
286 case ISD::CTLZ_ZERO_UNDEF:
287 case ISD::CTTZ_ZERO_UNDEF:
293 case ISD::ZERO_EXTEND:
294 case ISD::ANY_EXTEND:
296 case ISD::SIGN_EXTEND:
297 case ISD::FP_TO_SINT:
298 case ISD::FP_TO_UINT:
319 case ISD::FNEARBYINT:
325 case ISD::SIGN_EXTEND_INREG:
326 case ISD::ANY_EXTEND_VECTOR_INREG:
327 case ISD::SIGN_EXTEND_VECTOR_INREG:
328 case ISD::ZERO_EXTEND_VECTOR_INREG:
335 QueryType = Node->getValueType(0);
337 case ISD::FP_ROUND_INREG:
338 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
340 case ISD::SINT_TO_FP:
341 case ISD::UINT_TO_FP:
342 QueryType = Node->getOperand(0).getValueType();
345 QueryType = cast<MaskedScatterSDNode>(Node)->getValue().getValueType();
349 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
350 default: llvm_unreachable("This action is not supported yet!");
351 case TargetLowering::Promote:
352 Result = Promote(Op);
355 case TargetLowering::Legal:
357 case TargetLowering::Custom: {
358 SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
359 if (Tmp1.getNode()) {
365 case TargetLowering::Expand:
369 // Make sure that the generated code is itself legal.
371 Result = LegalizeOp(Result);
375 // Note that LegalizeOp may be reentered even from single-use nodes, which
376 // means that we always must cache transformed nodes.
377 AddLegalizedOperand(Op, Result);
381 SDValue VectorLegalizer::Promote(SDValue Op) {
382 // For a few operations there is a specific concept for promotion based on
383 // the operand's type.
384 switch (Op.getOpcode()) {
385 case ISD::SINT_TO_FP:
386 case ISD::UINT_TO_FP:
387 // "Promote" the operation by extending the operand.
388 return PromoteINT_TO_FP(Op);
389 case ISD::FP_TO_UINT:
390 case ISD::FP_TO_SINT:
391 // Promote the operation by extending the operand.
392 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
395 // There are currently two cases of vector promotion:
396 // 1) Bitcasting a vector of integers to a different type to a vector of the
397 // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
398 // 2) Extending a vector of floats to a vector of the same number of larger
399 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
400 MVT VT = Op.getSimpleValueType();
401 assert(Op.getNode()->getNumValues() == 1 &&
402 "Can't promote a vector with multiple results!");
403 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
405 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
407 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
408 if (Op.getOperand(j).getValueType().isVector())
411 .getVectorElementType()
412 .isFloatingPoint() &&
413 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
414 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
416 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
418 Operands[j] = Op.getOperand(j);
421 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
422 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
423 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
424 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
425 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
427 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
430 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
431 // INT_TO_FP operations may require the input operand be promoted even
432 // when the type is otherwise legal.
433 EVT VT = Op.getOperand(0).getValueType();
434 assert(Op.getNode()->getNumValues() == 1 &&
435 "Can't promote a vector with multiple results!");
437 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
438 // by widening the vector w/ the same element width and twice the number
439 // of elements. We want the other way around, the same number of elements,
440 // each twice the width.
442 // Increase the bitwidth of the element to the next pow-of-two
443 // (which is greater than 8 bits).
445 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
446 assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
448 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
450 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
452 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
453 if (Op.getOperand(j).getValueType().isVector())
454 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
456 Operands[j] = Op.getOperand(j);
459 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
462 // For FP_TO_INT we promote the result type to a vector type with wider
463 // elements and then truncate the result. This is different from the default
464 // PromoteVector which uses bitcast to promote thus assumning that the
465 // promoted vector type has the same overall size.
466 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
467 assert(Op.getNode()->getNumValues() == 1 &&
468 "Can't promote a vector with multiple results!");
469 EVT VT = Op.getValueType();
474 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
475 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
476 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
477 NewOpc = ISD::FP_TO_SINT;
480 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
481 NewOpc = ISD::FP_TO_UINT;
487 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
488 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
492 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
494 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
495 SDValue Chain = LD->getChain();
496 SDValue BasePTR = LD->getBasePtr();
497 EVT SrcVT = LD->getMemoryVT();
498 ISD::LoadExtType ExtType = LD->getExtensionType();
500 SmallVector<SDValue, 8> Vals;
501 SmallVector<SDValue, 8> LoadChains;
502 unsigned NumElem = SrcVT.getVectorNumElements();
504 EVT SrcEltVT = SrcVT.getScalarType();
505 EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
507 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
508 // When elements in a vector is not byte-addressable, we cannot directly
509 // load each element by advancing pointer, which could only address bytes.
510 // Instead, we load all significant words, mask bits off, and concatenate
511 // them to form each element. Finally, they are extended to destination
512 // scalar type to build the destination vector.
513 EVT WideVT = TLI.getPointerTy(DAG.getDataLayout());
515 assert(WideVT.isRound() &&
516 "Could not handle the sophisticated case when the widest integer is"
518 assert(WideVT.bitsGE(SrcEltVT) &&
519 "Type is not legalized?");
521 unsigned WideBytes = WideVT.getStoreSize();
523 unsigned RemainingBytes = SrcVT.getStoreSize();
524 SmallVector<SDValue, 8> LoadVals;
526 while (RemainingBytes > 0) {
528 unsigned LoadBytes = WideBytes;
530 if (RemainingBytes >= LoadBytes) {
531 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
532 LD->getPointerInfo().getWithOffset(Offset),
533 LD->isVolatile(), LD->isNonTemporal(),
535 MinAlign(LD->getAlignment(), Offset),
539 while (RemainingBytes < LoadBytes) {
540 LoadBytes >>= 1; // Reduce the load size by half.
541 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
543 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
544 LD->getPointerInfo().getWithOffset(Offset),
545 LoadVT, LD->isVolatile(),
546 LD->isNonTemporal(), LD->isInvariant(),
547 MinAlign(LD->getAlignment(), Offset),
551 RemainingBytes -= LoadBytes;
553 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
554 DAG.getConstant(LoadBytes, dl,
555 BasePTR.getValueType()));
557 LoadVals.push_back(ScalarLoad.getValue(0));
558 LoadChains.push_back(ScalarLoad.getValue(1));
561 // Extract bits, pack and extend/trunc them into destination type.
562 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
563 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT);
565 unsigned BitOffset = 0;
566 unsigned WideIdx = 0;
567 unsigned WideBits = WideVT.getSizeInBits();
569 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
570 SDValue Lo, Hi, ShAmt;
572 if (BitOffset < WideBits) {
573 ShAmt = DAG.getConstant(
574 BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
575 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
576 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
579 BitOffset += SrcEltBits;
580 if (BitOffset >= WideBits) {
582 BitOffset -= WideBits;
584 ShAmt = DAG.getConstant(
585 SrcEltBits - BitOffset, dl,
586 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
587 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
588 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
593 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
596 default: llvm_unreachable("Unknown extended-load op!");
598 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
601 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
605 DAG.getConstant(WideBits - SrcEltBits, dl,
606 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
607 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
608 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
609 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
615 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
617 for (unsigned Idx=0; Idx<NumElem; Idx++) {
618 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
619 Op.getNode()->getValueType(0).getScalarType(),
620 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
621 SrcVT.getScalarType(),
622 LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(),
623 MinAlign(LD->getAlignment(), Idx * Stride), LD->getAAInfo());
625 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
626 DAG.getConstant(Stride, dl, BasePTR.getValueType()));
628 Vals.push_back(ScalarLoad.getValue(0));
629 LoadChains.push_back(ScalarLoad.getValue(1));
633 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
634 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
635 Op.getNode()->getValueType(0), Vals);
637 AddLegalizedOperand(Op.getValue(0), Value);
638 AddLegalizedOperand(Op.getValue(1), NewChain);
640 return (Op.getResNo() ? NewChain : Value);
643 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
645 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
646 SDValue Chain = ST->getChain();
647 SDValue BasePTR = ST->getBasePtr();
648 SDValue Value = ST->getValue();
649 EVT StVT = ST->getMemoryVT();
651 unsigned Alignment = ST->getAlignment();
652 bool isVolatile = ST->isVolatile();
653 bool isNonTemporal = ST->isNonTemporal();
654 AAMDNodes AAInfo = ST->getAAInfo();
656 unsigned NumElem = StVT.getVectorNumElements();
657 // The type of the data we want to save
658 EVT RegVT = Value.getValueType();
659 EVT RegSclVT = RegVT.getScalarType();
660 // The type of data as saved in memory.
661 EVT MemSclVT = StVT.getScalarType();
663 // Cast floats into integers
664 unsigned ScalarSize = MemSclVT.getSizeInBits();
666 // Round odd types to the next pow of two.
667 if (!isPowerOf2_32(ScalarSize))
668 ScalarSize = NextPowerOf2(ScalarSize);
670 // Store Stride in bytes
671 unsigned Stride = ScalarSize/8;
672 // Extract each of the elements from the original vector
673 // and save them into memory individually.
674 SmallVector<SDValue, 8> Stores;
675 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
676 SDValue Ex = DAG.getNode(
677 ISD::EXTRACT_VECTOR_ELT, dl, RegSclVT, Value,
678 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
680 // This scalar TruncStore may be illegal, but we legalize it later.
681 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
682 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
683 isVolatile, isNonTemporal, MinAlign(Alignment, Idx*Stride),
686 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
687 DAG.getConstant(Stride, dl, BasePTR.getValueType()));
689 Stores.push_back(Store);
691 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
692 AddLegalizedOperand(Op, TF);
696 SDValue VectorLegalizer::Expand(SDValue Op) {
697 switch (Op->getOpcode()) {
698 case ISD::SIGN_EXTEND_INREG:
699 return ExpandSEXTINREG(Op);
700 case ISD::ANY_EXTEND_VECTOR_INREG:
701 return ExpandANY_EXTEND_VECTOR_INREG(Op);
702 case ISD::SIGN_EXTEND_VECTOR_INREG:
703 return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
704 case ISD::ZERO_EXTEND_VECTOR_INREG:
705 return ExpandZERO_EXTEND_VECTOR_INREG(Op);
707 return ExpandBSWAP(Op);
709 return ExpandVSELECT(Op);
711 return ExpandSELECT(Op);
712 case ISD::UINT_TO_FP:
713 return ExpandUINT_TO_FLOAT(Op);
715 return ExpandFNEG(Op);
717 return UnrollVSETCC(Op);
720 return ExpandABSDIFF(Op);
722 return DAG.UnrollVectorOp(Op.getNode());
726 SDValue VectorLegalizer::ExpandABSDIFF(SDValue Op) {
728 SDValue Op0 = Op.getOperand(0);
729 SDValue Op1 = Op.getOperand(1);
730 EVT VT = Op.getValueType();
732 // For unsigned intrinsic, promote the type to handle unsigned overflow.
733 bool isUabsdiff = (Op->getOpcode() == ISD::UABSDIFF);
735 VT = VT.widenIntegerVectorElementType(*DAG.getContext());
736 Op0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op0);
737 Op1 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op1);
741 Flags.setNoSignedWrap(!isUabsdiff);
742 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op0, Op1, &Flags);
744 return DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Sub);
747 DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(DAG.getDataLayout(),
748 *DAG.getContext(), VT),
749 Sub, DAG.getConstant(0, dl, VT), DAG.getCondCode(ISD::SETGE));
750 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), Sub, &Flags);
751 return DAG.getNode(ISD::VSELECT, dl, VT, Cmp, Sub, Neg);
754 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
755 // Lower a select instruction where the condition is a scalar and the
756 // operands are vectors. Lower this select to VSELECT and implement it
757 // using XOR AND OR. The selector bit is broadcasted.
758 EVT VT = Op.getValueType();
761 SDValue Mask = Op.getOperand(0);
762 SDValue Op1 = Op.getOperand(1);
763 SDValue Op2 = Op.getOperand(2);
765 assert(VT.isVector() && !Mask.getValueType().isVector()
766 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
768 unsigned NumElem = VT.getVectorNumElements();
770 // If we can't even use the basic vector operations of
771 // AND,OR,XOR, we will have to scalarize the op.
772 // Notice that the operation may be 'promoted' which means that it is
773 // 'bitcasted' to another type which is handled.
774 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
775 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
776 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
777 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
778 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
779 return DAG.UnrollVectorOp(Op.getNode());
781 // Generate a mask operand.
782 EVT MaskTy = VT.changeVectorElementTypeToInteger();
784 // What is the size of each element in the vector mask.
785 EVT BitTy = MaskTy.getScalarType();
787 Mask = DAG.getSelect(DL, BitTy, Mask,
788 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
790 DAG.getConstant(0, DL, BitTy));
792 // Broadcast the mask so that the entire vector is all-one or all zero.
793 SmallVector<SDValue, 8> Ops(NumElem, Mask);
794 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
796 // Bitcast the operands to be the same type as the mask.
797 // This is needed when we select between FP types because
798 // the mask is a vector of integers.
799 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
800 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
802 SDValue AllOnes = DAG.getConstant(
803 APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy);
804 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
806 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
807 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
808 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
809 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
812 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
813 EVT VT = Op.getValueType();
815 // Make sure that the SRA and SHL instructions are available.
816 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
817 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
818 return DAG.UnrollVectorOp(Op.getNode());
821 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
823 unsigned BW = VT.getScalarType().getSizeInBits();
824 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
825 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
827 Op = Op.getOperand(0);
828 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
829 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
832 // Generically expand a vector anyext in register to a shuffle of the relevant
833 // lanes into the appropriate locations, with other lanes left undef.
834 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
836 EVT VT = Op.getValueType();
837 int NumElements = VT.getVectorNumElements();
838 SDValue Src = Op.getOperand(0);
839 EVT SrcVT = Src.getValueType();
840 int NumSrcElements = SrcVT.getVectorNumElements();
842 // Build a base mask of undef shuffles.
843 SmallVector<int, 16> ShuffleMask;
844 ShuffleMask.resize(NumSrcElements, -1);
846 // Place the extended lanes into the correct locations.
847 int ExtLaneScale = NumSrcElements / NumElements;
848 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
849 for (int i = 0; i < NumElements; ++i)
850 ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
853 ISD::BITCAST, DL, VT,
854 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
857 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
859 EVT VT = Op.getValueType();
860 SDValue Src = Op.getOperand(0);
861 EVT SrcVT = Src.getValueType();
863 // First build an any-extend node which can be legalized above when we
864 // recurse through it.
865 Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
867 // Now we need sign extend. Do this by shifting the elements. Even if these
868 // aren't legal operations, they have a better chance of being legalized
869 // without full scalarization than the sign extension does.
870 unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
871 unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
872 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
873 return DAG.getNode(ISD::SRA, DL, VT,
874 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
878 // Generically expand a vector zext in register to a shuffle of the relevant
879 // lanes into the appropriate locations, a blend of zero into the high bits,
880 // and a bitcast to the wider element type.
881 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
883 EVT VT = Op.getValueType();
884 int NumElements = VT.getVectorNumElements();
885 SDValue Src = Op.getOperand(0);
886 EVT SrcVT = Src.getValueType();
887 int NumSrcElements = SrcVT.getVectorNumElements();
889 // Build up a zero vector to blend into this one.
890 EVT SrcScalarVT = SrcVT.getScalarType();
891 SDValue ScalarZero = DAG.getTargetConstant(0, DL, SrcScalarVT);
892 SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero);
893 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands);
895 // Shuffle the incoming lanes into the correct position, and pull all other
896 // lanes from the zero vector.
897 SmallVector<int, 16> ShuffleMask;
898 ShuffleMask.reserve(NumSrcElements);
899 for (int i = 0; i < NumSrcElements; ++i)
900 ShuffleMask.push_back(i);
902 int ExtLaneScale = NumSrcElements / NumElements;
903 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
904 for (int i = 0; i < NumElements; ++i)
905 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
907 return DAG.getNode(ISD::BITCAST, DL, VT,
908 DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
911 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
912 EVT VT = Op.getValueType();
914 // Generate a byte wise shuffle mask for the BSWAP.
915 SmallVector<int, 16> ShuffleMask;
916 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
917 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
918 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
919 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
921 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
923 // Only emit a shuffle if the mask is legal.
924 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
925 return DAG.UnrollVectorOp(Op.getNode());
928 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
929 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
931 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
934 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
935 // Implement VSELECT in terms of XOR, AND, OR
936 // on platforms which do not support blend natively.
939 SDValue Mask = Op.getOperand(0);
940 SDValue Op1 = Op.getOperand(1);
941 SDValue Op2 = Op.getOperand(2);
943 EVT VT = Mask.getValueType();
945 // If we can't even use the basic vector operations of
946 // AND,OR,XOR, we will have to scalarize the op.
947 // Notice that the operation may be 'promoted' which means that it is
948 // 'bitcasted' to another type which is handled.
949 // This operation also isn't safe with AND, OR, XOR when the boolean
950 // type is 0/1 as we need an all ones vector constant to mask with.
951 // FIXME: Sign extend 1 to all ones if thats legal on the target.
952 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
953 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
954 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
955 TLI.getBooleanContents(Op1.getValueType()) !=
956 TargetLowering::ZeroOrNegativeOneBooleanContent)
957 return DAG.UnrollVectorOp(Op.getNode());
959 // If the mask and the type are different sizes, unroll the vector op. This
960 // can occur when getSetCCResultType returns something that is different in
961 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
962 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
963 return DAG.UnrollVectorOp(Op.getNode());
965 // Bitcast the operands to be the same type as the mask.
966 // This is needed when we select between FP types because
967 // the mask is a vector of integers.
968 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
969 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
971 SDValue AllOnes = DAG.getConstant(
972 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), DL, VT);
973 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
975 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
976 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
977 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
978 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
981 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
982 EVT VT = Op.getOperand(0).getValueType();
985 // Make sure that the SINT_TO_FP and SRL instructions are available.
986 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
987 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
988 return DAG.UnrollVectorOp(Op.getNode());
990 EVT SVT = VT.getScalarType();
991 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
992 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
994 unsigned BW = SVT.getSizeInBits();
995 SDValue HalfWord = DAG.getConstant(BW/2, DL, VT);
997 // Constants to clear the upper part of the word.
998 // Notice that we can also use SHL+SHR, but using a constant is slightly
1000 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
1001 SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
1003 // Two to the power of half-word-size.
1004 SDValue TWOHW = DAG.getConstantFP(1 << (BW/2), DL, Op.getValueType());
1006 // Clear upper part of LO, lower HI
1007 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
1008 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
1010 // Convert hi and lo to floats
1011 // Convert the hi part back to the upper values
1012 // TODO: Can any fast-math-flags be set on these nodes?
1013 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
1014 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
1015 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
1017 // Add the two halves
1018 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
1022 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
1023 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
1025 SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
1026 // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
1027 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
1028 Zero, Op.getOperand(0));
1030 return DAG.UnrollVectorOp(Op.getNode());
1033 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
1034 EVT VT = Op.getValueType();
1035 unsigned NumElems = VT.getVectorNumElements();
1036 EVT EltVT = VT.getVectorElementType();
1037 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
1038 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
1040 SmallVector<SDValue, 8> Ops(NumElems);
1041 for (unsigned i = 0; i < NumElems; ++i) {
1042 SDValue LHSElem = DAG.getNode(
1043 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
1044 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1045 SDValue RHSElem = DAG.getNode(
1046 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
1047 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1048 Ops[i] = DAG.getNode(ISD::SETCC, dl,
1049 TLI.getSetCCResultType(DAG.getDataLayout(),
1050 *DAG.getContext(), TmpEltVT),
1051 LHSElem, RHSElem, CC);
1052 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
1053 DAG.getConstant(APInt::getAllOnesValue
1054 (EltVT.getSizeInBits()), dl, EltVT),
1055 DAG.getConstant(0, dl, EltVT));
1057 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1062 bool SelectionDAG::LegalizeVectors() {
1063 return VectorLegalizer(*this).Run();