1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::LegalizeVectors method.
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/Target/TargetLowering.h"
35 class VectorLegalizer {
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
40 /// For nodes that are of legal width, and that have more than one use, this
41 /// map indicates what regularized operand to use. This allows us to avoid
42 /// legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
45 /// \brief Adds a node to the translation cache.
46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
50 LegalizedNodes.insert(std::make_pair(To, To));
53 /// \brief Legalizes the given node.
54 SDValue LegalizeOp(SDValue Op);
56 /// \brief Assuming the node is legal, "legalize" the results.
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
59 /// \brief Implements unrolling a VSETCC.
60 SDValue UnrollVSETCC(SDValue Op);
62 /// \brief Implement expand-based legalization of vector operations.
64 /// This is just a high-level routine to dispatch to specific code paths for
65 /// operations to legalize them.
66 SDValue Expand(SDValue Op);
68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
71 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
72 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
76 SDValue ExpandSEXTINREG(SDValue Op);
78 /// \brief Expand bswap of vectors into a shuffle if legal.
79 SDValue ExpandBSWAP(SDValue Op);
81 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
82 /// supported by the target.
83 SDValue ExpandVSELECT(SDValue Op);
84 SDValue ExpandSELECT(SDValue Op);
85 SDValue ExpandLoad(SDValue Op);
86 SDValue ExpandStore(SDValue Op);
87 SDValue ExpandFNEG(SDValue Op);
89 /// \brief Implements vector promotion.
91 /// This is essentially just bitcasting the operands to a different type and
92 /// bitcasting the result back to the original type.
93 SDValue Promote(SDValue Op);
95 /// \brief Implements [SU]INT_TO_FP vector promotion.
97 /// This is a [zs]ext of the input operand to the next size up.
98 SDValue PromoteINT_TO_FP(SDValue Op);
100 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
102 /// It is promoted to the next size up integer type. The result is then
103 /// truncated back to the original type.
104 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
107 /// \brief Begin legalizer the vector operations in the DAG.
109 VectorLegalizer(SelectionDAG& dag) :
110 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
113 bool VectorLegalizer::Run() {
114 // Before we start legalizing vector nodes, check if there are any vectors.
115 bool HasVectors = false;
116 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
117 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
118 // Check if the values of the nodes contain vectors. We don't need to check
119 // the operands because we are going to check their values at some point.
120 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
122 HasVectors |= J->isVector();
124 // If we found a vector node we can start the legalization.
129 // If this basic block has no vectors then no need to legalize vectors.
133 // The legalize process is inherently a bottom-up recursive process (users
134 // legalize their uses before themselves). Given infinite stack space, we
135 // could just start legalizing on the root and traverse the whole graph. In
136 // practice however, this causes us to run out of stack space on large basic
137 // blocks. To avoid this problem, compute an ordering of the nodes where each
138 // node is only legalized after all of its operands are legalized.
139 DAG.AssignTopologicalOrder();
140 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
141 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
142 LegalizeOp(SDValue(I, 0));
144 // Finally, it's possible the root changed. Get the new root.
145 SDValue OldRoot = DAG.getRoot();
146 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
147 DAG.setRoot(LegalizedNodes[OldRoot]);
149 LegalizedNodes.clear();
151 // Remove dead nodes now.
152 DAG.RemoveDeadNodes();
157 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
158 // Generic legalization: just pass the operand through.
159 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
160 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
161 return Result.getValue(Op.getResNo());
164 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
165 // Note that LegalizeOp may be reentered even from single-use nodes, which
166 // means that we always must cache transformed nodes.
167 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
168 if (I != LegalizedNodes.end()) return I->second;
170 SDNode* Node = Op.getNode();
172 // Legalize the operands
173 SmallVector<SDValue, 8> Ops;
174 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
175 Ops.push_back(LegalizeOp(Node->getOperand(i)));
177 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
179 if (Op.getOpcode() == ISD::LOAD) {
180 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
181 ISD::LoadExtType ExtType = LD->getExtensionType();
182 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
183 if (TLI.isLoadExtLegal(LD->getExtensionType(), LD->getMemoryVT()))
184 return TranslateLegalizeResults(Op, Result);
186 return LegalizeOp(ExpandLoad(Op));
188 } else if (Op.getOpcode() == ISD::STORE) {
189 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
190 EVT StVT = ST->getMemoryVT();
191 MVT ValVT = ST->getValue().getSimpleValueType();
192 if (StVT.isVector() && ST->isTruncatingStore())
193 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
194 default: llvm_unreachable("This action is not supported yet!");
195 case TargetLowering::Legal:
196 return TranslateLegalizeResults(Op, Result);
197 case TargetLowering::Custom:
199 return TranslateLegalizeResults(Op, TLI.LowerOperation(Result, DAG));
200 case TargetLowering::Expand:
202 return LegalizeOp(ExpandStore(Op));
206 bool HasVectorValue = false;
207 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
210 HasVectorValue |= J->isVector();
212 return TranslateLegalizeResults(Op, Result);
215 switch (Op.getOpcode()) {
217 return TranslateLegalizeResults(Op, Result);
241 case ISD::CTLZ_ZERO_UNDEF:
242 case ISD::CTTZ_ZERO_UNDEF:
248 case ISD::ZERO_EXTEND:
249 case ISD::ANY_EXTEND:
251 case ISD::SIGN_EXTEND:
252 case ISD::FP_TO_SINT:
253 case ISD::FP_TO_UINT:
270 case ISD::FNEARBYINT:
276 case ISD::SIGN_EXTEND_INREG:
277 QueryType = Node->getValueType(0);
279 case ISD::FP_ROUND_INREG:
280 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
282 case ISD::SINT_TO_FP:
283 case ISD::UINT_TO_FP:
284 QueryType = Node->getOperand(0).getValueType();
288 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
289 case TargetLowering::Promote:
290 Result = Promote(Op);
293 case TargetLowering::Legal:
295 case TargetLowering::Custom: {
296 SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
297 if (Tmp1.getNode()) {
303 case TargetLowering::Expand:
307 // Make sure that the generated code is itself legal.
309 Result = LegalizeOp(Result);
313 // Note that LegalizeOp may be reentered even from single-use nodes, which
314 // means that we always must cache transformed nodes.
315 AddLegalizedOperand(Op, Result);
319 SDValue VectorLegalizer::Promote(SDValue Op) {
320 // For a few operations there is a specific concept for promotion based on
321 // the operand's type.
322 switch (Op.getOpcode()) {
323 case ISD::SINT_TO_FP:
324 case ISD::UINT_TO_FP:
325 // "Promote" the operation by extending the operand.
326 return PromoteINT_TO_FP(Op);
327 case ISD::FP_TO_UINT:
328 case ISD::FP_TO_SINT:
329 // Promote the operation by extending the operand.
330 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
333 // The rest of the time, vector "promotion" is basically just bitcasting and
334 // doing the operation in a different type. For example, x86 promotes
335 // ISD::AND on v2i32 to v1i64.
336 MVT VT = Op.getSimpleValueType();
337 assert(Op.getNode()->getNumValues() == 1 &&
338 "Can't promote a vector with multiple results!");
339 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
341 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
343 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
344 if (Op.getOperand(j).getValueType().isVector())
345 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
347 Operands[j] = Op.getOperand(j);
350 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands);
352 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
355 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
356 // INT_TO_FP operations may require the input operand be promoted even
357 // when the type is otherwise legal.
358 EVT VT = Op.getOperand(0).getValueType();
359 assert(Op.getNode()->getNumValues() == 1 &&
360 "Can't promote a vector with multiple results!");
362 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
363 // by widening the vector w/ the same element width and twice the number
364 // of elements. We want the other way around, the same number of elements,
365 // each twice the width.
367 // Increase the bitwidth of the element to the next pow-of-two
368 // (which is greater than 8 bits).
370 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
371 assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
373 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
375 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
377 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
378 if (Op.getOperand(j).getValueType().isVector())
379 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
381 Operands[j] = Op.getOperand(j);
384 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
387 // For FP_TO_INT we promote the result type to a vector type with wider
388 // elements and then truncate the result. This is different from the default
389 // PromoteVector which uses bitcast to promote thus assumning that the
390 // promoted vector type has the same overall size.
391 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
392 assert(Op.getNode()->getNumValues() == 1 &&
393 "Can't promote a vector with multiple results!");
394 EVT VT = Op.getValueType();
399 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
400 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
401 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
402 NewOpc = ISD::FP_TO_SINT;
405 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
406 NewOpc = ISD::FP_TO_UINT;
412 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
413 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
417 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
419 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
420 SDValue Chain = LD->getChain();
421 SDValue BasePTR = LD->getBasePtr();
422 EVT SrcVT = LD->getMemoryVT();
423 ISD::LoadExtType ExtType = LD->getExtensionType();
425 SmallVector<SDValue, 8> Vals;
426 SmallVector<SDValue, 8> LoadChains;
427 unsigned NumElem = SrcVT.getVectorNumElements();
429 EVT SrcEltVT = SrcVT.getScalarType();
430 EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
432 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
433 // When elements in a vector is not byte-addressable, we cannot directly
434 // load each element by advancing pointer, which could only address bytes.
435 // Instead, we load all significant words, mask bits off, and concatenate
436 // them to form each element. Finally, they are extended to destination
437 // scalar type to build the destination vector.
438 EVT WideVT = TLI.getPointerTy();
440 assert(WideVT.isRound() &&
441 "Could not handle the sophisticated case when the widest integer is"
443 assert(WideVT.bitsGE(SrcEltVT) &&
444 "Type is not legalized?");
446 unsigned WideBytes = WideVT.getStoreSize();
448 unsigned RemainingBytes = SrcVT.getStoreSize();
449 SmallVector<SDValue, 8> LoadVals;
451 while (RemainingBytes > 0) {
453 unsigned LoadBytes = WideBytes;
455 if (RemainingBytes >= LoadBytes) {
456 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
457 LD->getPointerInfo().getWithOffset(Offset),
458 LD->isVolatile(), LD->isNonTemporal(),
459 LD->isInvariant(), LD->getAlignment(),
463 while (RemainingBytes < LoadBytes) {
464 LoadBytes >>= 1; // Reduce the load size by half.
465 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
467 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
468 LD->getPointerInfo().getWithOffset(Offset),
469 LoadVT, LD->isVolatile(),
470 LD->isNonTemporal(), LD->getAlignment(),
474 RemainingBytes -= LoadBytes;
476 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
477 DAG.getConstant(LoadBytes, BasePTR.getValueType()));
479 LoadVals.push_back(ScalarLoad.getValue(0));
480 LoadChains.push_back(ScalarLoad.getValue(1));
483 // Extract bits, pack and extend/trunc them into destination type.
484 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
485 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, WideVT);
487 unsigned BitOffset = 0;
488 unsigned WideIdx = 0;
489 unsigned WideBits = WideVT.getSizeInBits();
491 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
492 SDValue Lo, Hi, ShAmt;
494 if (BitOffset < WideBits) {
495 ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
496 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
497 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
500 BitOffset += SrcEltBits;
501 if (BitOffset >= WideBits) {
505 ShAmt = DAG.getConstant(SrcEltBits - Offset,
506 TLI.getShiftAmountTy(WideVT));
507 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
508 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
513 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
516 default: llvm_unreachable("Unknown extended-load op!");
518 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
521 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
524 ShAmt = DAG.getConstant(WideBits - SrcEltBits,
525 TLI.getShiftAmountTy(WideVT));
526 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
527 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
528 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
534 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
536 for (unsigned Idx=0; Idx<NumElem; Idx++) {
537 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
538 Op.getNode()->getValueType(0).getScalarType(),
539 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
540 SrcVT.getScalarType(),
541 LD->isVolatile(), LD->isNonTemporal(),
542 LD->getAlignment(), LD->getTBAAInfo());
544 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
545 DAG.getConstant(Stride, BasePTR.getValueType()));
547 Vals.push_back(ScalarLoad.getValue(0));
548 LoadChains.push_back(ScalarLoad.getValue(1));
552 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
553 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
554 Op.getNode()->getValueType(0), Vals);
556 AddLegalizedOperand(Op.getValue(0), Value);
557 AddLegalizedOperand(Op.getValue(1), NewChain);
559 return (Op.getResNo() ? NewChain : Value);
562 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
564 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
565 SDValue Chain = ST->getChain();
566 SDValue BasePTR = ST->getBasePtr();
567 SDValue Value = ST->getValue();
568 EVT StVT = ST->getMemoryVT();
570 unsigned Alignment = ST->getAlignment();
571 bool isVolatile = ST->isVolatile();
572 bool isNonTemporal = ST->isNonTemporal();
573 const MDNode *TBAAInfo = ST->getTBAAInfo();
575 unsigned NumElem = StVT.getVectorNumElements();
576 // The type of the data we want to save
577 EVT RegVT = Value.getValueType();
578 EVT RegSclVT = RegVT.getScalarType();
579 // The type of data as saved in memory.
580 EVT MemSclVT = StVT.getScalarType();
582 // Cast floats into integers
583 unsigned ScalarSize = MemSclVT.getSizeInBits();
585 // Round odd types to the next pow of two.
586 if (!isPowerOf2_32(ScalarSize))
587 ScalarSize = NextPowerOf2(ScalarSize);
589 // Store Stride in bytes
590 unsigned Stride = ScalarSize/8;
591 // Extract each of the elements from the original vector
592 // and save them into memory individually.
593 SmallVector<SDValue, 8> Stores;
594 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
595 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
596 RegSclVT, Value, DAG.getConstant(Idx, TLI.getVectorIdxTy()));
598 // This scalar TruncStore may be illegal, but we legalize it later.
599 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
600 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
601 isVolatile, isNonTemporal, Alignment, TBAAInfo);
603 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
604 DAG.getConstant(Stride, BasePTR.getValueType()));
606 Stores.push_back(Store);
608 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
609 AddLegalizedOperand(Op, TF);
613 SDValue VectorLegalizer::Expand(SDValue Op) {
614 switch (Op->getOpcode()) {
615 case ISD::SIGN_EXTEND_INREG:
616 return ExpandSEXTINREG(Op);
618 return ExpandBSWAP(Op);
620 return ExpandVSELECT(Op);
622 return ExpandSELECT(Op);
623 case ISD::UINT_TO_FP:
624 return ExpandUINT_TO_FLOAT(Op);
626 return ExpandFNEG(Op);
628 return UnrollVSETCC(Op);
630 return DAG.UnrollVectorOp(Op.getNode());
634 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
635 // Lower a select instruction where the condition is a scalar and the
636 // operands are vectors. Lower this select to VSELECT and implement it
637 // using XOR AND OR. The selector bit is broadcasted.
638 EVT VT = Op.getValueType();
641 SDValue Mask = Op.getOperand(0);
642 SDValue Op1 = Op.getOperand(1);
643 SDValue Op2 = Op.getOperand(2);
645 assert(VT.isVector() && !Mask.getValueType().isVector()
646 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
648 unsigned NumElem = VT.getVectorNumElements();
650 // If we can't even use the basic vector operations of
651 // AND,OR,XOR, we will have to scalarize the op.
652 // Notice that the operation may be 'promoted' which means that it is
653 // 'bitcasted' to another type which is handled.
654 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
655 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
656 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
657 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
658 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
659 return DAG.UnrollVectorOp(Op.getNode());
661 // Generate a mask operand.
662 EVT MaskTy = VT.changeVectorElementTypeToInteger();
664 // What is the size of each element in the vector mask.
665 EVT BitTy = MaskTy.getScalarType();
667 Mask = DAG.getSelect(DL, BitTy, Mask,
668 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy),
669 DAG.getConstant(0, BitTy));
671 // Broadcast the mask so that the entire vector is all-one or all zero.
672 SmallVector<SDValue, 8> Ops(NumElem, Mask);
673 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
675 // Bitcast the operands to be the same type as the mask.
676 // This is needed when we select between FP types because
677 // the mask is a vector of integers.
678 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
679 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
681 SDValue AllOnes = DAG.getConstant(
682 APInt::getAllOnesValue(BitTy.getSizeInBits()), MaskTy);
683 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
685 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
686 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
687 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
688 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
691 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
692 EVT VT = Op.getValueType();
694 // Make sure that the SRA and SHL instructions are available.
695 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
696 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
697 return DAG.UnrollVectorOp(Op.getNode());
700 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
702 unsigned BW = VT.getScalarType().getSizeInBits();
703 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
704 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT);
706 Op = Op.getOperand(0);
707 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
708 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
711 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
712 EVT VT = Op.getValueType();
714 // Generate a byte wise shuffle mask for the BSWAP.
715 SmallVector<int, 16> ShuffleMask;
716 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
717 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
718 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
719 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
721 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
723 // Only emit a shuffle if the mask is legal.
724 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
725 return DAG.UnrollVectorOp(Op.getNode());
728 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
729 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
731 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
734 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
735 // Implement VSELECT in terms of XOR, AND, OR
736 // on platforms which do not support blend natively.
739 SDValue Mask = Op.getOperand(0);
740 SDValue Op1 = Op.getOperand(1);
741 SDValue Op2 = Op.getOperand(2);
743 EVT VT = Mask.getValueType();
745 // If we can't even use the basic vector operations of
746 // AND,OR,XOR, we will have to scalarize the op.
747 // Notice that the operation may be 'promoted' which means that it is
748 // 'bitcasted' to another type which is handled.
749 // This operation also isn't safe with AND, OR, XOR when the boolean
750 // type is 0/1 as we need an all ones vector constant to mask with.
751 // FIXME: Sign extend 1 to all ones if thats legal on the target.
752 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
753 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
754 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
755 TLI.getBooleanContents(true) !=
756 TargetLowering::ZeroOrNegativeOneBooleanContent)
757 return DAG.UnrollVectorOp(Op.getNode());
759 // If the mask and the type are different sizes, unroll the vector op. This
760 // can occur when getSetCCResultType returns something that is different in
761 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
762 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
763 return DAG.UnrollVectorOp(Op.getNode());
765 // Bitcast the operands to be the same type as the mask.
766 // This is needed when we select between FP types because
767 // the mask is a vector of integers.
768 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
769 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
771 SDValue AllOnes = DAG.getConstant(
772 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT);
773 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
775 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
776 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
777 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
778 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
781 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
782 EVT VT = Op.getOperand(0).getValueType();
785 // Make sure that the SINT_TO_FP and SRL instructions are available.
786 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
787 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
788 return DAG.UnrollVectorOp(Op.getNode());
790 EVT SVT = VT.getScalarType();
791 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
792 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
794 unsigned BW = SVT.getSizeInBits();
795 SDValue HalfWord = DAG.getConstant(BW/2, VT);
797 // Constants to clear the upper part of the word.
798 // Notice that we can also use SHL+SHR, but using a constant is slightly
800 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
801 SDValue HalfWordMask = DAG.getConstant(HWMask, VT);
803 // Two to the power of half-word-size.
804 SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType());
806 // Clear upper part of LO, lower HI
807 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
808 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
810 // Convert hi and lo to floats
811 // Convert the hi part back to the upper values
812 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
813 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
814 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
816 // Add the two halves
817 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
821 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
822 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
823 SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType());
824 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
825 Zero, Op.getOperand(0));
827 return DAG.UnrollVectorOp(Op.getNode());
830 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
831 EVT VT = Op.getValueType();
832 unsigned NumElems = VT.getVectorNumElements();
833 EVT EltVT = VT.getVectorElementType();
834 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
835 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
837 SmallVector<SDValue, 8> Ops(NumElems);
838 for (unsigned i = 0; i < NumElems; ++i) {
839 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
840 DAG.getConstant(i, TLI.getVectorIdxTy()));
841 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
842 DAG.getConstant(i, TLI.getVectorIdxTy()));
843 Ops[i] = DAG.getNode(ISD::SETCC, dl,
844 TLI.getSetCCResultType(*DAG.getContext(), TmpEltVT),
845 LHSElem, RHSElem, CC);
846 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
847 DAG.getConstant(APInt::getAllOnesValue
848 (EltVT.getSizeInBits()), EltVT),
849 DAG.getConstant(0, EltVT));
851 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
856 bool SelectionDAG::LegalizeVectors() {
857 return VectorLegalizer(*this).Run();