1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
30 //===----------------------------------------------------------------------===//
31 // Result Vector Scalarization: <1 x ty> -> ty.
32 //===----------------------------------------------------------------------===//
34 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
38 SDValue R = SDValue();
40 switch (N->getOpcode()) {
43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
47 llvm_unreachable("Do not know how to scalarize the result of this operator!");
49 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
50 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
51 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
52 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
53 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
54 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
55 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
56 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
57 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
58 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
59 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
60 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
61 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
62 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
63 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
64 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
84 case ISD::SIGN_EXTEND:
85 case ISD::ZERO_EXTEND:
87 R = ScalarizeVecRes_UnaryOp(N);
109 R = ScalarizeVecRes_BinOp(N);
113 // If R is null, the sub-method took care of registering the result.
115 SetScalarizedVector(SDValue(N, ResNo), R);
118 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
119 SDValue LHS = GetScalarizedVector(N->getOperand(0));
120 SDValue RHS = GetScalarizedVector(N->getOperand(1));
121 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
122 LHS.getValueType(), LHS, RHS);
125 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
126 EVT NewVT = N->getValueType(0).getVectorElementType();
127 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
128 NewVT, N->getOperand(0));
131 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
132 EVT NewVT = N->getValueType(0).getVectorElementType();
133 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
134 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
135 Op0, DAG.getValueType(NewVT),
136 DAG.getValueType(Op0.getValueType()),
139 cast<CvtRndSatSDNode>(N)->getCvtCode());
142 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
143 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
144 N->getValueType(0).getVectorElementType(),
145 N->getOperand(0), N->getOperand(1));
148 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
149 SDValue Op = GetScalarizedVector(N->getOperand(0));
150 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
151 Op.getValueType(), Op, N->getOperand(1));
154 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
155 // The value to insert may have a wider type than the vector element type,
156 // so be sure to truncate it to the element type if necessary.
157 SDValue Op = N->getOperand(1);
158 EVT EltVT = N->getValueType(0).getVectorElementType();
159 if (Op.getValueType() != EltVT)
160 // FIXME: Can this happen for floating point types?
161 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
166 assert(N->isUnindexed() && "Indexed vector load?");
168 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
169 N->getExtensionType(),
170 N->getValueType(0).getVectorElementType(),
172 N->getChain(), N->getBasePtr(),
173 DAG.getUNDEF(N->getBasePtr().getValueType()),
175 N->getMemoryVT().getVectorElementType(),
176 N->isVolatile(), N->isNonTemporal(),
177 N->getOriginalAlignment());
179 // Legalized the chain result - switch anything that used the old chain to
181 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
185 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
186 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
187 EVT DestVT = N->getValueType(0).getVectorElementType();
188 SDValue Op = GetScalarizedVector(N->getOperand(0));
189 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
192 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
193 EVT EltVT = N->getValueType(0).getVectorElementType();
194 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
195 SDValue LHS = GetScalarizedVector(N->getOperand(0));
196 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT,
197 LHS, DAG.getValueType(ExtVT));
200 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
201 // If the operand is wider than the vector element type then it is implicitly
202 // truncated. Make that explicit here.
203 EVT EltVT = N->getValueType(0).getVectorElementType();
204 SDValue InOp = N->getOperand(0);
205 if (InOp.getValueType() != EltVT)
206 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
210 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
211 SDValue LHS = GetScalarizedVector(N->getOperand(1));
212 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
213 LHS.getValueType(), N->getOperand(0), LHS,
214 GetScalarizedVector(N->getOperand(2)));
217 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
218 SDValue LHS = GetScalarizedVector(N->getOperand(2));
219 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
220 N->getOperand(0), N->getOperand(1),
221 LHS, GetScalarizedVector(N->getOperand(3)),
225 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
226 SDValue LHS = GetScalarizedVector(N->getOperand(0));
227 SDValue RHS = GetScalarizedVector(N->getOperand(1));
228 DebugLoc DL = N->getDebugLoc();
230 // Turn it into a scalar SETCC.
231 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
234 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
235 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
238 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
239 // Figure out if the scalar is the LHS or RHS and return it.
240 SDValue Arg = N->getOperand(2).getOperand(0);
241 if (Arg.getOpcode() == ISD::UNDEF)
242 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
243 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
244 return GetScalarizedVector(N->getOperand(Op));
247 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
248 SDValue LHS = GetScalarizedVector(N->getOperand(0));
249 SDValue RHS = GetScalarizedVector(N->getOperand(1));
250 EVT NVT = N->getValueType(0).getVectorElementType();
251 EVT SVT = TLI.getSetCCResultType(LHS.getValueType());
252 DebugLoc DL = N->getDebugLoc();
254 // Turn it into a scalar SETCC.
255 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2));
257 // VSETCC always returns a sign-extended value, while SETCC may not. The
258 // SETCC result type may not match the vector element type. Correct these.
259 if (NVT.bitsLE(SVT)) {
260 // The SETCC result type is bigger than the vector element type.
261 // Ensure the SETCC result is sign-extended.
262 if (TLI.getBooleanContents() !=
263 TargetLowering::ZeroOrNegativeOneBooleanContent)
264 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
265 DAG.getValueType(MVT::i1));
266 // Truncate to the final type.
267 return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
270 // The SETCC result type is smaller than the vector element type.
271 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
272 if (TLI.getBooleanContents() !=
273 TargetLowering::ZeroOrNegativeOneBooleanContent)
274 Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
275 // Sign extend to the final type.
276 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
280 //===----------------------------------------------------------------------===//
281 // Operand Vector Scalarization <1 x ty> -> ty.
282 //===----------------------------------------------------------------------===//
284 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
285 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
288 SDValue Res = SDValue();
290 if (Res.getNode() == 0) {
291 switch (N->getOpcode()) {
294 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
298 llvm_unreachable("Do not know how to scalarize this operator's operand!");
299 case ISD::BIT_CONVERT:
300 Res = ScalarizeVecOp_BIT_CONVERT(N);
302 case ISD::CONCAT_VECTORS:
303 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
305 case ISD::EXTRACT_VECTOR_ELT:
306 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
309 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
314 // If the result is null, the sub-method took care of registering results etc.
315 if (!Res.getNode()) return false;
317 // If the result is N, the sub-method updated N in place. Tell the legalizer
319 if (Res.getNode() == N)
322 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
323 "Invalid operand expansion");
325 ReplaceValueWith(SDValue(N, 0), Res);
329 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
330 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
331 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
332 SDValue Elt = GetScalarizedVector(N->getOperand(0));
333 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
334 N->getValueType(0), Elt);
337 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
338 /// use a BUILD_VECTOR instead.
339 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
340 SmallVector<SDValue, 8> Ops(N->getNumOperands());
341 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
342 Ops[i] = GetScalarizedVector(N->getOperand(i));
343 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
344 &Ops[0], Ops.size());
347 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
348 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
350 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
351 SDValue Res = GetScalarizedVector(N->getOperand(0));
352 if (Res.getValueType() != N->getValueType(0))
353 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
358 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
359 /// scalarized, it must be <1 x ty>. Just store the element.
360 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
361 assert(N->isUnindexed() && "Indexed store of one-element vector?");
362 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
363 DebugLoc dl = N->getDebugLoc();
365 if (N->isTruncatingStore())
366 return DAG.getTruncStore(N->getChain(), dl,
367 GetScalarizedVector(N->getOperand(1)),
368 N->getBasePtr(), N->getPointerInfo(),
369 N->getMemoryVT().getVectorElementType(),
370 N->isVolatile(), N->isNonTemporal(),
373 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
374 N->getBasePtr(), N->getPointerInfo(),
375 N->isVolatile(), N->isNonTemporal(),
376 N->getOriginalAlignment());
380 //===----------------------------------------------------------------------===//
381 // Result Vector Splitting
382 //===----------------------------------------------------------------------===//
384 /// SplitVectorResult - This method is called when the specified result of the
385 /// specified node is found to need vector splitting. At this point, the node
386 /// may also have invalid operands or may have other results that need
387 /// legalization, we just know that (at least) one result needs vector
389 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
390 DEBUG(dbgs() << "Split node result: ";
395 switch (N->getOpcode()) {
398 dbgs() << "SplitVectorResult #" << ResNo << ": ";
402 llvm_unreachable("Do not know how to split the result of this operator!");
404 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
405 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
406 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
407 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
409 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
410 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
411 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
412 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
413 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
414 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
415 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
416 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
417 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
418 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
420 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
424 SplitVecRes_SETCC(N, Lo, Hi);
426 case ISD::VECTOR_SHUFFLE:
427 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
442 case ISD::FNEARBYINT:
443 case ISD::FP_TO_SINT:
444 case ISD::FP_TO_UINT:
445 case ISD::SINT_TO_FP:
446 case ISD::UINT_TO_FP:
448 case ISD::SIGN_EXTEND:
449 case ISD::ZERO_EXTEND:
450 case ISD::ANY_EXTEND:
456 SplitVecRes_UnaryOp(N, Lo, Hi);
478 SplitVecRes_BinOp(N, Lo, Hi);
482 // If Lo/Hi is null, the sub-method took care of registering results etc.
484 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
487 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
489 SDValue LHSLo, LHSHi;
490 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
491 SDValue RHSLo, RHSHi;
492 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
493 DebugLoc dl = N->getDebugLoc();
495 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
496 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
499 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
501 // We know the result is a vector. The input may be either a vector or a
504 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
505 DebugLoc dl = N->getDebugLoc();
507 SDValue InOp = N->getOperand(0);
508 EVT InVT = InOp.getValueType();
510 // Handle some special cases efficiently.
511 switch (getTypeAction(InVT)) {
513 assert(false && "Unknown type action!");
517 case ScalarizeVector:
521 // A scalar to vector conversion, where the scalar needs expansion.
522 // If the vector is being split in two then we can just convert the
525 GetExpandedOp(InOp, Lo, Hi);
526 if (TLI.isBigEndian())
528 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
529 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
534 // If the input is a vector that needs to be split, convert each split
535 // piece of the input now.
536 GetSplitVector(InOp, Lo, Hi);
537 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
538 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
542 // In the general case, convert the input to an integer and split it by hand.
543 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
544 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
545 if (TLI.isBigEndian())
546 std::swap(LoIntVT, HiIntVT);
548 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
550 if (TLI.isBigEndian())
552 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
553 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
556 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
559 DebugLoc dl = N->getDebugLoc();
560 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
561 unsigned LoNumElts = LoVT.getVectorNumElements();
562 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
563 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
565 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
566 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
569 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
571 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
572 DebugLoc dl = N->getDebugLoc();
573 unsigned NumSubvectors = N->getNumOperands() / 2;
574 if (NumSubvectors == 1) {
575 Lo = N->getOperand(0);
576 Hi = N->getOperand(1);
581 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
583 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
584 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
586 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
587 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
590 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
593 DebugLoc dl = N->getDebugLoc();
594 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
596 SDValue DTyOpLo = DAG.getValueType(LoVT);
597 SDValue DTyOpHi = DAG.getValueType(HiVT);
599 SDValue RndOp = N->getOperand(3);
600 SDValue SatOp = N->getOperand(4);
601 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
605 EVT InVT = N->getOperand(0).getValueType();
606 switch (getTypeAction(InVT)) {
607 default: llvm_unreachable("Unexpected type action!");
609 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
610 LoVT.getVectorNumElements());
611 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
612 DAG.getIntPtrConstant(0));
613 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
614 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
618 GetSplitVector(N->getOperand(0), VLo, VHi);
621 // If the result needs to be split and the input needs to be widened,
622 // the two types must have different lengths. Use the widened result
623 // and extract from it to do the split.
624 SDValue InOp = GetWidenedVector(N->getOperand(0));
625 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
626 LoVT.getVectorNumElements());
627 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
628 DAG.getIntPtrConstant(0));
629 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
630 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
635 SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
636 SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
638 Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
640 Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp,
644 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
646 SDValue Vec = N->getOperand(0);
647 SDValue Idx = N->getOperand(1);
648 EVT IdxVT = Idx.getValueType();
649 DebugLoc dl = N->getDebugLoc();
652 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
654 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
655 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
656 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
657 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, Idx);
660 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
662 DebugLoc dl = N->getDebugLoc();
663 GetSplitVector(N->getOperand(0), Lo, Hi);
664 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
665 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
668 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
670 SDValue LHSLo, LHSHi;
671 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
672 DebugLoc dl = N->getDebugLoc();
675 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT);
677 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
678 DAG.getValueType(LoVT));
679 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
680 DAG.getValueType(HiVT));
683 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
685 SDValue Vec = N->getOperand(0);
686 SDValue Elt = N->getOperand(1);
687 SDValue Idx = N->getOperand(2);
688 DebugLoc dl = N->getDebugLoc();
689 GetSplitVector(Vec, Lo, Hi);
691 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
692 unsigned IdxVal = CIdx->getZExtValue();
693 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
694 if (IdxVal < LoNumElts)
695 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
696 Lo.getValueType(), Lo, Elt, Idx);
698 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
699 DAG.getIntPtrConstant(IdxVal - LoNumElts));
703 // Spill the vector to the stack.
704 EVT VecVT = Vec.getValueType();
705 EVT EltVT = VecVT.getVectorElementType();
706 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
707 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
708 MachinePointerInfo(), false, false, 0);
710 // Store the new element. This may be larger than the vector element type,
711 // so use a truncating store.
712 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
713 const Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
715 TLI.getTargetData()->getPrefTypeAlignment(VecType);
716 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
719 // Load the Lo part from the stack slot.
720 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
723 // Increment the pointer to the other part.
724 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
725 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
726 DAG.getIntPtrConstant(IncrementSize));
728 // Load the Hi part from the stack slot.
729 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
730 false, false, MinAlign(Alignment, IncrementSize));
733 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
736 DebugLoc dl = N->getDebugLoc();
737 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
738 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
739 Hi = DAG.getUNDEF(HiVT);
742 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
744 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
746 DebugLoc dl = LD->getDebugLoc();
747 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
749 ISD::LoadExtType ExtType = LD->getExtensionType();
750 SDValue Ch = LD->getChain();
751 SDValue Ptr = LD->getBasePtr();
752 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
753 EVT MemoryVT = LD->getMemoryVT();
754 unsigned Alignment = LD->getOriginalAlignment();
755 bool isVolatile = LD->isVolatile();
756 bool isNonTemporal = LD->isNonTemporal();
758 EVT LoMemVT, HiMemVT;
759 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
761 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
762 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
765 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
766 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
767 DAG.getIntPtrConstant(IncrementSize));
768 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
769 LD->getPointerInfo().getWithOffset(IncrementSize),
770 HiMemVT, isVolatile, isNonTemporal, Alignment);
772 // Build a factor node to remember that this load is independent of the
774 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
777 // Legalized the chain result - switch anything that used the old chain to
779 ReplaceValueWith(SDValue(LD, 1), Ch);
782 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
784 DebugLoc DL = N->getDebugLoc();
785 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
788 EVT InVT = N->getOperand(0).getValueType();
789 SDValue LL, LH, RL, RH;
790 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
791 LoVT.getVectorNumElements());
792 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
793 DAG.getIntPtrConstant(0));
794 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
795 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
797 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
798 DAG.getIntPtrConstant(0));
799 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
800 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
802 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
803 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
806 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
808 // Get the dest types - they may not match the input types, e.g. int_to_fp.
810 DebugLoc dl = N->getDebugLoc();
811 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
814 EVT InVT = N->getOperand(0).getValueType();
815 switch (getTypeAction(InVT)) {
816 default: llvm_unreachable("Unexpected type action!");
818 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
819 LoVT.getVectorNumElements());
820 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
821 DAG.getIntPtrConstant(0));
822 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
823 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
827 GetSplitVector(N->getOperand(0), Lo, Hi);
830 // If the result needs to be split and the input needs to be widened,
831 // the two types must have different lengths. Use the widened result
832 // and extract from it to do the split.
833 SDValue InOp = GetWidenedVector(N->getOperand(0));
834 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
835 LoVT.getVectorNumElements());
836 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
837 DAG.getIntPtrConstant(0));
838 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
839 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
844 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
845 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
848 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
849 SDValue &Lo, SDValue &Hi) {
850 // The low and high parts of the original input give four input vectors.
852 DebugLoc dl = N->getDebugLoc();
853 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
854 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
855 EVT NewVT = Inputs[0].getValueType();
856 unsigned NewElts = NewVT.getVectorNumElements();
858 // If Lo or Hi uses elements from at most two of the four input vectors, then
859 // express it as a vector shuffle of those two inputs. Otherwise extract the
860 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
861 SmallVector<int, 16> Ops;
862 for (unsigned High = 0; High < 2; ++High) {
863 SDValue &Output = High ? Hi : Lo;
865 // Build a shuffle mask for the output, discovering on the fly which
866 // input vectors to use as shuffle operands (recorded in InputUsed).
867 // If building a suitable shuffle vector proves too hard, then bail
868 // out with useBuildVector set.
869 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
870 unsigned FirstMaskIdx = High * NewElts;
871 bool useBuildVector = false;
872 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
873 // The mask element. This indexes into the input.
874 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
876 // The input vector this mask element indexes into.
877 unsigned Input = (unsigned)Idx / NewElts;
879 if (Input >= array_lengthof(Inputs)) {
880 // The mask element does not index into any input vector.
885 // Turn the index into an offset from the start of the input vector.
886 Idx -= Input * NewElts;
888 // Find or create a shuffle vector operand to hold this input.
890 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
891 if (InputUsed[OpNo] == Input) {
892 // This input vector is already an operand.
894 } else if (InputUsed[OpNo] == -1U) {
895 // Create a new operand for this input vector.
896 InputUsed[OpNo] = Input;
901 if (OpNo >= array_lengthof(InputUsed)) {
902 // More than two input vectors used! Give up on trying to create a
903 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
904 useBuildVector = true;
908 // Add the mask index for the new shuffle vector.
909 Ops.push_back(Idx + OpNo * NewElts);
912 if (useBuildVector) {
913 EVT EltVT = NewVT.getVectorElementType();
914 SmallVector<SDValue, 16> SVOps;
916 // Extract the input elements by hand.
917 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
918 // The mask element. This indexes into the input.
919 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
921 // The input vector this mask element indexes into.
922 unsigned Input = (unsigned)Idx / NewElts;
924 if (Input >= array_lengthof(Inputs)) {
925 // The mask element is "undef" or indexes off the end of the input.
926 SVOps.push_back(DAG.getUNDEF(EltVT));
930 // Turn the index into an offset from the start of the input vector.
931 Idx -= Input * NewElts;
933 // Extract the vector element by hand.
934 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
935 Inputs[Input], DAG.getIntPtrConstant(Idx)));
938 // Construct the Lo/Hi output using a BUILD_VECTOR.
939 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
940 } else if (InputUsed[0] == -1U) {
941 // No input vectors were used! The result is undefined.
942 Output = DAG.getUNDEF(NewVT);
944 SDValue Op0 = Inputs[InputUsed[0]];
945 // If only one input was used, use an undefined vector for the other.
946 SDValue Op1 = InputUsed[1] == -1U ?
947 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
948 // At least one input vector was used. Create a new shuffle vector.
949 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
957 //===----------------------------------------------------------------------===//
958 // Operand Vector Splitting
959 //===----------------------------------------------------------------------===//
961 /// SplitVectorOperand - This method is called when the specified operand of the
962 /// specified node is found to need vector splitting. At this point, all of the
963 /// result types of the node are known to be legal, but other operands of the
964 /// node may need legalization as well as the specified one.
965 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
966 DEBUG(dbgs() << "Split node operand: ";
969 SDValue Res = SDValue();
971 if (Res.getNode() == 0) {
972 switch (N->getOpcode()) {
975 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
979 llvm_unreachable("Do not know how to split this operator's operand!");
981 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
982 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
983 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
984 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
986 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
992 case ISD::FP_TO_SINT:
993 case ISD::FP_TO_UINT:
994 case ISD::SINT_TO_FP:
995 case ISD::UINT_TO_FP:
997 case ISD::SIGN_EXTEND:
998 case ISD::ZERO_EXTEND:
999 case ISD::ANY_EXTEND:
1000 Res = SplitVecOp_UnaryOp(N);
1005 // If the result is null, the sub-method took care of registering results etc.
1006 if (!Res.getNode()) return false;
1008 // If the result is N, the sub-method updated N in place. Tell the legalizer
1010 if (Res.getNode() == N)
1013 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1014 "Invalid operand expansion");
1016 ReplaceValueWith(SDValue(N, 0), Res);
1020 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1021 // The result has a legal vector type, but the input needs splitting.
1022 EVT ResVT = N->getValueType(0);
1024 DebugLoc dl = N->getDebugLoc();
1025 GetSplitVector(N->getOperand(0), Lo, Hi);
1026 EVT InVT = Lo.getValueType();
1028 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1029 InVT.getVectorNumElements());
1031 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1032 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1034 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1037 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
1038 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
1039 // end up being split all the way down to individual components. Convert the
1040 // split pieces into integers and reassemble.
1042 GetSplitVector(N->getOperand(0), Lo, Hi);
1043 Lo = BitConvertToInteger(Lo);
1044 Hi = BitConvertToInteger(Hi);
1046 if (TLI.isBigEndian())
1049 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), N->getValueType(0),
1050 JoinIntegers(Lo, Hi));
1053 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1054 // We know that the extracted result type is legal. For now, assume the index
1056 EVT SubVT = N->getValueType(0);
1057 SDValue Idx = N->getOperand(1);
1058 DebugLoc dl = N->getDebugLoc();
1060 GetSplitVector(N->getOperand(0), Lo, Hi);
1062 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1063 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1065 if (IdxVal < LoElts) {
1066 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1067 "Extracted subvector crosses vector split!");
1068 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1070 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1071 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1075 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1076 SDValue Vec = N->getOperand(0);
1077 SDValue Idx = N->getOperand(1);
1078 EVT VecVT = Vec.getValueType();
1080 if (isa<ConstantSDNode>(Idx)) {
1081 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1082 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1085 GetSplitVector(Vec, Lo, Hi);
1087 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1089 if (IdxVal < LoElts)
1090 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1091 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1092 DAG.getConstant(IdxVal - LoElts,
1093 Idx.getValueType())), 0);
1096 // Store the vector to the stack.
1097 EVT EltVT = VecVT.getVectorElementType();
1098 DebugLoc dl = N->getDebugLoc();
1099 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1100 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1101 MachinePointerInfo(), false, false, 0);
1103 // Load back the required element.
1104 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1105 return DAG.getExtLoad(ISD::EXTLOAD, N->getValueType(0), dl, Store, StackPtr,
1106 MachinePointerInfo(), EltVT, false, false, 0);
1109 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1110 assert(N->isUnindexed() && "Indexed store of vector?");
1111 assert(OpNo == 1 && "Can only split the stored value");
1112 DebugLoc DL = N->getDebugLoc();
1114 bool isTruncating = N->isTruncatingStore();
1115 SDValue Ch = N->getChain();
1116 SDValue Ptr = N->getBasePtr();
1117 EVT MemoryVT = N->getMemoryVT();
1118 unsigned Alignment = N->getOriginalAlignment();
1119 bool isVol = N->isVolatile();
1120 bool isNT = N->isNonTemporal();
1122 GetSplitVector(N->getOperand(1), Lo, Hi);
1124 EVT LoMemVT, HiMemVT;
1125 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1127 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1130 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1131 LoMemVT, isVol, isNT, Alignment);
1133 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1134 isVol, isNT, Alignment);
1136 // Increment the pointer to the other half.
1137 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1138 DAG.getIntPtrConstant(IncrementSize));
1141 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1142 N->getPointerInfo().getWithOffset(IncrementSize),
1143 HiMemVT, isVol, isNT, Alignment);
1145 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1146 N->getPointerInfo().getWithOffset(IncrementSize),
1147 isVol, isNT, Alignment);
1149 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1152 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1153 DebugLoc DL = N->getDebugLoc();
1155 // The input operands all must have the same type, and we know the result the
1156 // result type is valid. Convert this to a buildvector which extracts all the
1158 // TODO: If the input elements are power-two vectors, we could convert this to
1159 // a new CONCAT_VECTORS node with elements that are half-wide.
1160 SmallVector<SDValue, 32> Elts;
1161 EVT EltVT = N->getValueType(0).getVectorElementType();
1162 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1163 SDValue Op = N->getOperand(op);
1164 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1166 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1167 Op, DAG.getIntPtrConstant(i)));
1172 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
1173 &Elts[0], Elts.size());
1177 //===----------------------------------------------------------------------===//
1178 // Result Vector Widening
1179 //===----------------------------------------------------------------------===//
1181 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1182 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1186 // See if the target wants to custom widen this node.
1187 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1190 SDValue Res = SDValue();
1191 switch (N->getOpcode()) {
1194 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1198 llvm_unreachable("Do not know how to widen the result of this operator!");
1200 case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break;
1201 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1202 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1203 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1204 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1205 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1206 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1207 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1208 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1209 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1210 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1211 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1212 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1213 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1214 case ISD::VECTOR_SHUFFLE:
1215 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1218 Res = WidenVecRes_VSETCC(N);
1225 case ISD::FCOPYSIGN:
1241 Res = WidenVecRes_Binary(N);
1245 Res = WidenVecRes_POWI(N);
1251 Res = WidenVecRes_Shift(N);
1255 case ISD::FP_TO_SINT:
1256 case ISD::FP_TO_UINT:
1257 case ISD::SINT_TO_FP:
1258 case ISD::UINT_TO_FP:
1260 case ISD::SIGN_EXTEND:
1261 case ISD::ZERO_EXTEND:
1262 case ISD::ANY_EXTEND:
1263 Res = WidenVecRes_Convert(N);
1279 Res = WidenVecRes_Unary(N);
1283 // If Res is null, the sub-method took care of registering the result.
1285 SetWidenedVector(SDValue(N, ResNo), Res);
1288 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1289 // Binary op widening.
1290 unsigned Opcode = N->getOpcode();
1291 DebugLoc dl = N->getDebugLoc();
1292 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1293 EVT WidenEltVT = WidenVT.getVectorElementType();
1295 unsigned NumElts = VT.getVectorNumElements();
1296 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1297 NumElts = NumElts / 2;
1298 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1301 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1302 // Operation doesn't trap so just widen as normal.
1303 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1304 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1305 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1308 // No legal vector version so unroll the vector operation and then widen.
1310 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1312 // Since the operation can trap, apply operation on the original vector.
1314 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1315 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1316 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1318 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1319 unsigned ConcatEnd = 0; // Current ConcatOps index.
1320 int Idx = 0; // Current Idx into input vectors.
1322 // NumElts := greatest legal vector size (at most WidenVT)
1323 // while (orig. vector has unhandled elements) {
1324 // take munches of size NumElts from the beginning and add to ConcatOps
1325 // NumElts := next smaller supported vector size or 1
1327 while (CurNumElts != 0) {
1328 while (CurNumElts >= NumElts) {
1329 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1330 DAG.getIntPtrConstant(Idx));
1331 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1332 DAG.getIntPtrConstant(Idx));
1333 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1335 CurNumElts -= NumElts;
1338 NumElts = NumElts / 2;
1339 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1340 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1343 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1344 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1345 InOp1, DAG.getIntPtrConstant(Idx));
1346 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1347 InOp2, DAG.getIntPtrConstant(Idx));
1348 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1355 // Check to see if we have a single operation with the widen type.
1356 if (ConcatEnd == 1) {
1357 VT = ConcatOps[0].getValueType();
1359 return ConcatOps[0];
1362 // while (Some element of ConcatOps is not of type MaxVT) {
1363 // From the end of ConcatOps, collect elements of the same type and put
1364 // them into an op of the next larger supported type
1366 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1367 Idx = ConcatEnd - 1;
1368 VT = ConcatOps[Idx--].getValueType();
1369 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1372 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1376 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1377 } while (!TLI.isTypeLegal(NextVT));
1379 if (!VT.isVector()) {
1380 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1381 SDValue VecOp = DAG.getUNDEF(NextVT);
1382 unsigned NumToInsert = ConcatEnd - Idx - 1;
1383 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1384 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1385 ConcatOps[OpIdx], DAG.getIntPtrConstant(i));
1387 ConcatOps[Idx+1] = VecOp;
1388 ConcatEnd = Idx + 2;
1390 // Vector type, create a CONCAT_VECTORS of type NextVT
1391 SDValue undefVec = DAG.getUNDEF(VT);
1392 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1393 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1394 unsigned RealVals = ConcatEnd - Idx - 1;
1395 unsigned SubConcatEnd = 0;
1396 unsigned SubConcatIdx = Idx + 1;
1397 while (SubConcatEnd < RealVals)
1398 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1399 while (SubConcatEnd < OpsToConcat)
1400 SubConcatOps[SubConcatEnd++] = undefVec;
1401 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1402 NextVT, &SubConcatOps[0],
1404 ConcatEnd = SubConcatIdx + 1;
1408 // Check to see if we have a single operation with the widen type.
1409 if (ConcatEnd == 1) {
1410 VT = ConcatOps[0].getValueType();
1412 return ConcatOps[0];
1415 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1416 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1417 if (NumOps != ConcatEnd ) {
1418 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1419 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1420 ConcatOps[j] = UndefVal;
1422 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps);
1425 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1426 SDValue InOp = N->getOperand(0);
1427 DebugLoc dl = N->getDebugLoc();
1429 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1430 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1432 EVT InVT = InOp.getValueType();
1433 EVT InEltVT = InVT.getVectorElementType();
1434 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1436 unsigned Opcode = N->getOpcode();
1437 unsigned InVTNumElts = InVT.getVectorNumElements();
1439 if (getTypeAction(InVT) == WidenVector) {
1440 InOp = GetWidenedVector(N->getOperand(0));
1441 InVT = InOp.getValueType();
1442 InVTNumElts = InVT.getVectorNumElements();
1443 if (InVTNumElts == WidenNumElts)
1444 return DAG.getNode(Opcode, dl, WidenVT, InOp);
1447 if (TLI.isTypeLegal(InWidenVT)) {
1448 // Because the result and the input are different vector types, widening
1449 // the result could create a legal type but widening the input might make
1450 // it an illegal type that might lead to repeatedly splitting the input
1451 // and then widening it. To avoid this, we widen the input only if
1452 // it results in a legal type.
1453 if (WidenNumElts % InVTNumElts == 0) {
1454 // Widen the input and call convert on the widened input vector.
1455 unsigned NumConcat = WidenNumElts/InVTNumElts;
1456 SmallVector<SDValue, 16> Ops(NumConcat);
1458 SDValue UndefVal = DAG.getUNDEF(InVT);
1459 for (unsigned i = 1; i != NumConcat; ++i)
1461 return DAG.getNode(Opcode, dl, WidenVT,
1462 DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT,
1463 &Ops[0], NumConcat));
1466 if (InVTNumElts % WidenNumElts == 0) {
1467 // Extract the input and convert the shorten input vector.
1468 return DAG.getNode(Opcode, dl, WidenVT,
1469 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT,
1470 InOp, DAG.getIntPtrConstant(0)));
1474 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1475 SmallVector<SDValue, 16> Ops(WidenNumElts);
1476 EVT EltVT = WidenVT.getVectorElementType();
1477 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1479 for (i=0; i < MinElts; ++i)
1480 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
1481 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1482 DAG.getIntPtrConstant(i)));
1484 SDValue UndefVal = DAG.getUNDEF(EltVT);
1485 for (; i < WidenNumElts; ++i)
1488 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1491 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
1492 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1493 SDValue InOp = GetWidenedVector(N->getOperand(0));
1494 SDValue ShOp = N->getOperand(1);
1495 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1498 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1499 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1500 SDValue InOp = GetWidenedVector(N->getOperand(0));
1501 SDValue ShOp = N->getOperand(1);
1503 EVT ShVT = ShOp.getValueType();
1504 if (getTypeAction(ShVT) == WidenVector) {
1505 ShOp = GetWidenedVector(ShOp);
1506 ShVT = ShOp.getValueType();
1508 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
1509 ShVT.getVectorElementType(),
1510 WidenVT.getVectorNumElements());
1511 if (ShVT != ShWidenVT)
1512 ShOp = ModifyToType(ShOp, ShWidenVT);
1514 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1517 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1518 // Unary op widening.
1519 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1520 SDValue InOp = GetWidenedVector(N->getOperand(0));
1521 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1524 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
1525 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1526 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
1527 cast<VTSDNode>(N->getOperand(1))->getVT()
1528 .getVectorElementType(),
1529 WidenVT.getVectorNumElements());
1530 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
1531 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
1532 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
1535 SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
1536 SDValue InOp = N->getOperand(0);
1537 EVT InVT = InOp.getValueType();
1538 EVT VT = N->getValueType(0);
1539 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1540 DebugLoc dl = N->getDebugLoc();
1542 switch (getTypeAction(InVT)) {
1544 assert(false && "Unknown type action!");
1548 case PromoteInteger:
1549 // If the InOp is promoted to the same size, convert it. Otherwise,
1550 // fall out of the switch and widen the promoted input.
1551 InOp = GetPromotedInteger(InOp);
1552 InVT = InOp.getValueType();
1553 if (WidenVT.bitsEq(InVT))
1554 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1559 case ScalarizeVector:
1563 // If the InOp is widened to the same size, convert it. Otherwise, fall
1564 // out of the switch and widen the widened input.
1565 InOp = GetWidenedVector(InOp);
1566 InVT = InOp.getValueType();
1567 if (WidenVT.bitsEq(InVT))
1568 // The input widens to the same size. Convert to the widen value.
1569 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1573 unsigned WidenSize = WidenVT.getSizeInBits();
1574 unsigned InSize = InVT.getSizeInBits();
1575 // x86mmx is not an acceptable vector element type, so don't try.
1576 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
1577 // Determine new input vector type. The new input vector type will use
1578 // the same element type (if its a vector) or use the input type as a
1579 // vector. It is the same size as the type to widen to.
1581 unsigned NewNumElts = WidenSize / InSize;
1582 if (InVT.isVector()) {
1583 EVT InEltVT = InVT.getVectorElementType();
1584 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
1585 WidenSize / InEltVT.getSizeInBits());
1587 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
1590 if (TLI.isTypeLegal(NewInVT)) {
1591 // Because the result and the input are different vector types, widening
1592 // the result could create a legal type but widening the input might make
1593 // it an illegal type that might lead to repeatedly splitting the input
1594 // and then widening it. To avoid this, we widen the input only if
1595 // it results in a legal type.
1596 SmallVector<SDValue, 16> Ops(NewNumElts);
1597 SDValue UndefVal = DAG.getUNDEF(InVT);
1599 for (unsigned i = 1; i < NewNumElts; ++i)
1603 if (InVT.isVector())
1604 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1605 NewInVT, &Ops[0], NewNumElts);
1607 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1608 NewInVT, &Ops[0], NewNumElts);
1609 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, NewVec);
1613 return CreateStackStoreLoad(InOp, WidenVT);
1616 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1617 DebugLoc dl = N->getDebugLoc();
1618 // Build a vector with undefined for the new nodes.
1619 EVT VT = N->getValueType(0);
1620 EVT EltVT = VT.getVectorElementType();
1621 unsigned NumElts = VT.getVectorNumElements();
1623 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1624 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1626 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1627 NewOps.reserve(WidenNumElts);
1628 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1629 NewOps.push_back(DAG.getUNDEF(EltVT));
1631 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1634 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1635 EVT InVT = N->getOperand(0).getValueType();
1636 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1637 DebugLoc dl = N->getDebugLoc();
1638 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1639 unsigned NumOperands = N->getNumOperands();
1641 bool InputWidened = false; // Indicates we need to widen the input.
1642 if (getTypeAction(InVT) != WidenVector) {
1643 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1644 // Add undef vectors to widen to correct length.
1645 unsigned NumConcat = WidenVT.getVectorNumElements() /
1646 InVT.getVectorNumElements();
1647 SDValue UndefVal = DAG.getUNDEF(InVT);
1648 SmallVector<SDValue, 16> Ops(NumConcat);
1649 for (unsigned i=0; i < NumOperands; ++i)
1650 Ops[i] = N->getOperand(i);
1651 for (unsigned i = NumOperands; i != NumConcat; ++i)
1653 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1656 InputWidened = true;
1657 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
1658 // The inputs and the result are widen to the same value.
1660 for (i=1; i < NumOperands; ++i)
1661 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1664 if (i > NumOperands)
1665 // Everything but the first operand is an UNDEF so just return the
1666 // widened first operand.
1667 return GetWidenedVector(N->getOperand(0));
1669 if (NumOperands == 2) {
1670 // Replace concat of two operands with a shuffle.
1671 SmallVector<int, 16> MaskOps(WidenNumElts);
1672 for (unsigned i=0; i < WidenNumElts/2; ++i) {
1674 MaskOps[i+WidenNumElts/2] = i+WidenNumElts;
1676 return DAG.getVectorShuffle(WidenVT, dl,
1677 GetWidenedVector(N->getOperand(0)),
1678 GetWidenedVector(N->getOperand(1)),
1684 // Fall back to use extracts and build vector.
1685 EVT EltVT = WidenVT.getVectorElementType();
1686 unsigned NumInElts = InVT.getVectorNumElements();
1687 SmallVector<SDValue, 16> Ops(WidenNumElts);
1689 for (unsigned i=0; i < NumOperands; ++i) {
1690 SDValue InOp = N->getOperand(i);
1692 InOp = GetWidenedVector(InOp);
1693 for (unsigned j=0; j < NumInElts; ++j)
1694 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1695 DAG.getIntPtrConstant(j));
1697 SDValue UndefVal = DAG.getUNDEF(EltVT);
1698 for (; Idx < WidenNumElts; ++Idx)
1699 Ops[Idx] = UndefVal;
1700 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1703 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1704 DebugLoc dl = N->getDebugLoc();
1705 SDValue InOp = N->getOperand(0);
1706 SDValue RndOp = N->getOperand(3);
1707 SDValue SatOp = N->getOperand(4);
1709 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1710 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1712 EVT InVT = InOp.getValueType();
1713 EVT InEltVT = InVT.getVectorElementType();
1714 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1716 SDValue DTyOp = DAG.getValueType(WidenVT);
1717 SDValue STyOp = DAG.getValueType(InWidenVT);
1718 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1720 unsigned InVTNumElts = InVT.getVectorNumElements();
1721 if (getTypeAction(InVT) == WidenVector) {
1722 InOp = GetWidenedVector(InOp);
1723 InVT = InOp.getValueType();
1724 InVTNumElts = InVT.getVectorNumElements();
1725 if (InVTNumElts == WidenNumElts)
1726 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1730 if (TLI.isTypeLegal(InWidenVT)) {
1731 // Because the result and the input are different vector types, widening
1732 // the result could create a legal type but widening the input might make
1733 // it an illegal type that might lead to repeatedly splitting the input
1734 // and then widening it. To avoid this, we widen the input only if
1735 // it results in a legal type.
1736 if (WidenNumElts % InVTNumElts == 0) {
1737 // Widen the input and call convert on the widened input vector.
1738 unsigned NumConcat = WidenNumElts/InVTNumElts;
1739 SmallVector<SDValue, 16> Ops(NumConcat);
1741 SDValue UndefVal = DAG.getUNDEF(InVT);
1742 for (unsigned i = 1; i != NumConcat; ++i)
1745 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1746 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1750 if (InVTNumElts % WidenNumElts == 0) {
1751 // Extract the input and convert the shorten input vector.
1752 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1753 DAG.getIntPtrConstant(0));
1754 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1759 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1760 SmallVector<SDValue, 16> Ops(WidenNumElts);
1761 EVT EltVT = WidenVT.getVectorElementType();
1762 DTyOp = DAG.getValueType(EltVT);
1763 STyOp = DAG.getValueType(InEltVT);
1765 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1767 for (i=0; i < MinElts; ++i) {
1768 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1769 DAG.getIntPtrConstant(i));
1770 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1774 SDValue UndefVal = DAG.getUNDEF(EltVT);
1775 for (; i < WidenNumElts; ++i)
1778 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1781 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1782 EVT VT = N->getValueType(0);
1783 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1784 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1785 SDValue InOp = N->getOperand(0);
1786 SDValue Idx = N->getOperand(1);
1787 DebugLoc dl = N->getDebugLoc();
1789 if (getTypeAction(InOp.getValueType()) == WidenVector)
1790 InOp = GetWidenedVector(InOp);
1792 EVT InVT = InOp.getValueType();
1794 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
1796 unsigned IdxVal = CIdx->getZExtValue();
1797 // Check if we can just return the input vector after widening.
1798 if (IdxVal == 0 && InVT == WidenVT)
1801 // Check if we can extract from the vector.
1802 unsigned InNumElts = InVT.getVectorNumElements();
1803 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1804 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1807 // We could try widening the input to the right length but for now, extract
1808 // the original elements, fill the rest with undefs and build a vector.
1809 SmallVector<SDValue, 16> Ops(WidenNumElts);
1810 EVT EltVT = VT.getVectorElementType();
1811 EVT IdxVT = Idx.getValueType();
1812 unsigned NumElts = VT.getVectorNumElements();
1815 unsigned IdxVal = CIdx->getZExtValue();
1816 for (i=0; i < NumElts; ++i)
1817 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1818 DAG.getConstant(IdxVal+i, IdxVT));
1820 Ops[0] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, Idx);
1821 for (i=1; i < NumElts; ++i) {
1822 SDValue NewIdx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1823 DAG.getConstant(i, IdxVT));
1824 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, NewIdx);
1828 SDValue UndefVal = DAG.getUNDEF(EltVT);
1829 for (; i < WidenNumElts; ++i)
1831 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1834 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1835 SDValue InOp = GetWidenedVector(N->getOperand(0));
1836 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1837 InOp.getValueType(), InOp,
1838 N->getOperand(1), N->getOperand(2));
1841 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1842 LoadSDNode *LD = cast<LoadSDNode>(N);
1843 ISD::LoadExtType ExtType = LD->getExtensionType();
1846 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1847 if (ExtType != ISD::NON_EXTLOAD)
1848 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
1850 Result = GenWidenVectorLoads(LdChain, LD);
1852 // If we generate a single load, we can use that for the chain. Otherwise,
1853 // build a factor node to remember the multiple loads are independent and
1856 if (LdChain.size() == 1)
1857 NewChain = LdChain[0];
1859 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other,
1860 &LdChain[0], LdChain.size());
1862 // Modified the chain - switch anything that used the old chain to use
1864 ReplaceValueWith(SDValue(N, 1), NewChain);
1869 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1870 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1871 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1872 WidenVT, N->getOperand(0));
1875 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1876 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1877 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1879 SDValue Cond1 = N->getOperand(0);
1880 EVT CondVT = Cond1.getValueType();
1881 if (CondVT.isVector()) {
1882 EVT CondEltVT = CondVT.getVectorElementType();
1883 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
1884 CondEltVT, WidenNumElts);
1885 if (getTypeAction(CondVT) == WidenVector)
1886 Cond1 = GetWidenedVector(Cond1);
1888 if (Cond1.getValueType() != CondWidenVT)
1889 Cond1 = ModifyToType(Cond1, CondWidenVT);
1892 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1893 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1894 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1895 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
1896 WidenVT, Cond1, InOp1, InOp2);
1899 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1900 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1901 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1902 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1903 InOp1.getValueType(), N->getOperand(0),
1904 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1907 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
1908 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1909 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1910 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1911 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
1912 InOp1, InOp2, N->getOperand(2));
1915 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1916 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1917 return DAG.getUNDEF(WidenVT);
1920 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
1921 EVT VT = N->getValueType(0);
1922 DebugLoc dl = N->getDebugLoc();
1924 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1925 unsigned NumElts = VT.getVectorNumElements();
1926 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1928 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1929 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1931 // Adjust mask based on new input vector length.
1932 SmallVector<int, 16> NewMask;
1933 for (unsigned i = 0; i != NumElts; ++i) {
1934 int Idx = N->getMaskElt(i);
1935 if (Idx < (int)NumElts)
1936 NewMask.push_back(Idx);
1938 NewMask.push_back(Idx - NumElts + WidenNumElts);
1940 for (unsigned i = NumElts; i != WidenNumElts; ++i)
1941 NewMask.push_back(-1);
1942 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
1945 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1946 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1947 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1949 SDValue InOp1 = N->getOperand(0);
1950 EVT InVT = InOp1.getValueType();
1951 assert(InVT.isVector() && "can not widen non vector type");
1952 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
1953 InVT.getVectorElementType(), WidenNumElts);
1954 InOp1 = GetWidenedVector(InOp1);
1955 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1957 // Assume that the input and output will be widen appropriately. If not,
1958 // we will have to unroll it at some point.
1959 assert(InOp1.getValueType() == WidenInVT &&
1960 InOp2.getValueType() == WidenInVT &&
1961 "Input not widened to expected type!");
1962 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(),
1963 WidenVT, InOp1, InOp2, N->getOperand(2));
1967 //===----------------------------------------------------------------------===//
1968 // Widen Vector Operand
1969 //===----------------------------------------------------------------------===//
1970 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
1971 DEBUG(dbgs() << "Widen node operand " << ResNo << ": ";
1974 SDValue Res = SDValue();
1976 switch (N->getOpcode()) {
1979 dbgs() << "WidenVectorOperand op #" << ResNo << ": ";
1983 llvm_unreachable("Do not know how to widen this operator's operand!");
1985 case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break;
1986 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
1987 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
1988 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
1989 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
1992 case ISD::FP_TO_SINT:
1993 case ISD::FP_TO_UINT:
1994 case ISD::SINT_TO_FP:
1995 case ISD::UINT_TO_FP:
1997 case ISD::SIGN_EXTEND:
1998 case ISD::ZERO_EXTEND:
1999 case ISD::ANY_EXTEND:
2000 Res = WidenVecOp_Convert(N);
2004 // If Res is null, the sub-method took care of registering the result.
2005 if (!Res.getNode()) return false;
2007 // If the result is N, the sub-method updated N in place. Tell the legalizer
2009 if (Res.getNode() == N)
2013 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2014 "Invalid operand expansion");
2016 ReplaceValueWith(SDValue(N, 0), Res);
2020 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2021 // Since the result is legal and the input is illegal, it is unlikely
2022 // that we can fix the input to a legal type so unroll the convert
2023 // into some scalar code and create a nasty build vector.
2024 EVT VT = N->getValueType(0);
2025 EVT EltVT = VT.getVectorElementType();
2026 DebugLoc dl = N->getDebugLoc();
2027 unsigned NumElts = VT.getVectorNumElements();
2028 SDValue InOp = N->getOperand(0);
2029 if (getTypeAction(InOp.getValueType()) == WidenVector)
2030 InOp = GetWidenedVector(InOp);
2031 EVT InVT = InOp.getValueType();
2032 EVT InEltVT = InVT.getVectorElementType();
2034 unsigned Opcode = N->getOpcode();
2035 SmallVector<SDValue, 16> Ops(NumElts);
2036 for (unsigned i=0; i < NumElts; ++i)
2037 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2038 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2039 DAG.getIntPtrConstant(i)));
2041 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2044 SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) {
2045 EVT VT = N->getValueType(0);
2046 SDValue InOp = GetWidenedVector(N->getOperand(0));
2047 EVT InWidenVT = InOp.getValueType();
2048 DebugLoc dl = N->getDebugLoc();
2050 // Check if we can convert between two legal vector types and extract.
2051 unsigned InWidenSize = InWidenVT.getSizeInBits();
2052 unsigned Size = VT.getSizeInBits();
2053 // x86mmx is not an acceptable vector element type, so don't try.
2054 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2055 unsigned NewNumElts = InWidenSize / Size;
2056 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2057 if (TLI.isTypeLegal(NewVT)) {
2058 SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp);
2059 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2060 DAG.getIntPtrConstant(0));
2064 return CreateStackStoreLoad(InOp, VT);
2067 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2068 // If the input vector is not legal, it is likely that we will not find a
2069 // legal vector of the same size. Replace the concatenate vector with a
2070 // nasty build vector.
2071 EVT VT = N->getValueType(0);
2072 EVT EltVT = VT.getVectorElementType();
2073 DebugLoc dl = N->getDebugLoc();
2074 unsigned NumElts = VT.getVectorNumElements();
2075 SmallVector<SDValue, 16> Ops(NumElts);
2077 EVT InVT = N->getOperand(0).getValueType();
2078 unsigned NumInElts = InVT.getVectorNumElements();
2081 unsigned NumOperands = N->getNumOperands();
2082 for (unsigned i=0; i < NumOperands; ++i) {
2083 SDValue InOp = N->getOperand(i);
2084 if (getTypeAction(InOp.getValueType()) == WidenVector)
2085 InOp = GetWidenedVector(InOp);
2086 for (unsigned j=0; j < NumInElts; ++j)
2087 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2088 DAG.getIntPtrConstant(j));
2090 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2093 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2094 SDValue InOp = GetWidenedVector(N->getOperand(0));
2095 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
2096 N->getValueType(0), InOp, N->getOperand(1));
2099 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2100 SDValue InOp = GetWidenedVector(N->getOperand(0));
2101 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
2102 N->getValueType(0), InOp, N->getOperand(1));
2105 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2106 // We have to widen the value but we want only to store the original
2108 StoreSDNode *ST = cast<StoreSDNode>(N);
2110 SmallVector<SDValue, 16> StChain;
2111 if (ST->isTruncatingStore())
2112 GenWidenVectorTruncStores(StChain, ST);
2114 GenWidenVectorStores(StChain, ST);
2116 if (StChain.size() == 1)
2119 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(),
2120 MVT::Other,&StChain[0],StChain.size());
2123 //===----------------------------------------------------------------------===//
2124 // Vector Widening Utilities
2125 //===----------------------------------------------------------------------===//
2127 // Utility function to find the type to chop up a widen vector for load/store
2128 // TLI: Target lowering used to determine legal types.
2129 // Width: Width left need to load/store.
2130 // WidenVT: The widen vector type to load to/store from
2131 // Align: If 0, don't allow use of a wider type
2132 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2134 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2135 unsigned Width, EVT WidenVT,
2136 unsigned Align = 0, unsigned WidenEx = 0) {
2137 EVT WidenEltVT = WidenVT.getVectorElementType();
2138 unsigned WidenWidth = WidenVT.getSizeInBits();
2139 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2140 unsigned AlignInBits = Align*8;
2142 // If we have one element to load/store, return it.
2143 EVT RetVT = WidenEltVT;
2144 if (Width == WidenEltWidth)
2147 // See if there is larger legal integer than the element type to load/store
2149 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2150 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2151 EVT MemVT((MVT::SimpleValueType) VT);
2152 unsigned MemVTWidth = MemVT.getSizeInBits();
2153 if (MemVT.getSizeInBits() <= WidenEltWidth)
2155 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2156 (MemVTWidth <= Width ||
2157 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2163 // See if there is a larger vector type to load/store that has the same vector
2164 // element type and is evenly divisible with the WidenVT.
2165 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2166 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2167 EVT MemVT = (MVT::SimpleValueType) VT;
2168 unsigned MemVTWidth = MemVT.getSizeInBits();
2169 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2170 (WidenWidth % MemVTWidth) == 0 &&
2171 (MemVTWidth <= Width ||
2172 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2173 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2181 // Builds a vector type from scalar loads
2182 // VecTy: Resulting Vector type
2183 // LDOps: Load operators to build a vector type
2184 // [Start,End) the list of loads to use.
2185 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2186 SmallVector<SDValue, 16>& LdOps,
2187 unsigned Start, unsigned End) {
2188 DebugLoc dl = LdOps[Start].getDebugLoc();
2189 EVT LdTy = LdOps[Start].getValueType();
2190 unsigned Width = VecTy.getSizeInBits();
2191 unsigned NumElts = Width / LdTy.getSizeInBits();
2192 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2195 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2197 for (unsigned i = Start + 1; i != End; ++i) {
2198 EVT NewLdTy = LdOps[i].getValueType();
2199 if (NewLdTy != LdTy) {
2200 NumElts = Width / NewLdTy.getSizeInBits();
2201 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2202 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp);
2203 // Readjust position and vector position based on new load type
2204 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2207 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2208 DAG.getIntPtrConstant(Idx++));
2210 return DAG.getNode(ISD::BIT_CONVERT, dl, VecTy, VecOp);
2213 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,
2215 // The strategy assumes that we can efficiently load powers of two widths.
2216 // The routines chops the vector into the largest vector loads with the same
2217 // element type or scalar loads and then recombines it to the widen vector
2219 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2220 unsigned WidenWidth = WidenVT.getSizeInBits();
2221 EVT LdVT = LD->getMemoryVT();
2222 DebugLoc dl = LD->getDebugLoc();
2223 assert(LdVT.isVector() && WidenVT.isVector());
2224 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2227 SDValue Chain = LD->getChain();
2228 SDValue BasePtr = LD->getBasePtr();
2229 unsigned Align = LD->getAlignment();
2230 bool isVolatile = LD->isVolatile();
2231 bool isNonTemporal = LD->isNonTemporal();
2233 int LdWidth = LdVT.getSizeInBits();
2234 int WidthDiff = WidenWidth - LdWidth; // Difference
2235 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
2237 // Find the vector type that can load from.
2238 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2239 int NewVTWidth = NewVT.getSizeInBits();
2240 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
2241 isVolatile, isNonTemporal, Align);
2242 LdChain.push_back(LdOp.getValue(1));
2244 // Check if we can load the element with one instruction
2245 if (LdWidth <= NewVTWidth) {
2246 if (!NewVT.isVector()) {
2247 unsigned NumElts = WidenWidth / NewVTWidth;
2248 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2249 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2250 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, VecOp);
2252 if (NewVT == WidenVT)
2255 assert(WidenWidth % NewVTWidth == 0);
2256 unsigned NumConcat = WidenWidth / NewVTWidth;
2257 SmallVector<SDValue, 16> ConcatOps(NumConcat);
2258 SDValue UndefVal = DAG.getUNDEF(NewVT);
2259 ConcatOps[0] = LdOp;
2260 for (unsigned i = 1; i != NumConcat; ++i)
2261 ConcatOps[i] = UndefVal;
2262 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
2266 // Load vector by using multiple loads from largest vector to scalar
2267 SmallVector<SDValue, 16> LdOps;
2268 LdOps.push_back(LdOp);
2270 LdWidth -= NewVTWidth;
2271 unsigned Offset = 0;
2273 while (LdWidth > 0) {
2274 unsigned Increment = NewVTWidth / 8;
2275 Offset += Increment;
2276 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2277 DAG.getIntPtrConstant(Increment));
2279 if (LdWidth < NewVTWidth) {
2280 // Our current type we are using is too large, find a better size
2281 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2282 NewVTWidth = NewVT.getSizeInBits();
2285 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2286 LD->getPointerInfo().getWithOffset(Offset),
2288 isNonTemporal, MinAlign(Align, Increment));
2289 LdChain.push_back(LdOp.getValue(1));
2290 LdOps.push_back(LdOp);
2292 LdWidth -= NewVTWidth;
2295 // Build the vector from the loads operations
2296 unsigned End = LdOps.size();
2297 if (!LdOps[0].getValueType().isVector())
2298 // All the loads are scalar loads.
2299 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
2301 // If the load contains vectors, build the vector using concat vector.
2302 // All of the vectors used to loads are power of 2 and the scalars load
2303 // can be combined to make a power of 2 vector.
2304 SmallVector<SDValue, 16> ConcatOps(End);
2307 EVT LdTy = LdOps[i].getValueType();
2308 // First combine the scalar loads to a vector
2309 if (!LdTy.isVector()) {
2310 for (--i; i >= 0; --i) {
2311 LdTy = LdOps[i].getValueType();
2312 if (LdTy.isVector())
2315 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
2317 ConcatOps[--Idx] = LdOps[i];
2318 for (--i; i >= 0; --i) {
2319 EVT NewLdTy = LdOps[i].getValueType();
2320 if (NewLdTy != LdTy) {
2321 // Create a larger vector
2322 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2323 &ConcatOps[Idx], End - Idx);
2327 ConcatOps[--Idx] = LdOps[i];
2330 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
2331 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2332 &ConcatOps[Idx], End - Idx);
2334 // We need to fill the rest with undefs to build the vector
2335 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
2336 SmallVector<SDValue, 16> WidenOps(NumOps);
2337 SDValue UndefVal = DAG.getUNDEF(LdTy);
2340 for (; i != End-Idx; ++i)
2341 WidenOps[i] = ConcatOps[Idx+i];
2342 for (; i != NumOps; ++i)
2343 WidenOps[i] = UndefVal;
2345 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
2349 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,
2351 ISD::LoadExtType ExtType) {
2352 // For extension loads, it may not be more efficient to chop up the vector
2353 // and then extended it. Instead, we unroll the load and build a new vector.
2354 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2355 EVT LdVT = LD->getMemoryVT();
2356 DebugLoc dl = LD->getDebugLoc();
2357 assert(LdVT.isVector() && WidenVT.isVector());
2360 SDValue Chain = LD->getChain();
2361 SDValue BasePtr = LD->getBasePtr();
2362 unsigned Align = LD->getAlignment();
2363 bool isVolatile = LD->isVolatile();
2364 bool isNonTemporal = LD->isNonTemporal();
2366 EVT EltVT = WidenVT.getVectorElementType();
2367 EVT LdEltVT = LdVT.getVectorElementType();
2368 unsigned NumElts = LdVT.getVectorNumElements();
2370 // Load each element and widen
2371 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2372 SmallVector<SDValue, 16> Ops(WidenNumElts);
2373 unsigned Increment = LdEltVT.getSizeInBits() / 8;
2374 Ops[0] = DAG.getExtLoad(ExtType, EltVT, dl, Chain, BasePtr,
2375 LD->getPointerInfo(),
2376 LdEltVT, isVolatile, isNonTemporal, Align);
2377 LdChain.push_back(Ops[0].getValue(1));
2378 unsigned i = 0, Offset = Increment;
2379 for (i=1; i < NumElts; ++i, Offset += Increment) {
2380 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2381 BasePtr, DAG.getIntPtrConstant(Offset));
2382 Ops[i] = DAG.getExtLoad(ExtType, EltVT, dl, Chain, NewBasePtr,
2383 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
2384 isVolatile, isNonTemporal, Align);
2385 LdChain.push_back(Ops[i].getValue(1));
2388 // Fill the rest with undefs
2389 SDValue UndefVal = DAG.getUNDEF(EltVT);
2390 for (; i != WidenNumElts; ++i)
2393 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
2397 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2399 // The strategy assumes that we can efficiently store powers of two widths.
2400 // The routines chops the vector into the largest vector stores with the same
2401 // element type or scalar stores.
2402 SDValue Chain = ST->getChain();
2403 SDValue BasePtr = ST->getBasePtr();
2404 unsigned Align = ST->getAlignment();
2405 bool isVolatile = ST->isVolatile();
2406 bool isNonTemporal = ST->isNonTemporal();
2407 SDValue ValOp = GetWidenedVector(ST->getValue());
2408 DebugLoc dl = ST->getDebugLoc();
2410 EVT StVT = ST->getMemoryVT();
2411 unsigned StWidth = StVT.getSizeInBits();
2412 EVT ValVT = ValOp.getValueType();
2413 unsigned ValWidth = ValVT.getSizeInBits();
2414 EVT ValEltVT = ValVT.getVectorElementType();
2415 unsigned ValEltWidth = ValEltVT.getSizeInBits();
2416 assert(StVT.getVectorElementType() == ValEltVT);
2418 int Idx = 0; // current index to store
2419 unsigned Offset = 0; // offset from base to store
2420 while (StWidth != 0) {
2421 // Find the largest vector type we can store with
2422 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
2423 unsigned NewVTWidth = NewVT.getSizeInBits();
2424 unsigned Increment = NewVTWidth / 8;
2425 if (NewVT.isVector()) {
2426 unsigned NumVTElts = NewVT.getVectorNumElements();
2428 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2429 DAG.getIntPtrConstant(Idx));
2430 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2431 ST->getPointerInfo().getWithOffset(Offset),
2432 isVolatile, isNonTemporal,
2433 MinAlign(Align, Offset)));
2434 StWidth -= NewVTWidth;
2435 Offset += Increment;
2437 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2438 DAG.getIntPtrConstant(Increment));
2439 } while (StWidth != 0 && StWidth >= NewVTWidth);
2441 // Cast the vector to the scalar type we can store
2442 unsigned NumElts = ValWidth / NewVTWidth;
2443 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2444 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, ValOp);
2445 // Readjust index position based on new vector type
2446 Idx = Idx * ValEltWidth / NewVTWidth;
2448 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2449 DAG.getIntPtrConstant(Idx++));
2450 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2451 ST->getPointerInfo().getWithOffset(Offset),
2452 isVolatile, isNonTemporal,
2453 MinAlign(Align, Offset)));
2454 StWidth -= NewVTWidth;
2455 Offset += Increment;
2456 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2457 DAG.getIntPtrConstant(Increment));
2458 } while (StWidth != 0 && StWidth >= NewVTWidth);
2459 // Restore index back to be relative to the original widen element type
2460 Idx = Idx * NewVTWidth / ValEltWidth;
2466 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,
2468 // For extension loads, it may not be more efficient to truncate the vector
2469 // and then store it. Instead, we extract each element and then store it.
2470 SDValue Chain = ST->getChain();
2471 SDValue BasePtr = ST->getBasePtr();
2472 unsigned Align = ST->getAlignment();
2473 bool isVolatile = ST->isVolatile();
2474 bool isNonTemporal = ST->isNonTemporal();
2475 SDValue ValOp = GetWidenedVector(ST->getValue());
2476 DebugLoc dl = ST->getDebugLoc();
2478 EVT StVT = ST->getMemoryVT();
2479 EVT ValVT = ValOp.getValueType();
2481 // It must be true that we the widen vector type is bigger than where
2482 // we need to store.
2483 assert(StVT.isVector() && ValOp.getValueType().isVector());
2484 assert(StVT.bitsLT(ValOp.getValueType()));
2486 // For truncating stores, we can not play the tricks of chopping legal
2487 // vector types and bit cast it to the right type. Instead, we unroll
2489 EVT StEltVT = StVT.getVectorElementType();
2490 EVT ValEltVT = ValVT.getVectorElementType();
2491 unsigned Increment = ValEltVT.getSizeInBits() / 8;
2492 unsigned NumElts = StVT.getVectorNumElements();
2493 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2494 DAG.getIntPtrConstant(0));
2495 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
2496 ST->getPointerInfo(), StEltVT,
2497 isVolatile, isNonTemporal, Align));
2498 unsigned Offset = Increment;
2499 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
2500 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2501 BasePtr, DAG.getIntPtrConstant(Offset));
2502 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2503 DAG.getIntPtrConstant(0));
2504 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
2505 ST->getPointerInfo().getWithOffset(Offset),
2506 StEltVT, isVolatile, isNonTemporal,
2507 MinAlign(Align, Offset)));
2511 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2512 /// input vector must have the same element type as NVT.
2513 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
2514 // Note that InOp might have been widened so it might already have
2515 // the right width or it might need be narrowed.
2516 EVT InVT = InOp.getValueType();
2517 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2518 "input and widen element type must match");
2519 DebugLoc dl = InOp.getDebugLoc();
2521 // Check if InOp already has the right width.
2525 unsigned InNumElts = InVT.getVectorNumElements();
2526 unsigned WidenNumElts = NVT.getVectorNumElements();
2527 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2528 unsigned NumConcat = WidenNumElts / InNumElts;
2529 SmallVector<SDValue, 16> Ops(NumConcat);
2530 SDValue UndefVal = DAG.getUNDEF(InVT);
2532 for (unsigned i = 1; i != NumConcat; ++i)
2535 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2538 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2539 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2540 DAG.getIntPtrConstant(0));
2542 // Fall back to extract and build.
2543 SmallVector<SDValue, 16> Ops(WidenNumElts);
2544 EVT EltVT = NVT.getVectorElementType();
2545 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2547 for (Idx = 0; Idx < MinNumElts; ++Idx)
2548 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2549 DAG.getIntPtrConstant(Idx));
2551 SDValue UndefVal = DAG.getUNDEF(EltVT);
2552 for ( ; Idx < WidenNumElts; ++Idx)
2553 Ops[Idx] = UndefVal;
2554 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);