1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in multiple vectors of a smaller type. For example,
19 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
26 //===----------------------------------------------------------------------===//
27 // Result Vector Scalarization: <1 x ty> -> ty.
28 //===----------------------------------------------------------------------===//
30 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
31 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
33 SDValue R = SDValue();
35 switch (N->getOpcode()) {
38 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
39 N->dump(&DAG); cerr << "\n";
41 assert(0 && "Do not know how to scalarize the result of this operator!");
44 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
45 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
46 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
47 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
48 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
49 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
50 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
51 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
52 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
70 case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break;
87 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
90 // If R is null, the sub-method took care of registering the result.
92 SetScalarizedVector(SDValue(N, ResNo), R);
95 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
96 SDValue LHS = GetScalarizedVector(N->getOperand(0));
97 SDValue RHS = GetScalarizedVector(N->getOperand(1));
98 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
101 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
102 MVT NewVT = N->getValueType(0).getVectorElementType();
103 return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
106 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
107 SDValue Op = GetScalarizedVector(N->getOperand(0));
108 return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
111 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
112 // The value to insert may have a wider type than the vector element type,
113 // so be sure to truncate it to the element type if necessary.
114 SDValue Op = N->getOperand(1);
115 MVT EltVT = N->getValueType(0).getVectorElementType();
116 if (Op.getValueType() != EltVT)
117 // FIXME: Can this happen for floating point types?
118 Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
122 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
123 assert(N->isUnindexed() && "Indexed vector load?");
125 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getExtensionType(),
126 N->getValueType(0).getVectorElementType(),
127 N->getChain(), N->getBasePtr(),
128 DAG.getNode(ISD::UNDEF,
129 N->getBasePtr().getValueType()),
130 N->getSrcValue(), N->getSrcValueOffset(),
131 N->getMemoryVT().getVectorElementType(),
132 N->isVolatile(), N->getAlignment());
134 // Legalized the chain result - switch anything that used the old chain to
136 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
140 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
141 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
142 MVT DestVT = TLI.getTypeToTransformTo(N->getValueType(0));
143 SDValue Op = GetScalarizedVector(N->getOperand(0));
144 return DAG.getNode(N->getOpcode(), DestVT, Op);
147 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
148 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
151 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
152 SDValue LHS = GetScalarizedVector(N->getOperand(1));
153 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
154 GetScalarizedVector(N->getOperand(2)));
157 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
158 // Figure out if the scalar is the LHS or RHS and return it.
159 SDValue Arg = N->getOperand(2).getOperand(0);
160 if (Arg.getOpcode() == ISD::UNDEF)
161 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
162 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
163 return GetScalarizedVector(N->getOperand(Op));
166 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
167 MVT NewVT = N->getValueType(0).getVectorElementType();
168 SDValue LHS = GetScalarizedVector(N->getOperand(0));
169 SDValue RHS = GetScalarizedVector(N->getOperand(1));
170 LHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, RHS,
173 DAG.getNode(ISD::SELECT, NewVT, LHS,
174 DAG.getConstant(APInt::getAllOnesValue(NewVT.getSizeInBits()),
176 DAG.getConstant(0ULL, NewVT));
180 //===----------------------------------------------------------------------===//
181 // Operand Vector Scalarization <1 x ty> -> ty.
182 //===----------------------------------------------------------------------===//
184 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
185 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
187 SDValue Res = SDValue();
189 if (Res.getNode() == 0) {
190 switch (N->getOpcode()) {
193 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
194 N->dump(&DAG); cerr << "\n";
196 assert(0 && "Do not know how to scalarize this operator's operand!");
199 case ISD::BIT_CONVERT:
200 Res = ScalarizeVecOp_BIT_CONVERT(N); break;
202 case ISD::EXTRACT_VECTOR_ELT:
203 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
206 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
210 // If the result is null, the sub-method took care of registering results etc.
211 if (!Res.getNode()) return false;
213 // If the result is N, the sub-method updated N in place. Check to see if any
214 // operands are new, and if so, mark them.
215 if (Res.getNode() == N) {
216 // Mark N as new and remark N and its operands. This allows us to correctly
217 // revisit N if it needs another step of promotion and allows us to visit
218 // any new operands to N.
223 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
224 "Invalid operand expansion");
226 ReplaceValueWith(SDValue(N, 0), Res);
230 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
231 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
232 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
233 SDValue Elt = GetScalarizedVector(N->getOperand(0));
234 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
237 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
238 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
240 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
241 return GetScalarizedVector(N->getOperand(0));
244 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
245 /// scalarized, it must be <1 x ty>. Just store the element.
246 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
247 assert(N->isUnindexed() && "Indexed store of one-element vector?");
248 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
250 if (N->isTruncatingStore())
251 return DAG.getTruncStore(N->getChain(),
252 GetScalarizedVector(N->getOperand(1)),
254 N->getSrcValue(), N->getSrcValueOffset(),
255 N->getMemoryVT().getVectorElementType(),
256 N->isVolatile(), N->getAlignment());
258 return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
259 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
260 N->isVolatile(), N->getAlignment());
264 //===----------------------------------------------------------------------===//
265 // Result Vector Splitting
266 //===----------------------------------------------------------------------===//
268 /// SplitVectorResult - This method is called when the specified result of the
269 /// specified node is found to need vector splitting. At this point, the node
270 /// may also have invalid operands or may have other results that need
271 /// legalization, we just know that (at least) one result needs vector
273 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
274 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
277 switch (N->getOpcode()) {
280 cerr << "SplitVectorResult #" << ResNo << ": ";
281 N->dump(&DAG); cerr << "\n";
283 assert(0 && "Do not know how to split the result of this operator!");
286 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
287 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
288 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
289 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
291 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
292 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
293 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
294 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
295 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
296 case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
297 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
298 case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
312 case ISD::FNEARBYINT:
313 case ISD::FP_TO_SINT:
314 case ISD::FP_TO_UINT:
315 case ISD::SINT_TO_FP:
316 case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break;
333 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
336 // If Lo/Hi is null, the sub-method took care of registering results etc.
338 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
341 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
343 SDValue LHSLo, LHSHi;
344 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
345 SDValue RHSLo, RHSHi;
346 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
348 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
349 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
352 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
354 // We know the result is a vector. The input may be either a vector or a
357 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
359 SDValue InOp = N->getOperand(0);
360 MVT InVT = InOp.getValueType();
362 // Handle some special cases efficiently.
363 switch (getTypeAction(InVT)) {
365 assert(false && "Unknown type action!");
369 case ScalarizeVector:
373 // A scalar to vector conversion, where the scalar needs expansion.
374 // If the vector is being split in two then we can just convert the
377 GetExpandedOp(InOp, Lo, Hi);
378 if (TLI.isBigEndian())
380 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
381 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
386 // If the input is a vector that needs to be split, convert each split
387 // piece of the input now.
388 GetSplitVector(InOp, Lo, Hi);
389 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
390 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
394 // In the general case, convert the input to an integer and split it by hand.
395 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
396 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
397 if (TLI.isBigEndian())
398 std::swap(LoIntVT, HiIntVT);
400 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
402 if (TLI.isBigEndian())
404 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
405 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
408 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
411 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
412 unsigned LoNumElts = LoVT.getVectorNumElements();
413 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
414 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
416 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
417 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
420 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
422 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
423 unsigned NumSubvectors = N->getNumOperands() / 2;
424 if (NumSubvectors == 1) {
425 Lo = N->getOperand(0);
426 Hi = N->getOperand(1);
431 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
433 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
434 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
436 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
437 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
440 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
442 GetSplitVector(N->getOperand(0), Lo, Hi);
443 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
444 Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
447 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
449 SDValue Vec = N->getOperand(0);
450 SDValue Elt = N->getOperand(1);
451 SDValue Idx = N->getOperand(2);
452 GetSplitVector(Vec, Lo, Hi);
454 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
455 unsigned IdxVal = CIdx->getZExtValue();
456 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
457 if (IdxVal < LoNumElts)
458 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx);
460 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt,
461 DAG.getIntPtrConstant(IdxVal - LoNumElts));
465 // Spill the vector to the stack.
466 MVT VecVT = Vec.getValueType();
467 MVT EltVT = VecVT.getVectorElementType();
468 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
469 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
471 // Store the new element. This may be larger than the vector element type,
472 // so use a truncating store.
473 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
474 Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
476 // Reload the vector from the stack.
477 SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
480 SplitVecRes_LOAD(cast<LoadSDNode>(Load.getNode()), Lo, Hi);
483 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
485 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
487 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
489 ISD::LoadExtType ExtType = LD->getExtensionType();
490 SDValue Ch = LD->getChain();
491 SDValue Ptr = LD->getBasePtr();
492 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
493 const Value *SV = LD->getSrcValue();
494 int SVOffset = LD->getSrcValueOffset();
495 MVT MemoryVT = LD->getMemoryVT();
496 unsigned Alignment = LD->getAlignment();
497 bool isVolatile = LD->isVolatile();
499 MVT LoMemVT, HiMemVT;
500 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
502 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, Ch, Ptr, Offset,
503 SV, SVOffset, LoMemVT, isVolatile, Alignment);
505 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
506 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
507 DAG.getIntPtrConstant(IncrementSize));
508 SVOffset += IncrementSize;
509 Alignment = MinAlign(Alignment, IncrementSize);
510 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, Ch, Ptr, Offset,
511 SV, SVOffset, HiMemVT, isVolatile, Alignment);
513 // Build a factor node to remember that this load is independent of the
515 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
518 // Legalized the chain result - switch anything that used the old chain to
520 ReplaceValueWith(SDValue(LD, 1), Ch);
523 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
525 // Get the dest types - they may not match the input types, e.g. int_to_fp.
527 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
530 MVT InVT = N->getOperand(0).getValueType();
531 switch (getTypeAction(InVT)) {
532 default: assert(0 && "Unexpected type action!");
534 assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
535 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
536 LoVT.getVectorNumElements());
537 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
538 DAG.getIntPtrConstant(0));
539 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
540 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
544 GetSplitVector(N->getOperand(0), Lo, Hi);
548 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
549 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
552 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
554 // Build the low part.
555 SDValue Mask = N->getOperand(2);
556 SmallVector<SDValue, 16> Ops;
558 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
559 MVT EltVT = LoVT.getVectorElementType();
560 unsigned LoNumElts = LoVT.getVectorNumElements();
561 unsigned NumElements = Mask.getNumOperands();
563 // Insert all of the elements from the input that are needed. We use
564 // buildvector of extractelement here because the input vectors will have
565 // to be legalized, so this makes the code simpler.
566 for (unsigned i = 0; i != LoNumElts; ++i) {
567 SDValue Arg = Mask.getOperand(i);
568 if (Arg.getOpcode() == ISD::UNDEF) {
569 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
571 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
572 SDValue InVec = N->getOperand(0);
573 if (Idx >= NumElements) {
574 InVec = N->getOperand(1);
577 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
578 DAG.getIntPtrConstant(Idx)));
581 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size());
584 for (unsigned i = LoNumElts; i != NumElements; ++i) {
585 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
586 SDValue InVec = N->getOperand(0);
587 if (Idx >= NumElements) {
588 InVec = N->getOperand(1);
591 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
592 DAG.getIntPtrConstant(Idx)));
594 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
597 void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
600 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
602 SDValue LL, LH, RL, RH;
603 GetSplitVector(N->getOperand(0), LL, LH);
604 GetSplitVector(N->getOperand(1), RL, RH);
606 Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2));
607 Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2));
611 //===----------------------------------------------------------------------===//
612 // Operand Vector Splitting
613 //===----------------------------------------------------------------------===//
615 /// SplitVectorOperand - This method is called when the specified operand of the
616 /// specified node is found to need vector splitting. At this point, all of the
617 /// result types of the node are known to be legal, but other operands of the
618 /// node may need legalization as well as the specified one.
619 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
620 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
621 SDValue Res = SDValue();
623 if (Res.getNode() == 0) {
624 switch (N->getOpcode()) {
627 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
628 N->dump(&DAG); cerr << "\n";
630 assert(0 && "Do not know how to split this operator's operand!");
633 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
634 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
635 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
636 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N),
638 case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break;
642 // If the result is null, the sub-method took care of registering results etc.
643 if (!Res.getNode()) return false;
645 // If the result is N, the sub-method updated N in place. Check to see if any
646 // operands are new, and if so, mark them.
647 if (Res.getNode() == N) {
648 // Mark N as new and remark N and its operands. This allows us to correctly
649 // revisit N if it needs another step of promotion and allows us to visit
650 // any new operands to N.
655 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
656 "Invalid operand expansion");
658 ReplaceValueWith(SDValue(N, 0), Res);
662 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
663 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
664 // end up being split all the way down to individual components. Convert the
665 // split pieces into integers and reassemble.
667 GetSplitVector(N->getOperand(0), Lo, Hi);
668 Lo = BitConvertToInteger(Lo);
669 Hi = BitConvertToInteger(Hi);
671 if (TLI.isBigEndian())
674 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
675 JoinIntegers(Lo, Hi));
678 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
679 // We know that the extracted result type is legal. For now, assume the index
681 MVT SubVT = N->getValueType(0);
682 SDValue Idx = N->getOperand(1);
684 GetSplitVector(N->getOperand(0), Lo, Hi);
686 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
687 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
689 if (IdxVal < LoElts) {
690 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
691 "Extracted subvector crosses vector split!");
692 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
694 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
695 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
699 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
700 SDValue Vec = N->getOperand(0);
701 SDValue Idx = N->getOperand(1);
702 MVT VecVT = Vec.getValueType();
704 if (isa<ConstantSDNode>(Idx)) {
705 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
706 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
709 GetSplitVector(Vec, Lo, Hi);
711 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
714 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
716 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
717 DAG.getConstant(IdxVal - LoElts,
718 Idx.getValueType()));
721 // Store the vector to the stack.
722 MVT EltVT = VecVT.getVectorElementType();
723 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
724 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
726 // Load back the required element.
727 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
728 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
731 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
732 assert(N->isUnindexed() && "Indexed store of vector?");
733 assert(OpNo == 1 && "Can only split the stored value");
735 bool isTruncating = N->isTruncatingStore();
736 SDValue Ch = N->getChain();
737 SDValue Ptr = N->getBasePtr();
738 int SVOffset = N->getSrcValueOffset();
739 MVT MemoryVT = N->getMemoryVT();
740 unsigned Alignment = N->getAlignment();
741 bool isVol = N->isVolatile();
743 GetSplitVector(N->getOperand(1), Lo, Hi);
745 MVT LoMemVT, HiMemVT;
746 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
748 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
751 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
752 LoMemVT, isVol, Alignment);
754 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
757 // Increment the pointer to the other half.
758 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
759 DAG.getIntPtrConstant(IncrementSize));
762 Hi = DAG.getTruncStore(Ch, Hi, Ptr,
763 N->getSrcValue(), SVOffset+IncrementSize,
765 isVol, MinAlign(Alignment, IncrementSize));
767 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
768 isVol, MinAlign(Alignment, IncrementSize));
770 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
773 SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
774 assert(OpNo == 2 && "Shuffle source type differs from result type?");
775 SDValue Mask = N->getOperand(2);
776 unsigned MaskLength = Mask.getValueType().getVectorNumElements();
777 unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
778 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
780 // Look for a legal vector type to place the mask values in.
781 // Note that there may not be *any* legal vector-of-integer
782 // type for which the element type is legal!
783 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
784 EltVT <= MVT::LAST_INTEGER_VALUETYPE;
785 // Integer values types are consecutively numbered. Exploit this.
786 EltVT = MVT::SimpleValueType(EltVT + 1)) {
788 // Is the element type big enough to hold the values?
789 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
793 // Is the vector type legal?
794 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
795 if (!isTypeLegal(VecVT))
799 // If the element type is not legal, find a larger legal type to use for
800 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
801 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
802 // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
803 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
804 // Integer values types are consecutively numbered. Exploit this.
805 OpVT = MVT::SimpleValueType(OpVT + 1)) {
806 if (!isTypeLegal(OpVT))
809 // Success! Rebuild the vector using the legal types.
810 SmallVector<SDValue, 16> Ops(MaskLength);
811 for (unsigned i = 0; i < MaskLength; ++i) {
812 SDValue Arg = Mask.getOperand(i);
813 if (Arg.getOpcode() == ISD::UNDEF) {
814 Ops[i] = DAG.getNode(ISD::UNDEF, OpVT);
816 uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
817 Ops[i] = DAG.getConstant(Idx, OpVT);
820 return DAG.UpdateNodeOperands(SDValue(N,0),
821 N->getOperand(0), N->getOperand(1),
822 DAG.getNode(ISD::BUILD_VECTOR,
823 VecVT, &Ops[0], Ops.size()));
826 // Continuing is pointless - failure is certain.
829 assert(false && "Failed to find an appropriate mask type!");
830 return SDValue(N, 0);