1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in multiple vectors of a smaller type. For example,
19 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetData.h"
28 //===----------------------------------------------------------------------===//
29 // Result Vector Scalarization: <1 x ty> -> ty.
30 //===----------------------------------------------------------------------===//
32 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
35 SDValue R = SDValue();
37 switch (N->getOpcode()) {
40 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
41 N->dump(&DAG); cerr << "\n";
43 assert(0 && "Do not know how to scalarize the result of this operator!");
46 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
47 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
48 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
49 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
50 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
51 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
52 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
53 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
54 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
55 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
56 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
57 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
58 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
77 case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break;
94 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
98 case ISD::SRL: R = ScalarizeVecRes_ShiftOp(N); break;
101 // If R is null, the sub-method took care of registering the result.
103 SetScalarizedVector(SDValue(N, ResNo), R);
106 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
107 SDValue LHS = GetScalarizedVector(N->getOperand(0));
108 SDValue RHS = GetScalarizedVector(N->getOperand(1));
109 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
110 LHS.getValueType(), LHS, RHS);
113 SDValue DAGTypeLegalizer::ScalarizeVecRes_ShiftOp(SDNode *N) {
114 SDValue LHS = GetScalarizedVector(N->getOperand(0));
115 SDValue ShiftAmt = GetScalarizedVector(N->getOperand(1));
116 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
117 LHS.getValueType(), LHS, ShiftAmt);
120 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
121 MVT NewVT = N->getValueType(0).getVectorElementType();
122 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
123 NewVT, N->getOperand(0));
126 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
127 MVT NewVT = N->getValueType(0).getVectorElementType();
128 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
129 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
130 Op0, DAG.getValueType(NewVT),
131 DAG.getValueType(Op0.getValueType()),
134 cast<CvtRndSatSDNode>(N)->getCvtCode());
137 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
138 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
139 N->getValueType(0).getVectorElementType(),
140 N->getOperand(0), N->getOperand(1));
143 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
144 SDValue Op = GetScalarizedVector(N->getOperand(0));
145 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
146 Op.getValueType(), Op, N->getOperand(1));
149 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
150 // The value to insert may have a wider type than the vector element type,
151 // so be sure to truncate it to the element type if necessary.
152 SDValue Op = N->getOperand(1);
153 MVT EltVT = N->getValueType(0).getVectorElementType();
154 if (Op.getValueType() != EltVT)
155 // FIXME: Can this happen for floating point types?
156 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
160 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
161 assert(N->isUnindexed() && "Indexed vector load?");
163 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getDebugLoc(),
164 N->getExtensionType(),
165 N->getValueType(0).getVectorElementType(),
166 N->getChain(), N->getBasePtr(),
167 DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
168 N->getBasePtr().getValueType()),
169 N->getSrcValue(), N->getSrcValueOffset(),
170 N->getMemoryVT().getVectorElementType(),
171 N->isVolatile(), N->getAlignment());
173 // Legalized the chain result - switch anything that used the old chain to
175 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
179 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
180 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
181 MVT DestVT = N->getValueType(0).getVectorElementType();
182 SDValue Op = GetScalarizedVector(N->getOperand(0));
183 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
186 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
187 return N->getOperand(0);
190 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
191 SDValue LHS = GetScalarizedVector(N->getOperand(1));
192 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
193 LHS.getValueType(), N->getOperand(0), LHS,
194 GetScalarizedVector(N->getOperand(2)));
197 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
198 SDValue LHS = GetScalarizedVector(N->getOperand(2));
199 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
200 N->getOperand(0), N->getOperand(1),
201 LHS, GetScalarizedVector(N->getOperand(3)),
205 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
206 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
207 N->getValueType(0).getVectorElementType());
210 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
211 // Figure out if the scalar is the LHS or RHS and return it.
212 SDValue Arg = N->getOperand(2).getOperand(0);
213 if (Arg.getOpcode() == ISD::UNDEF)
214 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
215 N->getValueType(0).getVectorElementType());
216 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
217 return GetScalarizedVector(N->getOperand(Op));
220 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
221 SDValue LHS = GetScalarizedVector(N->getOperand(0));
222 SDValue RHS = GetScalarizedVector(N->getOperand(1));
223 MVT NVT = N->getValueType(0).getVectorElementType();
224 MVT SVT = TLI.getSetCCResultType(LHS.getValueType());
225 DebugLoc dl = N->getDebugLoc();
227 // Turn it into a scalar SETCC.
228 SDValue Res = DAG.getNode(ISD::SETCC, dl, SVT, LHS, RHS, N->getOperand(2));
230 // VSETCC always returns a sign-extended value, while SETCC may not. The
231 // SETCC result type may not match the vector element type. Correct these.
232 if (NVT.bitsLE(SVT)) {
233 // The SETCC result type is bigger than the vector element type.
234 // Ensure the SETCC result is sign-extended.
235 if (TLI.getBooleanContents() !=
236 TargetLowering::ZeroOrNegativeOneBooleanContent)
237 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, SVT, Res,
238 DAG.getValueType(MVT::i1));
239 // Truncate to the final type.
240 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
242 // The SETCC result type is smaller than the vector element type.
243 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
244 if (TLI.getBooleanContents() !=
245 TargetLowering::ZeroOrNegativeOneBooleanContent)
246 Res = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Res);
247 // Sign extend to the final type.
248 return DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Res);
253 //===----------------------------------------------------------------------===//
254 // Operand Vector Scalarization <1 x ty> -> ty.
255 //===----------------------------------------------------------------------===//
257 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
258 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
260 SDValue Res = SDValue();
262 if (Res.getNode() == 0) {
263 switch (N->getOpcode()) {
266 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
267 N->dump(&DAG); cerr << "\n";
269 assert(0 && "Do not know how to scalarize this operator's operand!");
272 case ISD::BIT_CONVERT:
273 Res = ScalarizeVecOp_BIT_CONVERT(N); break;
275 case ISD::CONCAT_VECTORS:
276 Res = ScalarizeVecOp_CONCAT_VECTORS(N); break;
278 case ISD::EXTRACT_VECTOR_ELT:
279 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
282 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
286 // If the result is null, the sub-method took care of registering results etc.
287 if (!Res.getNode()) return false;
289 // If the result is N, the sub-method updated N in place. Tell the legalizer
291 if (Res.getNode() == N)
294 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
295 "Invalid operand expansion");
297 ReplaceValueWith(SDValue(N, 0), Res);
301 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
302 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
303 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
304 SDValue Elt = GetScalarizedVector(N->getOperand(0));
305 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
306 N->getValueType(0), Elt);
309 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
310 /// use a BUILD_VECTOR instead.
311 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
312 SmallVector<SDValue, 8> Ops(N->getNumOperands());
313 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
314 Ops[i] = GetScalarizedVector(N->getOperand(i));
315 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
316 &Ops[0], Ops.size());
319 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
320 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
322 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
323 return GetScalarizedVector(N->getOperand(0));
326 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
327 /// scalarized, it must be <1 x ty>. Just store the element.
328 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
329 assert(N->isUnindexed() && "Indexed store of one-element vector?");
330 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
331 DebugLoc dl = N->getDebugLoc();
333 if (N->isTruncatingStore())
334 return DAG.getTruncStore(N->getChain(), dl,
335 GetScalarizedVector(N->getOperand(1)),
337 N->getSrcValue(), N->getSrcValueOffset(),
338 N->getMemoryVT().getVectorElementType(),
339 N->isVolatile(), N->getAlignment());
341 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
342 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
343 N->isVolatile(), N->getAlignment());
347 //===----------------------------------------------------------------------===//
348 // Result Vector Splitting
349 //===----------------------------------------------------------------------===//
351 /// SplitVectorResult - This method is called when the specified result of the
352 /// specified node is found to need vector splitting. At this point, the node
353 /// may also have invalid operands or may have other results that need
354 /// legalization, we just know that (at least) one result needs vector
356 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
357 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
360 switch (N->getOpcode()) {
363 cerr << "SplitVectorResult #" << ResNo << ": ";
364 N->dump(&DAG); cerr << "\n";
366 assert(0 && "Do not know how to split the result of this operator!");
369 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
370 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
371 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
372 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
374 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
375 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
376 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
377 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
378 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
379 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
380 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
381 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
382 case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
383 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
384 case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
398 case ISD::FNEARBYINT:
399 case ISD::FP_TO_SINT:
400 case ISD::FP_TO_UINT:
401 case ISD::SINT_TO_FP:
403 case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break;
423 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
426 // If Lo/Hi is null, the sub-method took care of registering results etc.
428 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
431 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
433 SDValue LHSLo, LHSHi;
434 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
435 SDValue RHSLo, RHSHi;
436 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
437 DebugLoc dl = N->getDebugLoc();
439 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
440 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
443 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
445 // We know the result is a vector. The input may be either a vector or a
448 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
449 DebugLoc dl = N->getDebugLoc();
451 SDValue InOp = N->getOperand(0);
452 MVT InVT = InOp.getValueType();
454 // Handle some special cases efficiently.
455 switch (getTypeAction(InVT)) {
457 assert(false && "Unknown type action!");
461 case ScalarizeVector:
465 // A scalar to vector conversion, where the scalar needs expansion.
466 // If the vector is being split in two then we can just convert the
469 GetExpandedOp(InOp, Lo, Hi);
470 if (TLI.isBigEndian())
472 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
473 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
478 // If the input is a vector that needs to be split, convert each split
479 // piece of the input now.
480 GetSplitVector(InOp, Lo, Hi);
481 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
482 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
486 // In the general case, convert the input to an integer and split it by hand.
487 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
488 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
489 if (TLI.isBigEndian())
490 std::swap(LoIntVT, HiIntVT);
492 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
494 if (TLI.isBigEndian())
496 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
497 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
500 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
503 DebugLoc dl = N->getDebugLoc();
504 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
505 unsigned LoNumElts = LoVT.getVectorNumElements();
506 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
507 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
509 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
510 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
513 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
515 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
516 DebugLoc dl = N->getDebugLoc();
517 unsigned NumSubvectors = N->getNumOperands() / 2;
518 if (NumSubvectors == 1) {
519 Lo = N->getOperand(0);
520 Hi = N->getOperand(1);
525 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
527 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
528 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
530 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
531 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
534 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
537 DebugLoc dl = N->getDebugLoc();
538 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
540 GetSplitVector(N->getOperand(0), VLo, VHi);
541 SDValue DTyOpLo = DAG.getValueType(LoVT);
542 SDValue DTyOpHi = DAG.getValueType(HiVT);
543 SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
544 SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
546 SDValue RndOp = N->getOperand(3);
547 SDValue SatOp = N->getOperand(4);
548 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
550 Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
552 Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp,
556 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
558 SDValue Vec = N->getOperand(0);
559 SDValue Idx = N->getOperand(1);
560 MVT IdxVT = Idx.getValueType();
561 DebugLoc dl = N->getDebugLoc();
564 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
565 // The indices are not guaranteed to be a multiple of the new vector
566 // size unless the original vector type was split in two.
567 assert(LoVT == HiVT && "Non power-of-two vectors not supported!");
569 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
570 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
571 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
572 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, Idx);
575 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
577 DebugLoc dl = N->getDebugLoc();
578 GetSplitVector(N->getOperand(0), Lo, Hi);
579 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
580 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
583 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
585 SDValue Vec = N->getOperand(0);
586 SDValue Elt = N->getOperand(1);
587 SDValue Idx = N->getOperand(2);
588 DebugLoc dl = N->getDebugLoc();
589 GetSplitVector(Vec, Lo, Hi);
591 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
592 unsigned IdxVal = CIdx->getZExtValue();
593 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
594 if (IdxVal < LoNumElts)
595 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
596 Lo.getValueType(), Lo, Elt, Idx);
598 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
599 DAG.getIntPtrConstant(IdxVal - LoNumElts));
603 // Spill the vector to the stack.
604 MVT VecVT = Vec.getValueType();
605 MVT EltVT = VecVT.getVectorElementType();
606 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
607 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
609 // Store the new element. This may be larger than the vector element type,
610 // so use a truncating store.
611 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
613 TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT());
614 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT);
616 // Load the Lo part from the stack slot.
617 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, NULL, 0);
619 // Increment the pointer to the other part.
620 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
621 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
622 DAG.getIntPtrConstant(IncrementSize));
624 // Load the Hi part from the stack slot.
625 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, NULL, 0, false,
626 MinAlign(Alignment, IncrementSize));
629 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
632 DebugLoc dl = N->getDebugLoc();
633 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
634 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
635 Hi = DAG.getNode(ISD::UNDEF, dl, HiVT);
638 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
640 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
642 DebugLoc dl = LD->getDebugLoc();
643 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
645 ISD::LoadExtType ExtType = LD->getExtensionType();
646 SDValue Ch = LD->getChain();
647 SDValue Ptr = LD->getBasePtr();
648 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
649 const Value *SV = LD->getSrcValue();
650 int SVOffset = LD->getSrcValueOffset();
651 MVT MemoryVT = LD->getMemoryVT();
652 unsigned Alignment = LD->getAlignment();
653 bool isVolatile = LD->isVolatile();
655 MVT LoMemVT, HiMemVT;
656 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
658 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, LoVT, Ch, Ptr, Offset,
659 SV, SVOffset, LoMemVT, isVolatile, Alignment);
661 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
662 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
663 DAG.getIntPtrConstant(IncrementSize));
664 SVOffset += IncrementSize;
665 Alignment = MinAlign(Alignment, IncrementSize);
666 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, HiVT, Ch, Ptr, Offset,
667 SV, SVOffset, HiMemVT, isVolatile, Alignment);
669 // Build a factor node to remember that this load is independent of the
671 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
674 // Legalized the chain result - switch anything that used the old chain to
676 ReplaceValueWith(SDValue(LD, 1), Ch);
679 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
681 // Get the dest types - they may not match the input types, e.g. int_to_fp.
683 DebugLoc dl = N->getDebugLoc();
684 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
687 MVT InVT = N->getOperand(0).getValueType();
688 switch (getTypeAction(InVT)) {
689 default: assert(0 && "Unexpected type action!");
691 assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
692 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
693 LoVT.getVectorNumElements());
694 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
695 DAG.getIntPtrConstant(0));
696 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
697 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
701 GetSplitVector(N->getOperand(0), Lo, Hi);
705 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
706 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
709 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
711 // The low and high parts of the original input give four input vectors.
713 DebugLoc dl = N->getDebugLoc();
714 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
715 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
716 MVT NewVT = Inputs[0].getValueType();
717 unsigned NewElts = NewVT.getVectorNumElements();
718 assert(NewVT == Inputs[1].getValueType() &&
719 "Non power-of-two vectors not supported!");
721 // If Lo or Hi uses elements from at most two of the four input vectors, then
722 // express it as a vector shuffle of those two inputs. Otherwise extract the
723 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
724 SDValue Mask = N->getOperand(2);
725 MVT IdxVT = Mask.getValueType().getVectorElementType();
726 SmallVector<SDValue, 16> Ops;
727 Ops.reserve(NewElts);
728 for (unsigned High = 0; High < 2; ++High) {
729 SDValue &Output = High ? Hi : Lo;
731 // Build a shuffle mask for the output, discovering on the fly which
732 // input vectors to use as shuffle operands (recorded in InputUsed).
733 // If building a suitable shuffle vector proves too hard, then bail
734 // out with useBuildVector set.
735 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
736 unsigned FirstMaskIdx = High * NewElts;
737 bool useBuildVector = false;
738 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
739 SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
741 // The mask element. This indexes into the input.
742 unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
743 -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
745 // The input vector this mask element indexes into.
746 unsigned Input = Idx / NewElts;
748 if (Input >= array_lengthof(Inputs)) {
749 // The mask element does not index into any input vector.
750 Ops.push_back(DAG.getNode(ISD::UNDEF, dl, IdxVT));
754 // Turn the index into an offset from the start of the input vector.
755 Idx -= Input * NewElts;
757 // Find or create a shuffle vector operand to hold this input.
759 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
760 if (InputUsed[OpNo] == Input) {
761 // This input vector is already an operand.
763 } else if (InputUsed[OpNo] == -1U) {
764 // Create a new operand for this input vector.
765 InputUsed[OpNo] = Input;
770 if (OpNo >= array_lengthof(InputUsed)) {
771 // More than two input vectors used! Give up on trying to create a
772 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
773 useBuildVector = true;
777 // Add the mask index for the new shuffle vector.
778 Ops.push_back(DAG.getConstant(Idx + OpNo * NewElts, IdxVT));
781 if (useBuildVector) {
782 MVT EltVT = NewVT.getVectorElementType();
785 // Extract the input elements by hand.
786 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
787 SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
789 // The mask element. This indexes into the input.
790 unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
791 -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
793 // The input vector this mask element indexes into.
794 unsigned Input = Idx / NewElts;
796 if (Input >= array_lengthof(Inputs)) {
797 // The mask element is "undef" or indexes off the end of the input.
798 Ops.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
802 // Turn the index into an offset from the start of the input vector.
803 Idx -= Input * NewElts;
805 // Extract the vector element by hand.
806 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
807 Inputs[Input], DAG.getIntPtrConstant(Idx)));
810 // Construct the Lo/Hi output using a BUILD_VECTOR.
811 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, &Ops[0], Ops.size());
812 } else if (InputUsed[0] == -1U) {
813 // No input vectors were used! The result is undefined.
814 Output = DAG.getNode(ISD::UNDEF, dl, NewVT);
816 // At least one input vector was used. Create a new shuffle vector.
817 SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl,
818 MVT::getVectorVT(IdxVT, Ops.size()),
819 &Ops[0], Ops.size());
820 SDValue Op0 = Inputs[InputUsed[0]];
821 // If only one input was used, use an undefined vector for the other.
822 SDValue Op1 = InputUsed[1] == -1U ?
823 DAG.getNode(ISD::UNDEF, dl, NewVT) : Inputs[InputUsed[1]];
824 Output = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, Op0, Op1, NewMask);
831 void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
834 DebugLoc dl = N->getDebugLoc();
835 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
837 SDValue LL, LH, RL, RH;
838 GetSplitVector(N->getOperand(0), LL, LH);
839 GetSplitVector(N->getOperand(1), RL, RH);
841 Lo = DAG.getNode(ISD::VSETCC, dl, LoVT, LL, RL, N->getOperand(2));
842 Hi = DAG.getNode(ISD::VSETCC, dl, HiVT, LH, RH, N->getOperand(2));
846 //===----------------------------------------------------------------------===//
847 // Operand Vector Splitting
848 //===----------------------------------------------------------------------===//
850 /// SplitVectorOperand - This method is called when the specified operand of the
851 /// specified node is found to need vector splitting. At this point, all of the
852 /// result types of the node are known to be legal, but other operands of the
853 /// node may need legalization as well as the specified one.
854 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
855 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
856 SDValue Res = SDValue();
858 if (Res.getNode() == 0) {
859 switch (N->getOpcode()) {
862 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
863 N->dump(&DAG); cerr << "\n";
865 assert(0 && "Do not know how to split this operator's operand!");
868 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
869 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
870 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
871 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N),
873 case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break;
878 case ISD::FP_TO_SINT:
879 case ISD::FP_TO_UINT:
880 case ISD::SINT_TO_FP:
882 case ISD::UINT_TO_FP: Res = SplitVecOp_UnaryOp(N); break;
886 // If the result is null, the sub-method took care of registering results etc.
887 if (!Res.getNode()) return false;
889 // If the result is N, the sub-method updated N in place. Tell the legalizer
891 if (Res.getNode() == N)
894 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
895 "Invalid operand expansion");
897 ReplaceValueWith(SDValue(N, 0), Res);
901 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
902 // The result has a legal vector type, but the input needs splitting.
903 MVT ResVT = N->getValueType(0);
905 DebugLoc dl = N->getDebugLoc();
906 GetSplitVector(N->getOperand(0), Lo, Hi);
907 assert(Lo.getValueType() == Hi.getValueType() &&
908 "Returns legal non-power-of-two vector type?");
909 MVT InVT = Lo.getValueType();
911 MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
912 InVT.getVectorNumElements());
914 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
915 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
917 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
920 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
921 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
922 // end up being split all the way down to individual components. Convert the
923 // split pieces into integers and reassemble.
925 GetSplitVector(N->getOperand(0), Lo, Hi);
926 Lo = BitConvertToInteger(Lo);
927 Hi = BitConvertToInteger(Hi);
929 if (TLI.isBigEndian())
932 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), N->getValueType(0),
933 JoinIntegers(Lo, Hi));
936 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
937 // We know that the extracted result type is legal. For now, assume the index
939 MVT SubVT = N->getValueType(0);
940 SDValue Idx = N->getOperand(1);
941 DebugLoc dl = N->getDebugLoc();
943 GetSplitVector(N->getOperand(0), Lo, Hi);
945 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
946 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
948 if (IdxVal < LoElts) {
949 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
950 "Extracted subvector crosses vector split!");
951 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
953 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
954 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
958 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
959 SDValue Vec = N->getOperand(0);
960 SDValue Idx = N->getOperand(1);
961 MVT VecVT = Vec.getValueType();
963 if (isa<ConstantSDNode>(Idx)) {
964 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
965 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
968 GetSplitVector(Vec, Lo, Hi);
970 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
973 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
975 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
976 DAG.getConstant(IdxVal - LoElts,
977 Idx.getValueType()));
980 // Store the vector to the stack.
981 MVT EltVT = VecVT.getVectorElementType();
982 DebugLoc dl = N->getDebugLoc();
983 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
984 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
985 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
986 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, SV, 0);
988 // Load back the required element.
989 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
990 return DAG.getLoad(EltVT, dl, Store, StackPtr, SV, 0);
993 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
994 assert(N->isUnindexed() && "Indexed store of vector?");
995 assert(OpNo == 1 && "Can only split the stored value");
996 DebugLoc dl = N->getDebugLoc();
998 bool isTruncating = N->isTruncatingStore();
999 SDValue Ch = N->getChain();
1000 SDValue Ptr = N->getBasePtr();
1001 int SVOffset = N->getSrcValueOffset();
1002 MVT MemoryVT = N->getMemoryVT();
1003 unsigned Alignment = N->getAlignment();
1004 bool isVol = N->isVolatile();
1006 GetSplitVector(N->getOperand(1), Lo, Hi);
1008 MVT LoMemVT, HiMemVT;
1009 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1011 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1014 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
1015 LoMemVT, isVol, Alignment);
1017 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
1020 // Increment the pointer to the other half.
1021 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1022 DAG.getIntPtrConstant(IncrementSize));
1025 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
1026 N->getSrcValue(), SVOffset+IncrementSize,
1028 isVol, MinAlign(Alignment, IncrementSize));
1030 Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
1031 isVol, MinAlign(Alignment, IncrementSize));
1033 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1036 SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
1037 assert(OpNo == 2 && "Shuffle source type differs from result type?");
1038 SDValue Mask = N->getOperand(2);
1039 DebugLoc dl = N->getDebugLoc();
1040 unsigned MaskLength = Mask.getValueType().getVectorNumElements();
1041 unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
1042 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
1044 // Look for a legal vector type to place the mask values in.
1045 // Note that there may not be *any* legal vector-of-integer
1046 // type for which the element type is legal!
1047 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
1048 EltVT <= MVT::LAST_INTEGER_VALUETYPE;
1049 // Integer values types are consecutively numbered. Exploit this.
1050 EltVT = MVT::SimpleValueType(EltVT + 1)) {
1052 // Is the element type big enough to hold the values?
1053 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
1057 // Is the vector type legal?
1058 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
1059 if (!isTypeLegal(VecVT))
1063 // If the element type is not legal, find a larger legal type to use for
1064 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
1065 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
1066 // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
1067 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
1068 // Integer values types are consecutively numbered. Exploit this.
1069 OpVT = MVT::SimpleValueType(OpVT + 1)) {
1070 if (!isTypeLegal(OpVT))
1073 // Success! Rebuild the vector using the legal types.
1074 SmallVector<SDValue, 16> Ops(MaskLength);
1075 for (unsigned i = 0; i < MaskLength; ++i) {
1076 SDValue Arg = Mask.getOperand(i);
1077 if (Arg.getOpcode() == ISD::UNDEF) {
1078 Ops[i] = DAG.getNode(ISD::UNDEF, dl, OpVT);
1080 uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1081 Ops[i] = DAG.getConstant(Idx, OpVT);
1084 return DAG.UpdateNodeOperands(SDValue(N,0),
1085 N->getOperand(0), N->getOperand(1),
1086 DAG.getNode(ISD::BUILD_VECTOR, dl,
1087 VecVT, &Ops[0], Ops.size()));
1090 // Continuing is pointless - failure is certain.
1093 assert(false && "Failed to find an appropriate mask type!");
1094 return SDValue(N, 0);
1098 //===----------------------------------------------------------------------===//
1099 // Result Vector Widening
1100 //===----------------------------------------------------------------------===//
1102 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1103 DEBUG(cerr << "Widen node result " << ResNo << ": "; N->dump(&DAG);
1105 SDValue Res = SDValue();
1107 switch (N->getOpcode()) {
1110 cerr << "WidenVectorResult #" << ResNo << ": ";
1111 N->dump(&DAG); cerr << "\n";
1113 assert(0 && "Do not know how to widen the result of this operator!");
1116 case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break;
1117 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1118 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1119 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1120 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1121 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1122 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1123 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1124 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1125 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1126 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1127 case ISD::VECTOR_SHUFFLE: Res = WidenVecRes_VECTOR_SHUFFLE(N); break;
1128 case ISD::VSETCC: Res = WidenVecRes_VSETCC(N); break;
1134 case ISD::FCOPYSIGN:
1150 case ISD::XOR: Res = WidenVecRes_Binary(N); break;
1154 case ISD::SRL: Res = WidenVecRes_Shift(N); break;
1156 case ISD::ANY_EXTEND:
1158 case ISD::FP_TO_SINT:
1159 case ISD::FP_TO_UINT:
1160 case ISD::SIGN_EXTEND:
1161 case ISD::SINT_TO_FP:
1163 case ISD::ZERO_EXTEND:
1164 case ISD::UINT_TO_FP: Res = WidenVecRes_Convert(N); break;
1173 case ISD::FSQRT: Res = WidenVecRes_Unary(N); break;
1176 // If Res is null, the sub-method took care of registering the result.
1178 SetWidenedVector(SDValue(N, ResNo), Res);
1181 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1182 // Binary op widening.
1183 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1184 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1185 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1186 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp1, InOp2);
1189 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1190 SDValue InOp = N->getOperand(0);
1191 DebugLoc dl = N->getDebugLoc();
1193 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1194 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1196 MVT InVT = InOp.getValueType();
1197 MVT InEltVT = InVT.getVectorElementType();
1198 MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
1200 unsigned Opcode = N->getOpcode();
1201 unsigned InVTNumElts = InVT.getVectorNumElements();
1203 if (getTypeAction(InVT) == WidenVector) {
1204 InOp = GetWidenedVector(N->getOperand(0));
1205 InVT = InOp.getValueType();
1206 InVTNumElts = InVT.getVectorNumElements();
1207 if (InVTNumElts == WidenNumElts)
1208 return DAG.getNode(Opcode, dl, WidenVT, InOp);
1211 if (TLI.isTypeLegal(InWidenVT)) {
1212 // Because the result and the input are different vector types, widening
1213 // the result could create a legal type but widening the input might make
1214 // it an illegal type that might lead to repeatedly splitting the input
1215 // and then widening it. To avoid this, we widen the input only if
1216 // it results in a legal type.
1217 if (WidenNumElts % InVTNumElts == 0) {
1218 // Widen the input and call convert on the widened input vector.
1219 unsigned NumConcat = WidenNumElts/InVTNumElts;
1220 SmallVector<SDValue, 16> Ops(NumConcat);
1222 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
1223 for (unsigned i = 1; i != NumConcat; ++i)
1225 return DAG.getNode(Opcode, dl, WidenVT,
1226 DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT,
1227 &Ops[0], NumConcat));
1230 if (InVTNumElts % WidenNumElts == 0) {
1231 // Extract the input and convert the shorten input vector.
1232 return DAG.getNode(Opcode, dl, WidenVT,
1233 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT,
1234 InOp, DAG.getIntPtrConstant(0)));
1238 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1239 SmallVector<SDValue, 16> Ops(WidenNumElts);
1240 MVT EltVT = WidenVT.getVectorElementType();
1241 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1243 for (i=0; i < MinElts; ++i)
1244 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
1245 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1246 DAG.getIntPtrConstant(i)));
1248 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
1249 for (; i < WidenNumElts; ++i)
1252 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1255 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1256 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1257 SDValue InOp = GetWidenedVector(N->getOperand(0));
1258 SDValue ShOp = N->getOperand(1);
1260 MVT ShVT = ShOp.getValueType();
1261 if (getTypeAction(ShVT) == WidenVector) {
1262 ShOp = GetWidenedVector(ShOp);
1263 ShVT = ShOp.getValueType();
1265 MVT ShWidenVT = MVT::getVectorVT(ShVT.getVectorElementType(),
1266 WidenVT.getVectorNumElements());
1267 if (ShVT != ShWidenVT)
1268 ShOp = ModifyToType(ShOp, ShWidenVT);
1270 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1273 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1274 // Unary op widening.
1275 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1276 SDValue InOp = GetWidenedVector(N->getOperand(0));
1277 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1280 SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
1281 SDValue InOp = N->getOperand(0);
1282 MVT InVT = InOp.getValueType();
1283 MVT VT = N->getValueType(0);
1284 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1285 DebugLoc dl = N->getDebugLoc();
1287 switch (getTypeAction(InVT)) {
1289 assert(false && "Unknown type action!");
1293 case PromoteInteger:
1294 // If the InOp is promoted to the same size, convert it. Otherwise,
1295 // fall out of the switch and widen the promoted input.
1296 InOp = GetPromotedInteger(InOp);
1297 InVT = InOp.getValueType();
1298 if (WidenVT.bitsEq(InVT))
1299 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1304 case ScalarizeVector:
1308 // If the InOp is widened to the same size, convert it. Otherwise, fall
1309 // out of the switch and widen the widened input.
1310 InOp = GetWidenedVector(InOp);
1311 InVT = InOp.getValueType();
1312 if (WidenVT.bitsEq(InVT))
1313 // The input widens to the same size. Convert to the widen value.
1314 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1318 unsigned WidenSize = WidenVT.getSizeInBits();
1319 unsigned InSize = InVT.getSizeInBits();
1320 if (WidenSize % InSize == 0) {
1321 // Determine new input vector type. The new input vector type will use
1322 // the same element type (if its a vector) or use the input type as a
1323 // vector. It is the same size as the type to widen to.
1325 unsigned NewNumElts = WidenSize / InSize;
1326 if (InVT.isVector()) {
1327 MVT InEltVT = InVT.getVectorElementType();
1328 NewInVT= MVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits());
1330 NewInVT = MVT::getVectorVT(InVT, NewNumElts);
1333 if (TLI.isTypeLegal(NewInVT)) {
1334 // Because the result and the input are different vector types, widening
1335 // the result could create a legal type but widening the input might make
1336 // it an illegal type that might lead to repeatedly splitting the input
1337 // and then widening it. To avoid this, we widen the input only if
1338 // it results in a legal type.
1339 SmallVector<SDValue, 16> Ops(NewNumElts);
1340 SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
1342 for (unsigned i = 1; i < NewNumElts; ++i)
1346 if (InVT.isVector())
1347 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1348 NewInVT, &Ops[0], NewNumElts);
1350 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1351 NewInVT, &Ops[0], NewNumElts);
1352 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, NewVec);
1356 // This should occur rarely. Lower the bit-convert to a store/load
1357 // from the stack. Create the stack frame object. Make sure it is aligned
1358 // for both the source and destination types.
1359 SDValue FIPtr = DAG.CreateStackTemporary(InVT, WidenVT);
1360 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1361 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1363 // Emit a store to the stack slot.
1364 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0);
1366 // Result is a load from the stack slot.
1367 return DAG.getLoad(WidenVT, dl, Store, FIPtr, SV, 0);
1370 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1371 DebugLoc dl = N->getDebugLoc();
1372 // Build a vector with undefined for the new nodes.
1373 MVT VT = N->getValueType(0);
1374 MVT EltVT = VT.getVectorElementType();
1375 unsigned NumElts = VT.getVectorNumElements();
1377 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1378 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1380 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1381 NewOps.reserve(WidenNumElts);
1382 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1383 NewOps.push_back(DAG.getNode(ISD::UNDEF, dl, EltVT));
1385 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1388 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1389 MVT InVT = N->getOperand(0).getValueType();
1390 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1391 DebugLoc dl = N->getDebugLoc();
1392 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1393 unsigned NumOperands = N->getNumOperands();
1395 bool InputWidened = false; // Indicates we need to widen the input.
1396 if (getTypeAction(InVT) != WidenVector) {
1397 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1398 // Add undef vectors to widen to correct length.
1399 unsigned NumConcat = WidenVT.getVectorNumElements() /
1400 InVT.getVectorNumElements();
1401 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
1402 SmallVector<SDValue, 16> Ops(NumConcat);
1403 for (unsigned i=0; i < NumOperands; ++i)
1404 Ops[i] = N->getOperand(i);
1405 for (unsigned i = NumOperands; i != NumConcat; ++i)
1407 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1410 InputWidened = true;
1411 if (WidenVT == TLI.getTypeToTransformTo(InVT)) {
1412 // The inputs and the result are widen to the same value.
1414 for (i=1; i < NumOperands; ++i)
1415 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1418 if (i > NumOperands)
1419 // Everything but the first operand is an UNDEF so just return the
1420 // widened first operand.
1421 return GetWidenedVector(N->getOperand(0));
1423 if (NumOperands == 2) {
1424 // Replace concat of two operands with a shuffle.
1425 MVT PtrVT = TLI.getPointerTy();
1426 SmallVector<SDValue, 16> MaskOps(WidenNumElts);
1427 for (unsigned i=0; i < WidenNumElts/2; ++i) {
1428 MaskOps[i] = DAG.getConstant(i, PtrVT);
1429 MaskOps[i+WidenNumElts/2] = DAG.getConstant(i+WidenNumElts, PtrVT);
1431 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl,
1432 MVT::getVectorVT(PtrVT, WidenNumElts),
1433 &MaskOps[0], WidenNumElts);
1434 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT,
1435 GetWidenedVector(N->getOperand(0)),
1436 GetWidenedVector(N->getOperand(1)), Mask);
1441 // Fall back to use extracts and build vector.
1442 MVT EltVT = WidenVT.getVectorElementType();
1443 unsigned NumInElts = InVT.getVectorNumElements();
1444 SmallVector<SDValue, 16> Ops(WidenNumElts);
1446 for (unsigned i=0; i < NumOperands; ++i) {
1447 SDValue InOp = N->getOperand(i);
1449 InOp = GetWidenedVector(InOp);
1450 for (unsigned j=0; j < NumInElts; ++j)
1451 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1452 DAG.getIntPtrConstant(j));
1454 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
1455 for (; Idx < WidenNumElts; ++Idx)
1456 Ops[Idx] = UndefVal;
1457 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1460 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1461 DebugLoc dl = N->getDebugLoc();
1462 SDValue InOp = N->getOperand(0);
1463 SDValue RndOp = N->getOperand(3);
1464 SDValue SatOp = N->getOperand(4);
1466 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1467 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1469 MVT InVT = InOp.getValueType();
1470 MVT InEltVT = InVT.getVectorElementType();
1471 MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
1473 SDValue DTyOp = DAG.getValueType(WidenVT);
1474 SDValue STyOp = DAG.getValueType(InWidenVT);
1475 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1477 unsigned InVTNumElts = InVT.getVectorNumElements();
1478 if (getTypeAction(InVT) == WidenVector) {
1479 InOp = GetWidenedVector(InOp);
1480 InVT = InOp.getValueType();
1481 InVTNumElts = InVT.getVectorNumElements();
1482 if (InVTNumElts == WidenNumElts)
1483 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1487 if (TLI.isTypeLegal(InWidenVT)) {
1488 // Because the result and the input are different vector types, widening
1489 // the result could create a legal type but widening the input might make
1490 // it an illegal type that might lead to repeatedly splitting the input
1491 // and then widening it. To avoid this, we widen the input only if
1492 // it results in a legal type.
1493 if (WidenNumElts % InVTNumElts == 0) {
1494 // Widen the input and call convert on the widened input vector.
1495 unsigned NumConcat = WidenNumElts/InVTNumElts;
1496 SmallVector<SDValue, 16> Ops(NumConcat);
1498 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
1499 for (unsigned i = 1; i != NumConcat; ++i) {
1502 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1503 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1507 if (InVTNumElts % WidenNumElts == 0) {
1508 // Extract the input and convert the shorten input vector.
1509 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1510 DAG.getIntPtrConstant(0));
1511 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1516 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1517 SmallVector<SDValue, 16> Ops(WidenNumElts);
1518 MVT EltVT = WidenVT.getVectorElementType();
1519 DTyOp = DAG.getValueType(EltVT);
1520 STyOp = DAG.getValueType(InEltVT);
1522 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1524 for (i=0; i < MinElts; ++i) {
1525 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1526 DAG.getIntPtrConstant(i));
1527 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1531 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
1532 for (; i < WidenNumElts; ++i)
1535 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1538 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1539 MVT VT = N->getValueType(0);
1540 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1541 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1542 SDValue InOp = N->getOperand(0);
1543 SDValue Idx = N->getOperand(1);
1544 DebugLoc dl = N->getDebugLoc();
1546 if (getTypeAction(InOp.getValueType()) == WidenVector)
1547 InOp = GetWidenedVector(InOp);
1549 MVT InVT = InOp.getValueType();
1551 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
1553 unsigned IdxVal = CIdx->getZExtValue();
1554 // Check if we can just return the input vector after widening.
1555 if (IdxVal == 0 && InVT == WidenVT)
1558 // Check if we can extract from the vector.
1559 unsigned InNumElts = InVT.getVectorNumElements();
1560 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1561 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1564 // We could try widening the input to the right length but for now, extract
1565 // the original elements, fill the rest with undefs and build a vector.
1566 SmallVector<SDValue, 16> Ops(WidenNumElts);
1567 MVT EltVT = VT.getVectorElementType();
1568 MVT IdxVT = Idx.getValueType();
1569 unsigned NumElts = VT.getVectorNumElements();
1572 unsigned IdxVal = CIdx->getZExtValue();
1573 for (i=0; i < NumElts; ++i)
1574 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1575 DAG.getConstant(IdxVal+i, IdxVT));
1577 Ops[0] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, Idx);
1578 for (i=1; i < NumElts; ++i) {
1579 SDValue NewIdx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1580 DAG.getConstant(i, IdxVT));
1581 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, NewIdx);
1585 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
1586 for (; i < WidenNumElts; ++i)
1588 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1591 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1592 SDValue InOp = GetWidenedVector(N->getOperand(0));
1593 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1594 InOp.getValueType(), InOp,
1595 N->getOperand(1), N->getOperand(2));
1598 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1599 LoadSDNode *LD = cast<LoadSDNode>(N);
1600 MVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0));
1601 MVT LdVT = LD->getMemoryVT();
1602 DebugLoc dl = N->getDebugLoc();
1603 assert(LdVT.isVector() && WidenVT.isVector());
1606 SDValue Chain = LD->getChain();
1607 SDValue BasePtr = LD->getBasePtr();
1608 int SVOffset = LD->getSrcValueOffset();
1609 unsigned Align = LD->getAlignment();
1610 bool isVolatile = LD->isVolatile();
1611 const Value *SV = LD->getSrcValue();
1612 ISD::LoadExtType ExtType = LD->getExtensionType();
1615 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1616 if (ExtType != ISD::NON_EXTLOAD) {
1617 // For extension loads, we can not play the tricks of chopping legal
1618 // vector types and bit cast it to the right type. Instead, we unroll
1619 // the load and build a vector.
1620 MVT EltVT = WidenVT.getVectorElementType();
1621 MVT LdEltVT = LdVT.getVectorElementType();
1622 unsigned NumElts = LdVT.getVectorNumElements();
1624 // Load each element and widen
1625 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1626 SmallVector<SDValue, 16> Ops(WidenNumElts);
1627 unsigned Increment = LdEltVT.getSizeInBits() / 8;
1628 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, SV, SVOffset,
1629 LdEltVT, isVolatile, Align);
1630 LdChain.push_back(Ops[0].getValue(1));
1631 unsigned i = 0, Offset = Increment;
1632 for (i=1; i < NumElts; ++i, Offset += Increment) {
1633 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
1634 BasePtr, DAG.getIntPtrConstant(Offset));
1635 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, SV,
1636 SVOffset + Offset, LdEltVT, isVolatile, Align);
1637 LdChain.push_back(Ops[i].getValue(1));
1640 // Fill the rest with undefs
1641 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
1642 for (; i != WidenNumElts; ++i)
1645 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
1647 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
1648 unsigned int LdWidth = LdVT.getSizeInBits();
1649 Result = GenWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
1650 Align, isVolatile, LdWidth, WidenVT, dl);
1653 // If we generate a single load, we can use that for the chain. Otherwise,
1654 // build a factor node to remember the multiple loads are independent and
1657 if (LdChain.size() == 1)
1658 NewChain = LdChain[0];
1660 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LdChain[0],
1663 // Modified the chain - switch anything that used the old chain to use
1665 ReplaceValueWith(SDValue(N, 1), Chain);
1670 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1671 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1672 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1673 WidenVT, N->getOperand(0));
1676 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1677 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1678 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1680 SDValue Cond1 = N->getOperand(0);
1681 MVT CondVT = Cond1.getValueType();
1682 if (CondVT.isVector()) {
1683 MVT CondEltVT = CondVT.getVectorElementType();
1684 MVT CondWidenVT = MVT::getVectorVT(CondEltVT, WidenNumElts);
1685 if (getTypeAction(CondVT) == WidenVector)
1686 Cond1 = GetWidenedVector(Cond1);
1688 if (Cond1.getValueType() != CondWidenVT)
1689 Cond1 = ModifyToType(Cond1, CondWidenVT);
1692 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1693 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1694 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1695 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
1696 WidenVT, Cond1, InOp1, InOp2);
1699 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1700 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1701 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1702 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1703 InOp1.getValueType(), N->getOperand(0),
1704 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1707 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1708 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1709 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), WidenVT);
1712 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(SDNode *N) {
1713 MVT VT = N->getValueType(0);
1714 unsigned NumElts = VT.getVectorNumElements();
1715 DebugLoc dl = N->getDebugLoc();
1717 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1718 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1720 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1721 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1723 // Adjust mask based on new input vector length.
1724 SDValue Mask = N->getOperand(2);
1725 SmallVector<SDValue, 16> MaskOps(WidenNumElts);
1726 MVT IdxVT = Mask.getValueType().getVectorElementType();
1727 for (unsigned i = 0; i < NumElts; ++i) {
1728 SDValue Arg = Mask.getOperand(i);
1729 if (Arg.getOpcode() == ISD::UNDEF)
1732 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1736 MaskOps[i] = DAG.getConstant(Idx - NumElts + WidenNumElts, IdxVT);
1739 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1740 MaskOps[i] = DAG.getNode(ISD::UNDEF, dl, IdxVT);
1741 SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl,
1742 MVT::getVectorVT(IdxVT, WidenNumElts),
1743 &MaskOps[0], WidenNumElts);
1745 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, InOp1, InOp2, NewMask);
1748 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1749 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1750 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1752 SDValue InOp1 = N->getOperand(0);
1753 MVT InVT = InOp1.getValueType();
1754 assert(InVT.isVector() && "can not widen non vector type");
1755 MVT WidenInVT = MVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts);
1756 InOp1 = GetWidenedVector(InOp1);
1757 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1759 // Assume that the input and output will be widen appropriately. If not,
1760 // we will have to unroll it at some point.
1761 assert(InOp1.getValueType() == WidenInVT &&
1762 InOp2.getValueType() == WidenInVT &&
1763 "Input not widened to expected type!");
1764 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(),
1765 WidenVT, InOp1, InOp2, N->getOperand(2));
1769 //===----------------------------------------------------------------------===//
1770 // Widen Vector Operand
1771 //===----------------------------------------------------------------------===//
1772 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
1773 DEBUG(cerr << "Widen node operand " << ResNo << ": "; N->dump(&DAG);
1775 SDValue Res = SDValue();
1777 switch (N->getOpcode()) {
1780 cerr << "WidenVectorOperand op #" << ResNo << ": ";
1781 N->dump(&DAG); cerr << "\n";
1783 assert(0 && "Do not know how to widen this operator's operand!");
1786 case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break;
1787 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
1788 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
1789 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
1792 case ISD::FP_TO_SINT:
1793 case ISD::FP_TO_UINT:
1794 case ISD::SINT_TO_FP:
1796 case ISD::UINT_TO_FP: Res = WidenVecOp_Convert(N); break;
1799 // If Res is null, the sub-method took care of registering the result.
1800 if (!Res.getNode()) return false;
1802 // If the result is N, the sub-method updated N in place. Tell the legalizer
1804 if (Res.getNode() == N)
1808 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1809 "Invalid operand expansion");
1811 ReplaceValueWith(SDValue(N, 0), Res);
1815 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
1816 // Since the result is legal and the input is illegal, it is unlikely
1817 // that we can fix the input to a legal type so unroll the convert
1818 // into some scalar code and create a nasty build vector.
1819 MVT VT = N->getValueType(0);
1820 MVT EltVT = VT.getVectorElementType();
1821 DebugLoc dl = N->getDebugLoc();
1822 unsigned NumElts = VT.getVectorNumElements();
1823 SDValue InOp = N->getOperand(0);
1824 if (getTypeAction(InOp.getValueType()) == WidenVector)
1825 InOp = GetWidenedVector(InOp);
1826 MVT InVT = InOp.getValueType();
1827 MVT InEltVT = InVT.getVectorElementType();
1829 unsigned Opcode = N->getOpcode();
1830 SmallVector<SDValue, 16> Ops(NumElts);
1831 for (unsigned i=0; i < NumElts; ++i)
1832 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
1833 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1834 DAG.getIntPtrConstant(i)));
1836 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
1839 SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) {
1840 MVT VT = N->getValueType(0);
1841 SDValue InOp = GetWidenedVector(N->getOperand(0));
1842 MVT InWidenVT = InOp.getValueType();
1843 DebugLoc dl = N->getDebugLoc();
1845 // Check if we can convert between two legal vector types and extract.
1846 unsigned InWidenSize = InWidenVT.getSizeInBits();
1847 unsigned Size = VT.getSizeInBits();
1848 if (InWidenSize % Size == 0 && !VT.isVector()) {
1849 unsigned NewNumElts = InWidenSize / Size;
1850 MVT NewVT = MVT::getVectorVT(VT, NewNumElts);
1851 if (TLI.isTypeLegal(NewVT)) {
1852 SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp);
1853 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
1854 DAG.getIntPtrConstant(0));
1858 // Lower the bit-convert to a store/load from the stack. Create the stack
1859 // frame object. Make sure it is aligned for both the source and destination
1861 SDValue FIPtr = DAG.CreateStackTemporary(InWidenVT, VT);
1862 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1863 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1865 // Emit a store to the stack slot.
1866 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0);
1868 // Result is a load from the stack slot.
1869 return DAG.getLoad(VT, dl, Store, FIPtr, SV, 0);
1872 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
1873 // If the input vector is not legal, it is likely that we will not find a
1874 // legal vector of the same size. Replace the concatenate vector with a
1875 // nasty build vector.
1876 MVT VT = N->getValueType(0);
1877 MVT EltVT = VT.getVectorElementType();
1878 DebugLoc dl = N->getDebugLoc();
1879 unsigned NumElts = VT.getVectorNumElements();
1880 SmallVector<SDValue, 16> Ops(NumElts);
1882 MVT InVT = N->getOperand(0).getValueType();
1883 unsigned NumInElts = InVT.getVectorNumElements();
1886 unsigned NumOperands = N->getNumOperands();
1887 for (unsigned i=0; i < NumOperands; ++i) {
1888 SDValue InOp = N->getOperand(i);
1889 if (getTypeAction(InOp.getValueType()) == WidenVector)
1890 InOp = GetWidenedVector(InOp);
1891 for (unsigned j=0; j < NumInElts; ++j)
1892 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1893 DAG.getIntPtrConstant(j));
1895 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
1898 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1899 SDValue InOp = GetWidenedVector(N->getOperand(0));
1900 MVT EltVT = InOp.getValueType().getVectorElementType();
1901 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
1902 EltVT, InOp, N->getOperand(1));
1905 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
1906 // We have to widen the value but we want only to store the original
1908 StoreSDNode *ST = cast<StoreSDNode>(N);
1909 SDValue Chain = ST->getChain();
1910 SDValue BasePtr = ST->getBasePtr();
1911 const Value *SV = ST->getSrcValue();
1912 int SVOffset = ST->getSrcValueOffset();
1913 unsigned Align = ST->getAlignment();
1914 bool isVolatile = ST->isVolatile();
1915 SDValue ValOp = GetWidenedVector(ST->getValue());
1916 DebugLoc dl = N->getDebugLoc();
1918 MVT StVT = ST->getMemoryVT();
1919 MVT ValVT = ValOp.getValueType();
1920 // It must be true that we the widen vector type is bigger than where
1921 // we need to store.
1922 assert(StVT.isVector() && ValOp.getValueType().isVector());
1923 assert(StVT.bitsLT(ValOp.getValueType()));
1925 SmallVector<SDValue, 16> StChain;
1926 if (ST->isTruncatingStore()) {
1927 // For truncating stores, we can not play the tricks of chopping legal
1928 // vector types and bit cast it to the right type. Instead, we unroll
1930 MVT StEltVT = StVT.getVectorElementType();
1931 MVT ValEltVT = ValVT.getVectorElementType();
1932 unsigned Increment = ValEltVT.getSizeInBits() / 8;
1933 unsigned NumElts = StVT.getVectorNumElements();
1934 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
1935 DAG.getIntPtrConstant(0));
1936 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, SV,
1938 isVolatile, Align));
1939 unsigned Offset = Increment;
1940 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
1941 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
1942 BasePtr, DAG.getIntPtrConstant(Offset));
1943 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
1944 DAG.getIntPtrConstant(0));
1945 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, SV,
1946 SVOffset + Offset, StEltVT,
1947 isVolatile, MinAlign(Align, Offset)));
1951 assert(StVT.getVectorElementType() == ValVT.getVectorElementType());
1953 GenWidenVectorStores(StChain, Chain, BasePtr, SV, SVOffset,
1954 Align, isVolatile, ValOp, StVT.getSizeInBits(), dl);
1956 if (StChain.size() == 1)
1959 return DAG.getNode(ISD::TokenFactor, dl,
1960 MVT::Other,&StChain[0],StChain.size());
1963 //===----------------------------------------------------------------------===//
1964 // Vector Widening Utilities
1965 //===----------------------------------------------------------------------===//
1968 // Utility function to find a vector type and its associated element
1969 // type from a preferred width and whose vector type must be the same size
1971 // TLI: Target lowering used to determine legal types.
1972 // Width: Preferred width to store.
1973 // VecVT: Vector value type whose size we must match.
1974 // Returns NewVecVT and NewEltVT - the vector type and its associated
1976 static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width,
1978 MVT& NewEltVT, MVT& NewVecVT) {
1979 unsigned EltWidth = Width + 1;
1980 if (TLI.isTypeLegal(VecVT)) {
1981 // We start with the preferred with, making it a power of 2 and find a
1982 // legal vector type of that width. If not, we reduce it by another of 2.
1983 // For incoming type is legal, this process will end as a vector of the
1984 // smallest loadable type should always be legal.
1986 assert(EltWidth > 0);
1987 EltWidth = 1 << Log2_32(EltWidth - 1);
1988 NewEltVT = MVT::getIntegerVT(EltWidth);
1989 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
1990 NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
1991 } while (!TLI.isTypeLegal(NewVecVT) ||
1992 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
1994 // The incoming vector type is illegal and is the result of widening
1995 // a vector to a power of 2. In this case, we will use the preferred
1996 // with as long as it is a multiple of the incoming vector length.
1997 // The legalization process will eventually make this into a legal type
1998 // and remove the illegal bit converts (which would turn to stack converts
1999 // if they are allow to exist).
2001 assert(EltWidth > 0);
2002 EltWidth = 1 << Log2_32(EltWidth - 1);
2003 NewEltVT = MVT::getIntegerVT(EltWidth);
2004 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
2005 NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
2006 } while (!TLI.isTypeLegal(NewEltVT) ||
2007 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
2011 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain,
2021 // The strategy assumes that we can efficiently load powers of two widths.
2022 // The routines chops the vector into the largest power of 2 load and
2023 // can be inserted into a legal vector and then cast the result into the
2024 // vector type we want. This avoids unnecessary stack converts.
2026 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
2027 // the load is nonvolatile, we an use a wider load for the value.
2029 // Find the vector type that can load from.
2030 MVT NewEltVT, NewVecVT;
2031 unsigned NewEltVTWidth;
2032 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
2033 NewEltVTWidth = NewEltVT.getSizeInBits();
2035 SDValue LdOp = DAG.getLoad(NewEltVT, dl, Chain, BasePtr, SV, SVOffset,
2036 isVolatile, Alignment);
2037 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2038 LdChain.push_back(LdOp.getValue(1));
2040 // Check if we can load the element with one instruction
2041 if (LdWidth == NewEltVTWidth) {
2042 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
2046 LdWidth -= NewEltVTWidth;
2047 unsigned Offset = 0;
2049 while (LdWidth > 0) {
2050 unsigned Increment = NewEltVTWidth / 8;
2051 Offset += Increment;
2052 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2053 DAG.getIntPtrConstant(Increment));
2055 if (LdWidth < NewEltVTWidth) {
2056 // Our current type we are using is too large, use a smaller size by
2057 // using a smaller power of 2
2058 unsigned oNewEltVTWidth = NewEltVTWidth;
2059 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
2060 NewEltVTWidth = NewEltVT.getSizeInBits();
2061 // Readjust position and vector position based on new load type
2062 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
2063 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp);
2066 SDValue LdOp = DAG.getLoad(NewEltVT, dl, Chain, BasePtr, SV,
2067 SVOffset+Offset, isVolatile,
2068 MinAlign(Alignment, Offset));
2069 LdChain.push_back(LdOp.getValue(1));
2070 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOp,
2071 DAG.getIntPtrConstant(Idx++));
2073 LdWidth -= NewEltVTWidth;
2076 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
2079 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2089 // Breaks the stores into a series of power of 2 width stores. For any
2090 // width, we convert the vector to the vector of element size that we
2091 // want to store. This avoids requiring a stack convert.
2093 // Find a width of the element type we can store with
2094 MVT WidenVT = ValOp.getValueType();
2095 MVT NewEltVT, NewVecVT;
2097 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2098 unsigned NewEltVTWidth = NewEltVT.getSizeInBits();
2100 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, ValOp);
2101 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, VecOp,
2102 DAG.getIntPtrConstant(0));
2103 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
2104 isVolatile, Alignment);
2105 StChain.push_back(StOp);
2107 // Check if we are done
2108 if (StWidth == NewEltVTWidth) {
2113 StWidth -= NewEltVTWidth;
2114 unsigned Offset = 0;
2116 while (StWidth > 0) {
2117 unsigned Increment = NewEltVTWidth / 8;
2118 Offset += Increment;
2119 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2120 DAG.getIntPtrConstant(Increment));
2122 if (StWidth < NewEltVTWidth) {
2123 // Our current type we are using is too large, use a smaller size by
2124 // using a smaller power of 2
2125 unsigned oNewEltVTWidth = NewEltVTWidth;
2126 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2127 NewEltVTWidth = NewEltVT.getSizeInBits();
2128 // Readjust position and vector position based on new load type
2129 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
2130 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp);
2133 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, VecOp,
2134 DAG.getIntPtrConstant(Idx++));
2135 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
2136 SVOffset + Offset, isVolatile,
2137 MinAlign(Alignment, Offset)));
2138 StWidth -= NewEltVTWidth;
2142 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2143 /// input vector must have the same element type as NVT.
2144 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) {
2145 // Note that InOp might have been widened so it might already have
2146 // the right width or it might need be narrowed.
2147 MVT InVT = InOp.getValueType();
2148 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2149 "input and widen element type must match");
2150 DebugLoc dl = InOp.getNode()->getDebugLoc();
2152 // Check if InOp already has the right width.
2156 unsigned InNumElts = InVT.getVectorNumElements();
2157 unsigned WidenNumElts = NVT.getVectorNumElements();
2158 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2159 unsigned NumConcat = WidenNumElts / InNumElts;
2160 SmallVector<SDValue, 16> Ops(NumConcat);
2161 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, InVT);
2163 for (unsigned i = 1; i != NumConcat; ++i)
2166 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2169 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2170 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2171 DAG.getIntPtrConstant(0));
2173 // Fall back to extract and build.
2174 SmallVector<SDValue, 16> Ops(WidenNumElts);
2175 MVT EltVT = NVT.getVectorElementType();
2176 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2178 for (Idx = 0; Idx < MinNumElts; ++Idx)
2179 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2180 DAG.getIntPtrConstant(Idx));
2182 SDValue UndefVal = DAG.getNode(ISD::UNDEF, dl, EltVT);
2183 for ( ; Idx < WidenNumElts; ++Idx)
2184 Ops[Idx] = UndefVal;
2185 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);