1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in multiple vectors of a smaller type. For example,
19 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
26 //===----------------------------------------------------------------------===//
27 // Result Vector Scalarization: <1 x ty> -> ty.
28 //===----------------------------------------------------------------------===//
30 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
31 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
33 SDOperand R = SDOperand();
35 switch (N->getOpcode()) {
38 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
39 N->dump(&DAG); cerr << "\n";
41 assert(0 && "Do not know how to scalarize the result of this operator!");
44 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
45 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N)); break;
62 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
68 case ISD::FCOS: R = ScalarizeVecRes_UnaryOp(N); break;
70 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
71 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
72 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
73 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
74 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
75 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
78 // If R is null, the sub-method took care of registering the result.
80 SetScalarizedVector(SDOperand(N, ResNo), R);
83 SDOperand DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
84 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
87 SDOperand DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
88 assert(ISD::isNormalLoad(N) && "Extending load of one-element vector?");
89 SDOperand Result = DAG.getLoad(N->getValueType(0).getVectorElementType(),
90 N->getChain(), N->getBasePtr(),
91 N->getSrcValue(), N->getSrcValueOffset(),
92 N->isVolatile(), N->getAlignment());
94 // Legalized the chain result - switch anything that used the old chain to
96 ReplaceValueWith(SDOperand(N, 1), Result.getValue(1));
100 SDOperand DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
101 SDOperand LHS = GetScalarizedVector(N->getOperand(0));
102 SDOperand RHS = GetScalarizedVector(N->getOperand(1));
103 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
106 SDOperand DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
107 SDOperand Op = GetScalarizedVector(N->getOperand(0));
108 return DAG.getNode(N->getOpcode(), Op.getValueType(), Op);
111 SDOperand DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
112 SDOperand Op = GetScalarizedVector(N->getOperand(0));
113 return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
116 SDOperand DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
117 // The value to insert may have a wider type than the vector element type,
118 // so be sure to truncate it to the element type if necessary.
119 SDOperand Op = N->getOperand(1);
120 MVT EltVT = N->getValueType(0).getVectorElementType();
121 if (Op.getValueType() != EltVT)
122 // FIXME: Can this happen for floating point types?
123 Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
127 SDOperand DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
128 // Figure out if the scalar is the LHS or RHS and return it.
129 SDOperand EltNum = N->getOperand(2).getOperand(0);
130 unsigned Op = cast<ConstantSDNode>(EltNum)->getValue() != 0;
131 return GetScalarizedVector(N->getOperand(Op));
134 SDOperand DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
135 MVT NewVT = N->getValueType(0).getVectorElementType();
136 return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
139 SDOperand DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
140 SDOperand LHS = GetScalarizedVector(N->getOperand(1));
141 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
142 GetScalarizedVector(N->getOperand(2)));
146 //===----------------------------------------------------------------------===//
147 // Operand Vector Scalarization <1 x ty> -> ty.
148 //===----------------------------------------------------------------------===//
150 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
151 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
153 SDOperand Res = SDOperand();
156 switch (N->getOpcode()) {
159 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
160 N->dump(&DAG); cerr << "\n";
162 assert(0 && "Do not know how to scalarize this operator's operand!");
165 case ISD::BIT_CONVERT:
166 Res = ScalarizeVecOp_BIT_CONVERT(N); break;
168 case ISD::EXTRACT_VECTOR_ELT:
169 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
172 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
176 // If the result is null, the sub-method took care of registering results etc.
177 if (!Res.Val) return false;
179 // If the result is N, the sub-method updated N in place. Check to see if any
180 // operands are new, and if so, mark them.
182 // Mark N as new and remark N and its operands. This allows us to correctly
183 // revisit N if it needs another step of promotion and allows us to visit
184 // any new operands to N.
189 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
190 "Invalid operand expansion");
192 ReplaceValueWith(SDOperand(N, 0), Res);
196 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
197 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
198 SDOperand DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
199 SDOperand Elt = GetScalarizedVector(N->getOperand(0));
200 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
203 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
204 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
206 SDOperand DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
207 return GetScalarizedVector(N->getOperand(0));
210 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
211 /// scalarized, it must be <1 x ty>. Just store the element.
212 SDOperand DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
213 assert(ISD::isNormalStore(N) && "Truncating store of one-element vector?");
214 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
215 return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
216 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
217 N->isVolatile(), N->getAlignment());
221 //===----------------------------------------------------------------------===//
222 // Result Vector Splitting
223 //===----------------------------------------------------------------------===//
225 /// SplitVectorResult - This method is called when the specified result of the
226 /// specified node is found to need vector splitting. At this point, the node
227 /// may also have invalid operands or may have other results that need
228 /// legalization, we just know that (at least) one result needs vector
230 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
231 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
234 switch (N->getOpcode()) {
237 cerr << "SplitVectorResult #" << ResNo << ": ";
238 N->dump(&DAG); cerr << "\n";
240 assert(0 && "Do not know how to split the result of this operator!");
243 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
244 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
245 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
246 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
249 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
251 case ISD::INSERT_VECTOR_ELT:SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
252 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
253 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
254 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
255 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
264 case ISD::FP_TO_SINT:
265 case ISD::FP_TO_UINT:
266 case ISD::SINT_TO_FP:
267 case ISD::UINT_TO_FP: SplitVecRes_UnOp(N, Lo, Hi); break;
283 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
284 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
287 // If Lo/Hi is null, the sub-method took care of registering results etc.
289 SetSplitVector(SDOperand(N, ResNo), Lo, Hi);
292 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDOperand &Lo,
294 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
296 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
298 SDOperand Ch = LD->getChain();
299 SDOperand Ptr = LD->getBasePtr();
300 const Value *SV = LD->getSrcValue();
301 int SVOffset = LD->getSrcValueOffset();
302 unsigned Alignment = LD->getAlignment();
303 bool isVolatile = LD->isVolatile();
305 Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
307 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
308 unsigned IncrementSize = LoVT.getSizeInBits()/8;
309 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
310 DAG.getIntPtrConstant(IncrementSize));
311 SVOffset += IncrementSize;
312 Alignment = MinAlign(Alignment, IncrementSize);
313 Hi = DAG.getLoad(HiVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
315 // Build a factor node to remember that this load is independent of the
317 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
320 assert(LD->getExtensionType() == ISD::EXTLOAD &&
321 "Unsupported vector extending load!");
322 Hi = DAG.getNode(ISD::UNDEF, HiVT);
326 // Legalized the chain result - switch anything that used the old chain to
328 ReplaceValueWith(SDOperand(LD, 1), Ch);
331 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo,
333 SDOperand Vec = N->getOperand(0);
334 SDOperand Elt = N->getOperand(1);
335 SDOperand Idx = N->getOperand(2);
336 GetSplitVector(Vec, Lo, Hi);
338 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
339 unsigned IdxVal = CIdx->getValue();
340 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
341 if (IdxVal < LoNumElts)
342 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx);
344 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt,
345 DAG.getIntPtrConstant(IdxVal - LoNumElts));
349 // Spill the vector to the stack.
350 MVT VecVT = Vec.getValueType();
351 MVT EltVT = VecVT.getVectorElementType();
352 SDOperand StackPtr = DAG.CreateStackTemporary(VecVT);
353 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
355 // Store the new element. This may be larger than the vector element type,
356 // so use a truncating store.
357 SDOperand EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
358 Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
360 // Reload the vector from the stack.
361 SDOperand Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
364 SplitVecRes_LOAD(cast<LoadSDNode>(Load.Val), Lo, Hi);
367 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo,
369 // Build the low part.
370 SDOperand Mask = N->getOperand(2);
371 SmallVector<SDOperand, 16> Ops;
373 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
374 MVT EltVT = LoVT.getVectorElementType();
375 unsigned LoNumElts = LoVT.getVectorNumElements();
376 unsigned NumElements = Mask.getNumOperands();
378 // Insert all of the elements from the input that are needed. We use
379 // buildvector of extractelement here because the input vectors will have
380 // to be legalized, so this makes the code simpler.
381 for (unsigned i = 0; i != LoNumElts; ++i) {
382 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
383 SDOperand InVec = N->getOperand(0);
384 if (Idx >= NumElements) {
385 InVec = N->getOperand(1);
388 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
389 DAG.getIntPtrConstant(Idx)));
391 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size());
394 for (unsigned i = LoNumElts; i != NumElements; ++i) {
395 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
396 SDOperand InVec = N->getOperand(0);
397 if (Idx >= NumElements) {
398 InVec = N->getOperand(1);
401 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
402 DAG.getIntPtrConstant(Idx)));
404 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
407 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo,
410 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
411 unsigned LoNumElts = LoVT.getVectorNumElements();
412 SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
413 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
415 SmallVector<SDOperand, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
416 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
419 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDOperand &Lo,
421 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
422 unsigned NumSubvectors = N->getNumOperands() / 2;
423 if (NumSubvectors == 1) {
424 Lo = N->getOperand(0);
425 Hi = N->getOperand(1);
430 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
432 SmallVector<SDOperand, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
433 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
435 SmallVector<SDOperand, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
436 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
439 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDOperand &Lo,
441 // We know the result is a vector. The input may be either a vector or a
444 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
446 SDOperand InOp = N->getOperand(0);
447 MVT InVT = InOp.getValueType();
449 // Handle some special cases efficiently.
450 switch (getTypeAction(InVT)) {
452 assert(false && "Unknown type action!");
456 case ScalarizeVector:
460 // A scalar to vector conversion, where the scalar needs expansion.
461 // If the vector is being split in two then we can just convert the
464 GetExpandedOp(InOp, Lo, Hi);
465 if (TLI.isBigEndian())
467 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
468 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
473 // If the input is a vector that needs to be split, convert each split
474 // piece of the input now.
475 GetSplitVector(InOp, Lo, Hi);
476 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
477 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
481 // In the general case, convert the input to an integer and split it by hand.
482 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
483 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
484 if (TLI.isBigEndian())
485 std::swap(LoIntVT, HiIntVT);
487 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
489 if (TLI.isBigEndian())
491 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
492 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
495 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDOperand &Lo,
497 SDOperand LHSLo, LHSHi;
498 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
499 SDOperand RHSLo, RHSHi;
500 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
502 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
503 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
506 void DAGTypeLegalizer::SplitVecRes_UnOp(SDNode *N, SDOperand &Lo,
508 // Get the dest types. This doesn't always match input types, e.g. int_to_fp.
510 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
512 GetSplitVector(N->getOperand(0), Lo, Hi);
513 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
514 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
517 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDOperand &Lo,
519 GetSplitVector(N->getOperand(0), Lo, Hi);
520 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
521 Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
525 //===----------------------------------------------------------------------===//
526 // Operand Vector Splitting
527 //===----------------------------------------------------------------------===//
529 /// SplitVectorOperand - This method is called when the specified operand of the
530 /// specified node is found to need vector splitting. At this point, all of the
531 /// result types of the node are known to be legal, but other operands of the
532 /// node may need legalization as well as the specified one.
533 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
534 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
535 SDOperand Res = SDOperand();
538 switch (N->getOpcode()) {
541 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
542 N->dump(&DAG); cerr << "\n";
544 assert(0 && "Do not know how to split this operator's operand!");
546 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
548 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
550 case ISD::EXTRACT_VECTOR_ELT: Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
551 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
552 case ISD::VECTOR_SHUFFLE:
553 Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);
558 // If the result is null, the sub-method took care of registering results etc.
559 if (!Res.Val) return false;
561 // If the result is N, the sub-method updated N in place. Check to see if any
562 // operands are new, and if so, mark them.
564 // Mark N as new and remark N and its operands. This allows us to correctly
565 // revisit N if it needs another step of promotion and allows us to visit
566 // any new operands to N.
571 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
572 "Invalid operand expansion");
574 ReplaceValueWith(SDOperand(N, 0), Res);
578 SDOperand DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
579 assert(ISD::isNormalStore(N) && "Truncating store of vector?");
580 assert(OpNo == 1 && "Can only split the stored value");
582 SDOperand Ch = N->getChain();
583 SDOperand Ptr = N->getBasePtr();
584 int SVOffset = N->getSrcValueOffset();
585 unsigned Alignment = N->getAlignment();
586 bool isVol = N->isVolatile();
588 GetSplitVector(N->getOperand(1), Lo, Hi);
590 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
592 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, isVol, Alignment);
594 // Increment the pointer to the other half.
595 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
596 DAG.getIntPtrConstant(IncrementSize));
598 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
599 isVol, MinAlign(Alignment, IncrementSize));
600 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
603 SDOperand DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
604 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
605 // end up being split all the way down to individual components. Convert the
606 // split pieces into integers and reassemble.
608 GetSplitVector(N->getOperand(0), Lo, Hi);
609 Lo = BitConvertToInteger(Lo);
610 Hi = BitConvertToInteger(Hi);
612 if (TLI.isBigEndian())
615 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
616 JoinIntegers(Lo, Hi));
619 SDOperand DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
620 SDOperand Vec = N->getOperand(0);
621 SDOperand Idx = N->getOperand(1);
622 MVT VecVT = Vec.getValueType();
624 if (isa<ConstantSDNode>(Idx)) {
625 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
626 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
629 GetSplitVector(Vec, Lo, Hi);
631 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
634 return DAG.UpdateNodeOperands(SDOperand(N, 0), Lo, Idx);
636 return DAG.UpdateNodeOperands(SDOperand(N, 0), Hi,
637 DAG.getConstant(IdxVal - LoElts,
638 Idx.getValueType()));
641 // Store the vector to the stack.
642 MVT EltVT = VecVT.getVectorElementType();
643 SDOperand StackPtr = DAG.CreateStackTemporary(VecVT);
644 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
646 // Load back the required element.
647 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
648 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
651 SDOperand DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
652 // We know that the extracted result type is legal. For now, assume the index
654 MVT SubVT = N->getValueType(0);
655 SDOperand Idx = N->getOperand(1);
657 GetSplitVector(N->getOperand(0), Lo, Hi);
659 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
660 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getValue();
662 if (IdxVal < LoElts) {
663 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
664 "Extracted subvector crosses vector split!");
665 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
667 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
668 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
672 SDOperand DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo){
673 assert(OpNo == 2 && "Shuffle source type differs from result type?");
674 SDOperand Mask = N->getOperand(2);
675 unsigned MaskLength = Mask.getValueType().getVectorNumElements();
676 unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
677 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
679 // Look for a legal vector type to place the mask values in.
680 // Note that there may not be *any* legal vector-of-integer
681 // type for which the element type is legal!
682 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
683 EltVT <= MVT::LAST_INTEGER_VALUETYPE;
684 // Integer values types are consecutively numbered. Exploit this.
685 EltVT = MVT::SimpleValueType(EltVT + 1)) {
687 // Is the element type big enough to hold the values?
688 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
692 // Is the vector type legal?
693 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
694 if (!isTypeLegal(VecVT))
698 // If the element type is not legal, find a larger legal type to use for
699 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
700 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
701 // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
702 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
703 // Integer values types are consecutively numbered. Exploit this.
704 OpVT = MVT::SimpleValueType(OpVT + 1)) {
705 if (!isTypeLegal(OpVT))
708 // Success! Rebuild the vector using the legal types.
709 SmallVector<SDOperand, 16> Ops(MaskLength);
710 for (unsigned i = 0; i < MaskLength; ++i) {
712 cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
713 Ops[i] = DAG.getConstant(Idx, OpVT);
715 return DAG.UpdateNodeOperands(SDOperand(N,0),
716 N->getOperand(0), N->getOperand(1),
717 DAG.getNode(ISD::BUILD_VECTOR,
718 VecVT, &Ops[0], Ops.size()));
721 // Continuing is pointless - failure is certain.
724 assert(false && "Failed to find an appropriate mask type!");
725 return SDOperand(N, 0);