1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 //===----------------------------------------------------------------------===//
30 // Result Vector Scalarization: <1 x ty> -> ty.
31 //===----------------------------------------------------------------------===//
33 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
34 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
37 SDValue R = SDValue();
39 switch (N->getOpcode()) {
42 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
46 report_fatal_error("Do not know how to scalarize the result of this "
49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
51 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
89 case ISD::SIGN_EXTEND:
93 case ISD::ZERO_EXTEND:
94 R = ScalarizeVecRes_UnaryOp(N);
116 R = ScalarizeVecRes_BinOp(N);
119 R = ScalarizeVecRes_TernaryOp(N);
123 // If R is null, the sub-method took care of registering the result.
125 SetScalarizedVector(SDValue(N, ResNo), R);
128 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
129 SDValue LHS = GetScalarizedVector(N->getOperand(0));
130 SDValue RHS = GetScalarizedVector(N->getOperand(1));
131 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
132 LHS.getValueType(), LHS, RHS);
135 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
136 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
137 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
138 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
139 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
140 Op0.getValueType(), Op0, Op1, Op2);
143 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
145 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
146 return GetScalarizedVector(Op);
149 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
150 EVT NewVT = N->getValueType(0).getVectorElementType();
151 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
152 NewVT, N->getOperand(0));
155 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
156 EVT EltVT = N->getValueType(0).getVectorElementType();
157 SDValue InOp = N->getOperand(0);
158 // The BUILD_VECTOR operands may be of wider element types and
159 // we may need to truncate them back to the requested return type.
160 if (EltVT.isInteger())
161 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
166 EVT NewVT = N->getValueType(0).getVectorElementType();
167 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
168 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
169 Op0, DAG.getValueType(NewVT),
170 DAG.getValueType(Op0.getValueType()),
173 cast<CvtRndSatSDNode>(N)->getCvtCode());
176 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
177 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
178 N->getValueType(0).getVectorElementType(),
179 N->getOperand(0), N->getOperand(1));
182 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
183 EVT NewVT = N->getValueType(0).getVectorElementType();
184 SDValue Op = GetScalarizedVector(N->getOperand(0));
185 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(),
186 NewVT, Op, N->getOperand(1));
189 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
190 SDValue Op = GetScalarizedVector(N->getOperand(0));
191 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
192 Op.getValueType(), Op, N->getOperand(1));
195 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
196 // The value to insert may have a wider type than the vector element type,
197 // so be sure to truncate it to the element type if necessary.
198 SDValue Op = N->getOperand(1);
199 EVT EltVT = N->getValueType(0).getVectorElementType();
200 if (Op.getValueType() != EltVT)
201 // FIXME: Can this happen for floating point types?
202 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
206 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
207 assert(N->isUnindexed() && "Indexed vector load?");
209 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
210 N->getExtensionType(),
211 N->getValueType(0).getVectorElementType(),
213 N->getChain(), N->getBasePtr(),
214 DAG.getUNDEF(N->getBasePtr().getValueType()),
216 N->getMemoryVT().getVectorElementType(),
217 N->isVolatile(), N->isNonTemporal(),
218 N->isInvariant(), N->getOriginalAlignment());
220 // Legalized the chain result - switch anything that used the old chain to
222 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
226 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
227 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
228 EVT DestVT = N->getValueType(0).getVectorElementType();
229 SDValue Op = GetScalarizedVector(N->getOperand(0));
230 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
233 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
234 EVT EltVT = N->getValueType(0).getVectorElementType();
235 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
236 SDValue LHS = GetScalarizedVector(N->getOperand(0));
237 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT,
238 LHS, DAG.getValueType(ExtVT));
241 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
242 // If the operand is wider than the vector element type then it is implicitly
243 // truncated. Make that explicit here.
244 EVT EltVT = N->getValueType(0).getVectorElementType();
245 SDValue InOp = N->getOperand(0);
246 if (InOp.getValueType() != EltVT)
247 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
251 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
252 SDValue Cond = GetScalarizedVector(N->getOperand(0));
253 SDValue LHS = GetScalarizedVector(N->getOperand(1));
254 TargetLowering::BooleanContent ScalarBool = TLI.getBooleanContents(false);
255 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true);
256 if (ScalarBool != VecBool) {
257 EVT CondVT = Cond.getValueType();
258 switch (ScalarBool) {
259 case TargetLowering::UndefinedBooleanContent:
261 case TargetLowering::ZeroOrOneBooleanContent:
262 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
263 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
264 // Vector read from all ones, scalar expects a single 1 so mask.
265 Cond = DAG.getNode(ISD::AND, N->getDebugLoc(), CondVT,
266 Cond, DAG.getConstant(1, CondVT));
268 case TargetLowering::ZeroOrNegativeOneBooleanContent:
269 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
270 VecBool == TargetLowering::ZeroOrOneBooleanContent);
271 // Vector reads from a one, scalar from all ones so sign extend.
272 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), CondVT,
273 Cond, DAG.getValueType(MVT::i1));
277 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
278 LHS.getValueType(), Cond, LHS,
279 GetScalarizedVector(N->getOperand(2)));
282 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
283 SDValue LHS = GetScalarizedVector(N->getOperand(1));
284 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
285 LHS.getValueType(), N->getOperand(0), LHS,
286 GetScalarizedVector(N->getOperand(2)));
289 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
290 SDValue LHS = GetScalarizedVector(N->getOperand(2));
291 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
292 N->getOperand(0), N->getOperand(1),
293 LHS, GetScalarizedVector(N->getOperand(3)),
297 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
298 assert(N->getValueType(0).isVector() ==
299 N->getOperand(0).getValueType().isVector() &&
300 "Scalar/Vector type mismatch");
302 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
304 SDValue LHS = GetScalarizedVector(N->getOperand(0));
305 SDValue RHS = GetScalarizedVector(N->getOperand(1));
306 DebugLoc DL = N->getDebugLoc();
308 // Turn it into a scalar SETCC.
309 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
312 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
313 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
316 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
317 // Figure out if the scalar is the LHS or RHS and return it.
318 SDValue Arg = N->getOperand(2).getOperand(0);
319 if (Arg.getOpcode() == ISD::UNDEF)
320 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
321 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
322 return GetScalarizedVector(N->getOperand(Op));
325 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
326 assert(N->getValueType(0).isVector() &&
327 N->getOperand(0).getValueType().isVector() &&
328 "Operand types must be vectors");
330 SDValue LHS = GetScalarizedVector(N->getOperand(0));
331 SDValue RHS = GetScalarizedVector(N->getOperand(1));
332 EVT NVT = N->getValueType(0).getVectorElementType();
333 DebugLoc DL = N->getDebugLoc();
335 // Turn it into a scalar SETCC.
336 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
338 // Vectors may have a different boolean contents to scalars. Promote the
339 // value appropriately.
340 ISD::NodeType ExtendCode =
341 TargetLowering::getExtendForContent(TLI.getBooleanContents(true));
342 return DAG.getNode(ExtendCode, DL, NVT, Res);
346 //===----------------------------------------------------------------------===//
347 // Operand Vector Scalarization <1 x ty> -> ty.
348 //===----------------------------------------------------------------------===//
350 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
351 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
354 SDValue Res = SDValue();
356 if (Res.getNode() == 0) {
357 switch (N->getOpcode()) {
360 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
364 llvm_unreachable("Do not know how to scalarize this operator's operand!");
366 Res = ScalarizeVecOp_BITCAST(N);
368 case ISD::ANY_EXTEND:
369 case ISD::ZERO_EXTEND:
370 case ISD::SIGN_EXTEND:
371 Res = ScalarizeVecOp_EXTEND(N);
373 case ISD::CONCAT_VECTORS:
374 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
376 case ISD::EXTRACT_VECTOR_ELT:
377 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
380 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
385 // If the result is null, the sub-method took care of registering results etc.
386 if (!Res.getNode()) return false;
388 // If the result is N, the sub-method updated N in place. Tell the legalizer
390 if (Res.getNode() == N)
393 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
394 "Invalid operand expansion");
396 ReplaceValueWith(SDValue(N, 0), Res);
400 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
401 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
402 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
403 SDValue Elt = GetScalarizedVector(N->getOperand(0));
404 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
405 N->getValueType(0), Elt);
408 /// ScalarizeVecOp_EXTEND - If the value to extend is a vector that needs
409 /// to be scalarized, it must be <1 x ty>. Extend the element instead.
410 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTEND(SDNode *N) {
411 assert(N->getValueType(0).getVectorNumElements() == 1 &&
412 "Unexected vector type!");
413 SDValue Elt = GetScalarizedVector(N->getOperand(0));
414 SmallVector<SDValue, 1> Ops(1);
415 Ops[0] = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
416 N->getValueType(0).getScalarType(), Elt);
417 // Revectorize the result so the types line up with what the uses of this
418 // expression expect.
419 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
423 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
424 /// use a BUILD_VECTOR instead.
425 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
426 SmallVector<SDValue, 8> Ops(N->getNumOperands());
427 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
428 Ops[i] = GetScalarizedVector(N->getOperand(i));
429 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
430 &Ops[0], Ops.size());
433 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
434 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
436 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
437 SDValue Res = GetScalarizedVector(N->getOperand(0));
438 if (Res.getValueType() != N->getValueType(0))
439 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
444 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
445 /// scalarized, it must be <1 x ty>. Just store the element.
446 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
447 assert(N->isUnindexed() && "Indexed store of one-element vector?");
448 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
449 DebugLoc dl = N->getDebugLoc();
451 if (N->isTruncatingStore())
452 return DAG.getTruncStore(N->getChain(), dl,
453 GetScalarizedVector(N->getOperand(1)),
454 N->getBasePtr(), N->getPointerInfo(),
455 N->getMemoryVT().getVectorElementType(),
456 N->isVolatile(), N->isNonTemporal(),
459 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
460 N->getBasePtr(), N->getPointerInfo(),
461 N->isVolatile(), N->isNonTemporal(),
462 N->getOriginalAlignment());
466 //===----------------------------------------------------------------------===//
467 // Result Vector Splitting
468 //===----------------------------------------------------------------------===//
470 /// SplitVectorResult - This method is called when the specified result of the
471 /// specified node is found to need vector splitting. At this point, the node
472 /// may also have invalid operands or may have other results that need
473 /// legalization, we just know that (at least) one result needs vector
475 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
476 DEBUG(dbgs() << "Split node result: ";
481 // See if the target wants to custom expand this node.
482 if (CustomLowerNode(N, N->getValueType(ResNo), true))
485 switch (N->getOpcode()) {
488 dbgs() << "SplitVectorResult #" << ResNo << ": ";
492 report_fatal_error("Do not know how to split the result of this "
495 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
497 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
498 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
499 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
500 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
501 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
502 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
503 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
504 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
505 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
506 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
507 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
508 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
510 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
513 SplitVecRes_SETCC(N, Lo, Hi);
515 case ISD::VECTOR_SHUFFLE:
516 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
519 case ISD::ANY_EXTEND:
520 case ISD::CONVERT_RNDSAT:
523 case ISD::CTLZ_ZERO_UNDEF:
524 case ISD::CTTZ_ZERO_UNDEF:
535 case ISD::FNEARBYINT:
539 case ISD::FP_TO_SINT:
540 case ISD::FP_TO_UINT:
545 case ISD::SIGN_EXTEND:
546 case ISD::SINT_TO_FP:
548 case ISD::UINT_TO_FP:
549 case ISD::ZERO_EXTEND:
550 SplitVecRes_UnaryOp(N, Lo, Hi);
572 SplitVecRes_BinOp(N, Lo, Hi);
575 SplitVecRes_TernaryOp(N, Lo, Hi);
579 // If Lo/Hi is null, the sub-method took care of registering results etc.
581 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
584 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
586 SDValue LHSLo, LHSHi;
587 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
588 SDValue RHSLo, RHSHi;
589 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
590 DebugLoc dl = N->getDebugLoc();
592 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
593 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
596 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
598 SDValue Op0Lo, Op0Hi;
599 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
600 SDValue Op1Lo, Op1Hi;
601 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
602 SDValue Op2Lo, Op2Hi;
603 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
604 DebugLoc dl = N->getDebugLoc();
606 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
607 Op0Lo, Op1Lo, Op2Lo);
608 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
609 Op0Hi, Op1Hi, Op2Hi);
612 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
614 // We know the result is a vector. The input may be either a vector or a
617 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
618 DebugLoc dl = N->getDebugLoc();
620 SDValue InOp = N->getOperand(0);
621 EVT InVT = InOp.getValueType();
623 // Handle some special cases efficiently.
624 switch (getTypeAction(InVT)) {
625 case TargetLowering::TypeLegal:
626 case TargetLowering::TypePromoteInteger:
627 case TargetLowering::TypeSoftenFloat:
628 case TargetLowering::TypeScalarizeVector:
629 case TargetLowering::TypeWidenVector:
631 case TargetLowering::TypeExpandInteger:
632 case TargetLowering::TypeExpandFloat:
633 // A scalar to vector conversion, where the scalar needs expansion.
634 // If the vector is being split in two then we can just convert the
637 GetExpandedOp(InOp, Lo, Hi);
638 if (TLI.isBigEndian())
640 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
641 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
645 case TargetLowering::TypeSplitVector:
646 // If the input is a vector that needs to be split, convert each split
647 // piece of the input now.
648 GetSplitVector(InOp, Lo, Hi);
649 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
650 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
654 // In the general case, convert the input to an integer and split it by hand.
655 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
656 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
657 if (TLI.isBigEndian())
658 std::swap(LoIntVT, HiIntVT);
660 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
662 if (TLI.isBigEndian())
664 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
665 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
668 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
671 DebugLoc dl = N->getDebugLoc();
672 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
673 unsigned LoNumElts = LoVT.getVectorNumElements();
674 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
675 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
677 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
678 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
681 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
683 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
684 DebugLoc dl = N->getDebugLoc();
685 unsigned NumSubvectors = N->getNumOperands() / 2;
686 if (NumSubvectors == 1) {
687 Lo = N->getOperand(0);
688 Hi = N->getOperand(1);
693 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
695 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
696 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
698 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
699 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
702 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
704 SDValue Vec = N->getOperand(0);
705 SDValue Idx = N->getOperand(1);
706 DebugLoc dl = N->getDebugLoc();
709 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
711 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
712 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
713 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
714 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements()));
717 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
719 DebugLoc dl = N->getDebugLoc();
720 GetSplitVector(N->getOperand(0), Lo, Hi);
721 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
722 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
725 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
727 SDValue LHSLo, LHSHi;
728 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
729 DebugLoc dl = N->getDebugLoc();
732 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT);
734 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
735 DAG.getValueType(LoVT));
736 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
737 DAG.getValueType(HiVT));
740 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
742 SDValue Vec = N->getOperand(0);
743 SDValue Elt = N->getOperand(1);
744 SDValue Idx = N->getOperand(2);
745 DebugLoc dl = N->getDebugLoc();
746 GetSplitVector(Vec, Lo, Hi);
748 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
749 unsigned IdxVal = CIdx->getZExtValue();
750 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
751 if (IdxVal < LoNumElts)
752 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
753 Lo.getValueType(), Lo, Elt, Idx);
755 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
756 DAG.getIntPtrConstant(IdxVal - LoNumElts));
760 // Spill the vector to the stack.
761 EVT VecVT = Vec.getValueType();
762 EVT EltVT = VecVT.getVectorElementType();
763 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
764 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
765 MachinePointerInfo(), false, false, 0);
767 // Store the new element. This may be larger than the vector element type,
768 // so use a truncating store.
769 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
770 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
772 TLI.getDataLayout()->getPrefTypeAlignment(VecType);
773 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
776 // Load the Lo part from the stack slot.
777 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
778 false, false, false, 0);
780 // Increment the pointer to the other part.
781 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
782 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
783 DAG.getIntPtrConstant(IncrementSize));
785 // Load the Hi part from the stack slot.
786 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
787 false, false, false, MinAlign(Alignment, IncrementSize));
790 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
793 DebugLoc dl = N->getDebugLoc();
794 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
795 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
796 Hi = DAG.getUNDEF(HiVT);
799 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
801 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
803 DebugLoc dl = LD->getDebugLoc();
804 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
806 ISD::LoadExtType ExtType = LD->getExtensionType();
807 SDValue Ch = LD->getChain();
808 SDValue Ptr = LD->getBasePtr();
809 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
810 EVT MemoryVT = LD->getMemoryVT();
811 unsigned Alignment = LD->getOriginalAlignment();
812 bool isVolatile = LD->isVolatile();
813 bool isNonTemporal = LD->isNonTemporal();
814 bool isInvariant = LD->isInvariant();
816 EVT LoMemVT, HiMemVT;
817 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
819 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
820 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
821 isInvariant, Alignment);
823 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
824 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
825 DAG.getIntPtrConstant(IncrementSize));
826 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
827 LD->getPointerInfo().getWithOffset(IncrementSize),
828 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment);
830 // Build a factor node to remember that this load is independent of the
832 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
835 // Legalized the chain result - switch anything that used the old chain to
837 ReplaceValueWith(SDValue(LD, 1), Ch);
840 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
841 assert(N->getValueType(0).isVector() &&
842 N->getOperand(0).getValueType().isVector() &&
843 "Operand types must be vectors");
846 DebugLoc DL = N->getDebugLoc();
847 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
850 EVT InVT = N->getOperand(0).getValueType();
851 SDValue LL, LH, RL, RH;
852 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
853 LoVT.getVectorNumElements());
854 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
855 DAG.getIntPtrConstant(0));
856 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
857 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
859 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
860 DAG.getIntPtrConstant(0));
861 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
862 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
864 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
865 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
868 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
870 // Get the dest types - they may not match the input types, e.g. int_to_fp.
872 DebugLoc dl = N->getDebugLoc();
873 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
875 // If the input also splits, handle it directly for a compile time speedup.
876 // Otherwise split it by hand.
877 EVT InVT = N->getOperand(0).getValueType();
878 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
879 GetSplitVector(N->getOperand(0), Lo, Hi);
881 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
882 LoVT.getVectorNumElements());
883 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
884 DAG.getIntPtrConstant(0));
885 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
886 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
889 if (N->getOpcode() == ISD::FP_ROUND) {
890 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
891 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
892 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
893 SDValue DTyOpLo = DAG.getValueType(LoVT);
894 SDValue DTyOpHi = DAG.getValueType(HiVT);
895 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
896 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
897 SDValue RndOp = N->getOperand(3);
898 SDValue SatOp = N->getOperand(4);
899 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
900 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
902 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
905 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
906 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
910 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
911 SDValue &Lo, SDValue &Hi) {
912 // The low and high parts of the original input give four input vectors.
914 DebugLoc dl = N->getDebugLoc();
915 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
916 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
917 EVT NewVT = Inputs[0].getValueType();
918 unsigned NewElts = NewVT.getVectorNumElements();
920 // If Lo or Hi uses elements from at most two of the four input vectors, then
921 // express it as a vector shuffle of those two inputs. Otherwise extract the
922 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
923 SmallVector<int, 16> Ops;
924 for (unsigned High = 0; High < 2; ++High) {
925 SDValue &Output = High ? Hi : Lo;
927 // Build a shuffle mask for the output, discovering on the fly which
928 // input vectors to use as shuffle operands (recorded in InputUsed).
929 // If building a suitable shuffle vector proves too hard, then bail
930 // out with useBuildVector set.
931 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
932 unsigned FirstMaskIdx = High * NewElts;
933 bool useBuildVector = false;
934 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
935 // The mask element. This indexes into the input.
936 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
938 // The input vector this mask element indexes into.
939 unsigned Input = (unsigned)Idx / NewElts;
941 if (Input >= array_lengthof(Inputs)) {
942 // The mask element does not index into any input vector.
947 // Turn the index into an offset from the start of the input vector.
948 Idx -= Input * NewElts;
950 // Find or create a shuffle vector operand to hold this input.
952 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
953 if (InputUsed[OpNo] == Input) {
954 // This input vector is already an operand.
956 } else if (InputUsed[OpNo] == -1U) {
957 // Create a new operand for this input vector.
958 InputUsed[OpNo] = Input;
963 if (OpNo >= array_lengthof(InputUsed)) {
964 // More than two input vectors used! Give up on trying to create a
965 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
966 useBuildVector = true;
970 // Add the mask index for the new shuffle vector.
971 Ops.push_back(Idx + OpNo * NewElts);
974 if (useBuildVector) {
975 EVT EltVT = NewVT.getVectorElementType();
976 SmallVector<SDValue, 16> SVOps;
978 // Extract the input elements by hand.
979 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
980 // The mask element. This indexes into the input.
981 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
983 // The input vector this mask element indexes into.
984 unsigned Input = (unsigned)Idx / NewElts;
986 if (Input >= array_lengthof(Inputs)) {
987 // The mask element is "undef" or indexes off the end of the input.
988 SVOps.push_back(DAG.getUNDEF(EltVT));
992 // Turn the index into an offset from the start of the input vector.
993 Idx -= Input * NewElts;
995 // Extract the vector element by hand.
996 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
997 Inputs[Input], DAG.getIntPtrConstant(Idx)));
1000 // Construct the Lo/Hi output using a BUILD_VECTOR.
1001 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
1002 } else if (InputUsed[0] == -1U) {
1003 // No input vectors were used! The result is undefined.
1004 Output = DAG.getUNDEF(NewVT);
1006 SDValue Op0 = Inputs[InputUsed[0]];
1007 // If only one input was used, use an undefined vector for the other.
1008 SDValue Op1 = InputUsed[1] == -1U ?
1009 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1010 // At least one input vector was used. Create a new shuffle vector.
1011 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
1019 //===----------------------------------------------------------------------===//
1020 // Operand Vector Splitting
1021 //===----------------------------------------------------------------------===//
1023 /// SplitVectorOperand - This method is called when the specified operand of the
1024 /// specified node is found to need vector splitting. At this point, all of the
1025 /// result types of the node are known to be legal, but other operands of the
1026 /// node may need legalization as well as the specified one.
1027 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1028 DEBUG(dbgs() << "Split node operand: ";
1031 SDValue Res = SDValue();
1033 if (Res.getNode() == 0) {
1034 switch (N->getOpcode()) {
1037 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1041 report_fatal_error("Do not know how to split this operator's "
1044 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1045 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1046 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1047 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1048 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1049 case ISD::TRUNCATE: Res = SplitVecOp_TRUNCATE(N); break;
1050 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1052 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1055 Res = SplitVecOp_VSELECT(N, OpNo);
1060 case ISD::FP_EXTEND:
1061 case ISD::FP_TO_SINT:
1062 case ISD::FP_TO_UINT:
1063 case ISD::SINT_TO_FP:
1064 case ISD::UINT_TO_FP:
1066 case ISD::SIGN_EXTEND:
1067 case ISD::ZERO_EXTEND:
1068 case ISD::ANY_EXTEND:
1069 Res = SplitVecOp_UnaryOp(N);
1074 // If the result is null, the sub-method took care of registering results etc.
1075 if (!Res.getNode()) return false;
1077 // If the result is N, the sub-method updated N in place. Tell the legalizer
1079 if (Res.getNode() == N)
1082 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1083 "Invalid operand expansion");
1085 ReplaceValueWith(SDValue(N, 0), Res);
1089 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1090 // The only possibility for an illegal operand is the mask, since result type
1091 // legalization would have handled this node already otherwise.
1092 assert(OpNo == 0 && "Illegal operand must be mask");
1094 SDValue Mask = N->getOperand(0);
1095 SDValue Src0 = N->getOperand(1);
1096 SDValue Src1 = N->getOperand(2);
1097 DebugLoc DL = N->getDebugLoc();
1098 EVT MaskVT = Mask.getValueType();
1099 assert(MaskVT.isVector() && "VSELECT without a vector mask?");
1102 GetSplitVector(N->getOperand(0), Lo, Hi);
1103 assert(Lo.getValueType() == Hi.getValueType() &&
1104 "Lo and Hi have differing types");;
1106 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
1107 unsigned HiNumElts = Hi.getValueType().getVectorNumElements();
1108 assert(LoNumElts == HiNumElts && "Asymmetric vector split?");
1110 LLVMContext &Ctx = *DAG.getContext();
1111 SDValue Zero = DAG.getIntPtrConstant(0);
1112 SDValue LoElts = DAG.getIntPtrConstant(LoNumElts);
1113 EVT Src0VT = Src0.getValueType();
1114 EVT Src0EltTy = Src0VT.getVectorElementType();
1115 EVT MaskEltTy = MaskVT.getVectorElementType();
1117 EVT LoOpVT = EVT::getVectorVT(Ctx, Src0EltTy, LoNumElts);
1118 EVT LoMaskVT = EVT::getVectorVT(Ctx, MaskEltTy, LoNumElts);
1119 EVT HiOpVT = EVT::getVectorVT(Ctx, Src0EltTy, HiNumElts);
1120 EVT HiMaskVT = EVT::getVectorVT(Ctx, MaskEltTy, HiNumElts);
1122 SDValue LoOp0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoOpVT, Src0, Zero);
1123 SDValue LoOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoOpVT, Src1, Zero);
1125 SDValue HiOp0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiOpVT, Src0, LoElts);
1126 SDValue HiOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiOpVT, Src1, LoElts);
1129 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoMaskVT, Mask, Zero);
1131 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiMaskVT, Mask, LoElts);
1134 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1136 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1138 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1141 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1142 // The result has a legal vector type, but the input needs splitting.
1143 EVT ResVT = N->getValueType(0);
1145 DebugLoc dl = N->getDebugLoc();
1146 GetSplitVector(N->getOperand(0), Lo, Hi);
1147 EVT InVT = Lo.getValueType();
1149 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1150 InVT.getVectorNumElements());
1152 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1153 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1155 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1158 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1159 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1160 // end up being split all the way down to individual components. Convert the
1161 // split pieces into integers and reassemble.
1163 GetSplitVector(N->getOperand(0), Lo, Hi);
1164 Lo = BitConvertToInteger(Lo);
1165 Hi = BitConvertToInteger(Hi);
1167 if (TLI.isBigEndian())
1170 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
1171 JoinIntegers(Lo, Hi));
1174 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1175 // We know that the extracted result type is legal.
1176 EVT SubVT = N->getValueType(0);
1177 SDValue Idx = N->getOperand(1);
1178 DebugLoc dl = N->getDebugLoc();
1180 GetSplitVector(N->getOperand(0), Lo, Hi);
1182 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1183 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1185 if (IdxVal < LoElts) {
1186 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1187 "Extracted subvector crosses vector split!");
1188 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1190 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1191 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1195 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1196 SDValue Vec = N->getOperand(0);
1197 SDValue Idx = N->getOperand(1);
1198 EVT VecVT = Vec.getValueType();
1200 if (isa<ConstantSDNode>(Idx)) {
1201 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1202 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1205 GetSplitVector(Vec, Lo, Hi);
1207 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1209 if (IdxVal < LoElts)
1210 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1211 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1212 DAG.getConstant(IdxVal - LoElts,
1213 Idx.getValueType())), 0);
1216 // Store the vector to the stack.
1217 EVT EltVT = VecVT.getVectorElementType();
1218 DebugLoc dl = N->getDebugLoc();
1219 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1220 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1221 MachinePointerInfo(), false, false, 0);
1223 // Load back the required element.
1224 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1225 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1226 MachinePointerInfo(), EltVT, false, false, 0);
1229 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1230 assert(N->isUnindexed() && "Indexed store of vector?");
1231 assert(OpNo == 1 && "Can only split the stored value");
1232 DebugLoc DL = N->getDebugLoc();
1234 bool isTruncating = N->isTruncatingStore();
1235 SDValue Ch = N->getChain();
1236 SDValue Ptr = N->getBasePtr();
1237 EVT MemoryVT = N->getMemoryVT();
1238 unsigned Alignment = N->getOriginalAlignment();
1239 bool isVol = N->isVolatile();
1240 bool isNT = N->isNonTemporal();
1242 GetSplitVector(N->getOperand(1), Lo, Hi);
1244 EVT LoMemVT, HiMemVT;
1245 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1247 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1250 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1251 LoMemVT, isVol, isNT, Alignment);
1253 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1254 isVol, isNT, Alignment);
1256 // Increment the pointer to the other half.
1257 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1258 DAG.getIntPtrConstant(IncrementSize));
1261 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1262 N->getPointerInfo().getWithOffset(IncrementSize),
1263 HiMemVT, isVol, isNT, Alignment);
1265 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1266 N->getPointerInfo().getWithOffset(IncrementSize),
1267 isVol, isNT, Alignment);
1269 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1272 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1273 DebugLoc DL = N->getDebugLoc();
1275 // The input operands all must have the same type, and we know the result
1276 // type is valid. Convert this to a buildvector which extracts all the
1278 // TODO: If the input elements are power-two vectors, we could convert this to
1279 // a new CONCAT_VECTORS node with elements that are half-wide.
1280 SmallVector<SDValue, 32> Elts;
1281 EVT EltVT = N->getValueType(0).getVectorElementType();
1282 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1283 SDValue Op = N->getOperand(op);
1284 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1286 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1287 Op, DAG.getIntPtrConstant(i)));
1292 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
1293 &Elts[0], Elts.size());
1296 SDValue DAGTypeLegalizer::SplitVecOp_TRUNCATE(SDNode *N) {
1297 // The result type is legal, but the input type is illegal. If splitting
1298 // ends up with the result type of each half still being legal, just
1299 // do that. If, however, that would result in an illegal result type,
1300 // we can try to get more clever with power-two vectors. Specifically,
1301 // split the input type, but also widen the result element size, then
1302 // concatenate the halves and truncate again. For example, consider a target
1303 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1304 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1305 // %inlo = v4i32 extract_subvector %in, 0
1306 // %inhi = v4i32 extract_subvector %in, 4
1307 // %lo16 = v4i16 trunc v4i32 %inlo
1308 // %hi16 = v4i16 trunc v4i32 %inhi
1309 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1310 // %res = v8i8 trunc v8i16 %in16
1312 // Without this transform, the original truncate would end up being
1313 // scalarized, which is pretty much always a last resort.
1314 SDValue InVec = N->getOperand(0);
1315 EVT InVT = InVec->getValueType(0);
1316 EVT OutVT = N->getValueType(0);
1317 unsigned NumElements = OutVT.getVectorNumElements();
1318 // Widening should have already made sure this is a power-two vector
1319 // if we're trying to split it at all. assert() that's true, just in case.
1320 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1322 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1323 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1325 // If the input elements are only 1/2 the width of the result elements,
1326 // just use the normal splitting. Our trick only work if there's room
1327 // to split more than once.
1328 if (InElementSize <= OutElementSize * 2)
1329 return SplitVecOp_UnaryOp(N);
1330 DebugLoc DL = N->getDebugLoc();
1332 // Extract the halves of the input via extract_subvector.
1333 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(),
1334 InVT.getVectorElementType(), NumElements/2);
1335 SDValue InLoVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, InVec,
1336 DAG.getIntPtrConstant(0));
1337 SDValue InHiVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, InVec,
1338 DAG.getIntPtrConstant(NumElements/2));
1339 // Truncate them to 1/2 the element size.
1340 EVT HalfElementVT = EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1341 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1343 SDValue HalfLo = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InLoVec);
1344 SDValue HalfHi = DAG.getNode(ISD::TRUNCATE, DL, HalfVT, InHiVec);
1345 // Concatenate them to get the full intermediate truncation result.
1346 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1347 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1349 // Now finish up by truncating all the way down to the original result
1350 // type. This should normally be something that ends up being legal directly,
1351 // but in theory if a target has very wide vectors and an annoyingly
1352 // restricted set of legal types, this split can chain to build things up.
1353 return DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1356 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1357 assert(N->getValueType(0).isVector() &&
1358 N->getOperand(0).getValueType().isVector() &&
1359 "Operand types must be vectors");
1360 // The result has a legal vector type, but the input needs splitting.
1361 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1362 DebugLoc DL = N->getDebugLoc();
1363 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1364 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1365 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1366 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1367 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1369 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1370 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1371 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1372 return PromoteTargetBoolean(Con, N->getValueType(0));
1376 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1377 // The result has a legal vector type, but the input needs splitting.
1378 EVT ResVT = N->getValueType(0);
1380 DebugLoc DL = N->getDebugLoc();
1381 GetSplitVector(N->getOperand(0), Lo, Hi);
1382 EVT InVT = Lo.getValueType();
1384 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1385 InVT.getVectorNumElements());
1387 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1388 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1390 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1395 //===----------------------------------------------------------------------===//
1396 // Result Vector Widening
1397 //===----------------------------------------------------------------------===//
1399 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1400 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1404 // See if the target wants to custom widen this node.
1405 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1408 SDValue Res = SDValue();
1409 switch (N->getOpcode()) {
1412 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1416 llvm_unreachable("Do not know how to widen the result of this operator!");
1418 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1419 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1420 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1421 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1422 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1423 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1424 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1425 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1426 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1427 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1428 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1430 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1431 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1432 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1433 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1434 case ISD::VECTOR_SHUFFLE:
1435 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1441 case ISD::FCOPYSIGN:
1457 Res = WidenVecRes_Binary(N);
1461 Res = WidenVecRes_POWI(N);
1467 Res = WidenVecRes_Shift(N);
1470 case ISD::ANY_EXTEND:
1471 case ISD::FP_EXTEND:
1473 case ISD::FP_TO_SINT:
1474 case ISD::FP_TO_UINT:
1475 case ISD::SIGN_EXTEND:
1476 case ISD::SINT_TO_FP:
1478 case ISD::UINT_TO_FP:
1479 case ISD::ZERO_EXTEND:
1480 Res = WidenVecRes_Convert(N);
1495 case ISD::FNEARBYINT:
1501 Res = WidenVecRes_Unary(N);
1504 Res = WidenVecRes_Ternary(N);
1508 // If Res is null, the sub-method took care of registering the result.
1510 SetWidenedVector(SDValue(N, ResNo), Res);
1513 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
1514 // Ternary op widening.
1515 DebugLoc dl = N->getDebugLoc();
1516 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1517 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1518 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1519 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
1520 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
1523 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1524 // Binary op widening.
1525 unsigned Opcode = N->getOpcode();
1526 DebugLoc dl = N->getDebugLoc();
1527 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1528 EVT WidenEltVT = WidenVT.getVectorElementType();
1530 unsigned NumElts = VT.getVectorNumElements();
1531 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1532 NumElts = NumElts / 2;
1533 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1536 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1537 // Operation doesn't trap so just widen as normal.
1538 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1539 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1540 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1543 // No legal vector version so unroll the vector operation and then widen.
1545 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1547 // Since the operation can trap, apply operation on the original vector.
1549 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1550 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1551 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1553 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1554 unsigned ConcatEnd = 0; // Current ConcatOps index.
1555 int Idx = 0; // Current Idx into input vectors.
1557 // NumElts := greatest legal vector size (at most WidenVT)
1558 // while (orig. vector has unhandled elements) {
1559 // take munches of size NumElts from the beginning and add to ConcatOps
1560 // NumElts := next smaller supported vector size or 1
1562 while (CurNumElts != 0) {
1563 while (CurNumElts >= NumElts) {
1564 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1565 DAG.getIntPtrConstant(Idx));
1566 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1567 DAG.getIntPtrConstant(Idx));
1568 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1570 CurNumElts -= NumElts;
1573 NumElts = NumElts / 2;
1574 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1575 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1578 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1579 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1580 InOp1, DAG.getIntPtrConstant(Idx));
1581 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1582 InOp2, DAG.getIntPtrConstant(Idx));
1583 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1590 // Check to see if we have a single operation with the widen type.
1591 if (ConcatEnd == 1) {
1592 VT = ConcatOps[0].getValueType();
1594 return ConcatOps[0];
1597 // while (Some element of ConcatOps is not of type MaxVT) {
1598 // From the end of ConcatOps, collect elements of the same type and put
1599 // them into an op of the next larger supported type
1601 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1602 Idx = ConcatEnd - 1;
1603 VT = ConcatOps[Idx--].getValueType();
1604 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1607 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1611 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1612 } while (!TLI.isTypeLegal(NextVT));
1614 if (!VT.isVector()) {
1615 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1616 SDValue VecOp = DAG.getUNDEF(NextVT);
1617 unsigned NumToInsert = ConcatEnd - Idx - 1;
1618 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1619 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1620 ConcatOps[OpIdx], DAG.getIntPtrConstant(i));
1622 ConcatOps[Idx+1] = VecOp;
1623 ConcatEnd = Idx + 2;
1625 // Vector type, create a CONCAT_VECTORS of type NextVT
1626 SDValue undefVec = DAG.getUNDEF(VT);
1627 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1628 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1629 unsigned RealVals = ConcatEnd - Idx - 1;
1630 unsigned SubConcatEnd = 0;
1631 unsigned SubConcatIdx = Idx + 1;
1632 while (SubConcatEnd < RealVals)
1633 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1634 while (SubConcatEnd < OpsToConcat)
1635 SubConcatOps[SubConcatEnd++] = undefVec;
1636 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1637 NextVT, &SubConcatOps[0],
1639 ConcatEnd = SubConcatIdx + 1;
1643 // Check to see if we have a single operation with the widen type.
1644 if (ConcatEnd == 1) {
1645 VT = ConcatOps[0].getValueType();
1647 return ConcatOps[0];
1650 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1651 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1652 if (NumOps != ConcatEnd ) {
1653 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1654 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1655 ConcatOps[j] = UndefVal;
1657 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps);
1660 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1661 SDValue InOp = N->getOperand(0);
1662 DebugLoc DL = N->getDebugLoc();
1664 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1665 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1667 EVT InVT = InOp.getValueType();
1668 EVT InEltVT = InVT.getVectorElementType();
1669 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1671 unsigned Opcode = N->getOpcode();
1672 unsigned InVTNumElts = InVT.getVectorNumElements();
1674 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1675 InOp = GetWidenedVector(N->getOperand(0));
1676 InVT = InOp.getValueType();
1677 InVTNumElts = InVT.getVectorNumElements();
1678 if (InVTNumElts == WidenNumElts) {
1679 if (N->getNumOperands() == 1)
1680 return DAG.getNode(Opcode, DL, WidenVT, InOp);
1681 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
1685 if (TLI.isTypeLegal(InWidenVT)) {
1686 // Because the result and the input are different vector types, widening
1687 // the result could create a legal type but widening the input might make
1688 // it an illegal type that might lead to repeatedly splitting the input
1689 // and then widening it. To avoid this, we widen the input only if
1690 // it results in a legal type.
1691 if (WidenNumElts % InVTNumElts == 0) {
1692 // Widen the input and call convert on the widened input vector.
1693 unsigned NumConcat = WidenNumElts/InVTNumElts;
1694 SmallVector<SDValue, 16> Ops(NumConcat);
1696 SDValue UndefVal = DAG.getUNDEF(InVT);
1697 for (unsigned i = 1; i != NumConcat; ++i)
1699 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT,
1700 &Ops[0], NumConcat);
1701 if (N->getNumOperands() == 1)
1702 return DAG.getNode(Opcode, DL, WidenVT, InVec);
1703 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
1706 if (InVTNumElts % WidenNumElts == 0) {
1707 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
1708 InOp, DAG.getIntPtrConstant(0));
1709 // Extract the input and convert the shorten input vector.
1710 if (N->getNumOperands() == 1)
1711 return DAG.getNode(Opcode, DL, WidenVT, InVal);
1712 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
1716 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1717 SmallVector<SDValue, 16> Ops(WidenNumElts);
1718 EVT EltVT = WidenVT.getVectorElementType();
1719 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1721 for (i=0; i < MinElts; ++i) {
1722 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
1723 DAG.getIntPtrConstant(i));
1724 if (N->getNumOperands() == 1)
1725 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
1727 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
1730 SDValue UndefVal = DAG.getUNDEF(EltVT);
1731 for (; i < WidenNumElts; ++i)
1734 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts);
1737 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
1738 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1739 SDValue InOp = GetWidenedVector(N->getOperand(0));
1740 SDValue ShOp = N->getOperand(1);
1741 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1744 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1745 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1746 SDValue InOp = GetWidenedVector(N->getOperand(0));
1747 SDValue ShOp = N->getOperand(1);
1749 EVT ShVT = ShOp.getValueType();
1750 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
1751 ShOp = GetWidenedVector(ShOp);
1752 ShVT = ShOp.getValueType();
1754 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
1755 ShVT.getVectorElementType(),
1756 WidenVT.getVectorNumElements());
1757 if (ShVT != ShWidenVT)
1758 ShOp = ModifyToType(ShOp, ShWidenVT);
1760 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1763 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1764 // Unary op widening.
1765 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1766 SDValue InOp = GetWidenedVector(N->getOperand(0));
1767 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1770 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
1771 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1772 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
1773 cast<VTSDNode>(N->getOperand(1))->getVT()
1774 .getVectorElementType(),
1775 WidenVT.getVectorNumElements());
1776 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
1777 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
1778 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
1781 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
1782 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
1783 return GetWidenedVector(WidenVec);
1786 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
1787 SDValue InOp = N->getOperand(0);
1788 EVT InVT = InOp.getValueType();
1789 EVT VT = N->getValueType(0);
1790 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1791 DebugLoc dl = N->getDebugLoc();
1793 switch (getTypeAction(InVT)) {
1794 case TargetLowering::TypeLegal:
1796 case TargetLowering::TypePromoteInteger:
1797 // If the incoming type is a vector that is being promoted, then
1798 // we know that the elements are arranged differently and that we
1799 // must perform the conversion using a stack slot.
1800 if (InVT.isVector())
1803 // If the InOp is promoted to the same size, convert it. Otherwise,
1804 // fall out of the switch and widen the promoted input.
1805 InOp = GetPromotedInteger(InOp);
1806 InVT = InOp.getValueType();
1807 if (WidenVT.bitsEq(InVT))
1808 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1810 case TargetLowering::TypeSoftenFloat:
1811 case TargetLowering::TypeExpandInteger:
1812 case TargetLowering::TypeExpandFloat:
1813 case TargetLowering::TypeScalarizeVector:
1814 case TargetLowering::TypeSplitVector:
1816 case TargetLowering::TypeWidenVector:
1817 // If the InOp is widened to the same size, convert it. Otherwise, fall
1818 // out of the switch and widen the widened input.
1819 InOp = GetWidenedVector(InOp);
1820 InVT = InOp.getValueType();
1821 if (WidenVT.bitsEq(InVT))
1822 // The input widens to the same size. Convert to the widen value.
1823 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1827 unsigned WidenSize = WidenVT.getSizeInBits();
1828 unsigned InSize = InVT.getSizeInBits();
1829 // x86mmx is not an acceptable vector element type, so don't try.
1830 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
1831 // Determine new input vector type. The new input vector type will use
1832 // the same element type (if its a vector) or use the input type as a
1833 // vector. It is the same size as the type to widen to.
1835 unsigned NewNumElts = WidenSize / InSize;
1836 if (InVT.isVector()) {
1837 EVT InEltVT = InVT.getVectorElementType();
1838 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
1839 WidenSize / InEltVT.getSizeInBits());
1841 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
1844 if (TLI.isTypeLegal(NewInVT)) {
1845 // Because the result and the input are different vector types, widening
1846 // the result could create a legal type but widening the input might make
1847 // it an illegal type that might lead to repeatedly splitting the input
1848 // and then widening it. To avoid this, we widen the input only if
1849 // it results in a legal type.
1850 SmallVector<SDValue, 16> Ops(NewNumElts);
1851 SDValue UndefVal = DAG.getUNDEF(InVT);
1853 for (unsigned i = 1; i < NewNumElts; ++i)
1857 if (InVT.isVector())
1858 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1859 NewInVT, &Ops[0], NewNumElts);
1861 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1862 NewInVT, &Ops[0], NewNumElts);
1863 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
1867 return CreateStackStoreLoad(InOp, WidenVT);
1870 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1871 DebugLoc dl = N->getDebugLoc();
1872 // Build a vector with undefined for the new nodes.
1873 EVT VT = N->getValueType(0);
1874 EVT EltVT = VT.getVectorElementType();
1875 unsigned NumElts = VT.getVectorNumElements();
1877 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1878 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1880 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1881 NewOps.reserve(WidenNumElts);
1882 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1883 NewOps.push_back(DAG.getUNDEF(EltVT));
1885 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1888 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1889 EVT InVT = N->getOperand(0).getValueType();
1890 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1891 DebugLoc dl = N->getDebugLoc();
1892 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1893 unsigned NumInElts = InVT.getVectorNumElements();
1894 unsigned NumOperands = N->getNumOperands();
1896 bool InputWidened = false; // Indicates we need to widen the input.
1897 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
1898 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1899 // Add undef vectors to widen to correct length.
1900 unsigned NumConcat = WidenVT.getVectorNumElements() /
1901 InVT.getVectorNumElements();
1902 SDValue UndefVal = DAG.getUNDEF(InVT);
1903 SmallVector<SDValue, 16> Ops(NumConcat);
1904 for (unsigned i=0; i < NumOperands; ++i)
1905 Ops[i] = N->getOperand(i);
1906 for (unsigned i = NumOperands; i != NumConcat; ++i)
1908 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1911 InputWidened = true;
1912 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
1913 // The inputs and the result are widen to the same value.
1915 for (i=1; i < NumOperands; ++i)
1916 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1919 if (i == NumOperands)
1920 // Everything but the first operand is an UNDEF so just return the
1921 // widened first operand.
1922 return GetWidenedVector(N->getOperand(0));
1924 if (NumOperands == 2) {
1925 // Replace concat of two operands with a shuffle.
1926 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
1927 for (unsigned i = 0; i < NumInElts; ++i) {
1929 MaskOps[i + NumInElts] = i + WidenNumElts;
1931 return DAG.getVectorShuffle(WidenVT, dl,
1932 GetWidenedVector(N->getOperand(0)),
1933 GetWidenedVector(N->getOperand(1)),
1939 // Fall back to use extracts and build vector.
1940 EVT EltVT = WidenVT.getVectorElementType();
1941 SmallVector<SDValue, 16> Ops(WidenNumElts);
1943 for (unsigned i=0; i < NumOperands; ++i) {
1944 SDValue InOp = N->getOperand(i);
1946 InOp = GetWidenedVector(InOp);
1947 for (unsigned j=0; j < NumInElts; ++j)
1948 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1949 DAG.getIntPtrConstant(j));
1951 SDValue UndefVal = DAG.getUNDEF(EltVT);
1952 for (; Idx < WidenNumElts; ++Idx)
1953 Ops[Idx] = UndefVal;
1954 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1957 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1958 DebugLoc dl = N->getDebugLoc();
1959 SDValue InOp = N->getOperand(0);
1960 SDValue RndOp = N->getOperand(3);
1961 SDValue SatOp = N->getOperand(4);
1963 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1964 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1966 EVT InVT = InOp.getValueType();
1967 EVT InEltVT = InVT.getVectorElementType();
1968 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1970 SDValue DTyOp = DAG.getValueType(WidenVT);
1971 SDValue STyOp = DAG.getValueType(InWidenVT);
1972 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1974 unsigned InVTNumElts = InVT.getVectorNumElements();
1975 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1976 InOp = GetWidenedVector(InOp);
1977 InVT = InOp.getValueType();
1978 InVTNumElts = InVT.getVectorNumElements();
1979 if (InVTNumElts == WidenNumElts)
1980 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1984 if (TLI.isTypeLegal(InWidenVT)) {
1985 // Because the result and the input are different vector types, widening
1986 // the result could create a legal type but widening the input might make
1987 // it an illegal type that might lead to repeatedly splitting the input
1988 // and then widening it. To avoid this, we widen the input only if
1989 // it results in a legal type.
1990 if (WidenNumElts % InVTNumElts == 0) {
1991 // Widen the input and call convert on the widened input vector.
1992 unsigned NumConcat = WidenNumElts/InVTNumElts;
1993 SmallVector<SDValue, 16> Ops(NumConcat);
1995 SDValue UndefVal = DAG.getUNDEF(InVT);
1996 for (unsigned i = 1; i != NumConcat; ++i)
1999 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
2000 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2004 if (InVTNumElts % WidenNumElts == 0) {
2005 // Extract the input and convert the shorten input vector.
2006 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2007 DAG.getIntPtrConstant(0));
2008 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2013 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2014 SmallVector<SDValue, 16> Ops(WidenNumElts);
2015 EVT EltVT = WidenVT.getVectorElementType();
2016 DTyOp = DAG.getValueType(EltVT);
2017 STyOp = DAG.getValueType(InEltVT);
2019 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2021 for (i=0; i < MinElts; ++i) {
2022 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2023 DAG.getIntPtrConstant(i));
2024 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2028 SDValue UndefVal = DAG.getUNDEF(EltVT);
2029 for (; i < WidenNumElts; ++i)
2032 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
2035 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2036 EVT VT = N->getValueType(0);
2037 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2038 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2039 SDValue InOp = N->getOperand(0);
2040 SDValue Idx = N->getOperand(1);
2041 DebugLoc dl = N->getDebugLoc();
2043 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2044 InOp = GetWidenedVector(InOp);
2046 EVT InVT = InOp.getValueType();
2048 // Check if we can just return the input vector after widening.
2049 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2050 if (IdxVal == 0 && InVT == WidenVT)
2053 // Check if we can extract from the vector.
2054 unsigned InNumElts = InVT.getVectorNumElements();
2055 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2056 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2058 // We could try widening the input to the right length but for now, extract
2059 // the original elements, fill the rest with undefs and build a vector.
2060 SmallVector<SDValue, 16> Ops(WidenNumElts);
2061 EVT EltVT = VT.getVectorElementType();
2062 unsigned NumElts = VT.getVectorNumElements();
2064 for (i=0; i < NumElts; ++i)
2065 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2066 DAG.getIntPtrConstant(IdxVal+i));
2068 SDValue UndefVal = DAG.getUNDEF(EltVT);
2069 for (; i < WidenNumElts; ++i)
2071 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
2074 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2075 SDValue InOp = GetWidenedVector(N->getOperand(0));
2076 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
2077 InOp.getValueType(), InOp,
2078 N->getOperand(1), N->getOperand(2));
2081 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2082 LoadSDNode *LD = cast<LoadSDNode>(N);
2083 ISD::LoadExtType ExtType = LD->getExtensionType();
2086 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2087 if (ExtType != ISD::NON_EXTLOAD)
2088 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2090 Result = GenWidenVectorLoads(LdChain, LD);
2092 // If we generate a single load, we can use that for the chain. Otherwise,
2093 // build a factor node to remember the multiple loads are independent and
2096 if (LdChain.size() == 1)
2097 NewChain = LdChain[0];
2099 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other,
2100 &LdChain[0], LdChain.size());
2102 // Modified the chain - switch anything that used the old chain to use
2104 ReplaceValueWith(SDValue(N, 1), NewChain);
2109 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2110 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2111 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
2112 WidenVT, N->getOperand(0));
2115 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2116 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2117 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2119 SDValue Cond1 = N->getOperand(0);
2120 EVT CondVT = Cond1.getValueType();
2121 if (CondVT.isVector()) {
2122 EVT CondEltVT = CondVT.getVectorElementType();
2123 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2124 CondEltVT, WidenNumElts);
2125 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2126 Cond1 = GetWidenedVector(Cond1);
2128 if (Cond1.getValueType() != CondWidenVT)
2129 Cond1 = ModifyToType(Cond1, CondWidenVT);
2132 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2133 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2134 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2135 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
2136 WidenVT, Cond1, InOp1, InOp2);
2139 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2140 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2141 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2142 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
2143 InOp1.getValueType(), N->getOperand(0),
2144 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2147 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2148 assert(N->getValueType(0).isVector() ==
2149 N->getOperand(0).getValueType().isVector() &&
2150 "Scalar/Vector type mismatch");
2151 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2153 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2154 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2155 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2156 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
2157 InOp1, InOp2, N->getOperand(2));
2160 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2161 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2162 return DAG.getUNDEF(WidenVT);
2165 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2166 EVT VT = N->getValueType(0);
2167 DebugLoc dl = N->getDebugLoc();
2169 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2170 unsigned NumElts = VT.getVectorNumElements();
2171 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2173 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2174 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2176 // Adjust mask based on new input vector length.
2177 SmallVector<int, 16> NewMask;
2178 for (unsigned i = 0; i != NumElts; ++i) {
2179 int Idx = N->getMaskElt(i);
2180 if (Idx < (int)NumElts)
2181 NewMask.push_back(Idx);
2183 NewMask.push_back(Idx - NumElts + WidenNumElts);
2185 for (unsigned i = NumElts; i != WidenNumElts; ++i)
2186 NewMask.push_back(-1);
2187 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2190 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2191 assert(N->getValueType(0).isVector() &&
2192 N->getOperand(0).getValueType().isVector() &&
2193 "Operands must be vectors");
2194 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2195 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2197 SDValue InOp1 = N->getOperand(0);
2198 EVT InVT = InOp1.getValueType();
2199 assert(InVT.isVector() && "can not widen non vector type");
2200 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2201 InVT.getVectorElementType(), WidenNumElts);
2202 InOp1 = GetWidenedVector(InOp1);
2203 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2205 // Assume that the input and output will be widen appropriately. If not,
2206 // we will have to unroll it at some point.
2207 assert(InOp1.getValueType() == WidenInVT &&
2208 InOp2.getValueType() == WidenInVT &&
2209 "Input not widened to expected type!");
2211 return DAG.getNode(ISD::SETCC, N->getDebugLoc(),
2212 WidenVT, InOp1, InOp2, N->getOperand(2));
2216 //===----------------------------------------------------------------------===//
2217 // Widen Vector Operand
2218 //===----------------------------------------------------------------------===//
2219 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
2220 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
2223 SDValue Res = SDValue();
2225 // See if the target wants to custom widen this node.
2226 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2229 switch (N->getOpcode()) {
2232 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
2236 llvm_unreachable("Do not know how to widen this operator's operand!");
2238 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2239 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2240 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2241 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2242 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2243 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2245 case ISD::FP_EXTEND:
2246 case ISD::FP_TO_SINT:
2247 case ISD::FP_TO_UINT:
2248 case ISD::SINT_TO_FP:
2249 case ISD::UINT_TO_FP:
2251 case ISD::SIGN_EXTEND:
2252 case ISD::ZERO_EXTEND:
2253 case ISD::ANY_EXTEND:
2254 Res = WidenVecOp_Convert(N);
2258 // If Res is null, the sub-method took care of registering the result.
2259 if (!Res.getNode()) return false;
2261 // If the result is N, the sub-method updated N in place. Tell the legalizer
2263 if (Res.getNode() == N)
2267 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2268 "Invalid operand expansion");
2270 ReplaceValueWith(SDValue(N, 0), Res);
2274 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2275 // Since the result is legal and the input is illegal, it is unlikely
2276 // that we can fix the input to a legal type so unroll the convert
2277 // into some scalar code and create a nasty build vector.
2278 EVT VT = N->getValueType(0);
2279 EVT EltVT = VT.getVectorElementType();
2280 DebugLoc dl = N->getDebugLoc();
2281 unsigned NumElts = VT.getVectorNumElements();
2282 SDValue InOp = N->getOperand(0);
2283 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2284 InOp = GetWidenedVector(InOp);
2285 EVT InVT = InOp.getValueType();
2286 EVT InEltVT = InVT.getVectorElementType();
2288 unsigned Opcode = N->getOpcode();
2289 SmallVector<SDValue, 16> Ops(NumElts);
2290 for (unsigned i=0; i < NumElts; ++i)
2291 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2292 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2293 DAG.getIntPtrConstant(i)));
2295 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2298 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2299 EVT VT = N->getValueType(0);
2300 SDValue InOp = GetWidenedVector(N->getOperand(0));
2301 EVT InWidenVT = InOp.getValueType();
2302 DebugLoc dl = N->getDebugLoc();
2304 // Check if we can convert between two legal vector types and extract.
2305 unsigned InWidenSize = InWidenVT.getSizeInBits();
2306 unsigned Size = VT.getSizeInBits();
2307 // x86mmx is not an acceptable vector element type, so don't try.
2308 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2309 unsigned NewNumElts = InWidenSize / Size;
2310 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2311 if (TLI.isTypeLegal(NewVT)) {
2312 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2313 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2314 DAG.getIntPtrConstant(0));
2318 return CreateStackStoreLoad(InOp, VT);
2321 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2322 // If the input vector is not legal, it is likely that we will not find a
2323 // legal vector of the same size. Replace the concatenate vector with a
2324 // nasty build vector.
2325 EVT VT = N->getValueType(0);
2326 EVT EltVT = VT.getVectorElementType();
2327 DebugLoc dl = N->getDebugLoc();
2328 unsigned NumElts = VT.getVectorNumElements();
2329 SmallVector<SDValue, 16> Ops(NumElts);
2331 EVT InVT = N->getOperand(0).getValueType();
2332 unsigned NumInElts = InVT.getVectorNumElements();
2335 unsigned NumOperands = N->getNumOperands();
2336 for (unsigned i=0; i < NumOperands; ++i) {
2337 SDValue InOp = N->getOperand(i);
2338 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2339 InOp = GetWidenedVector(InOp);
2340 for (unsigned j=0; j < NumInElts; ++j)
2341 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2342 DAG.getIntPtrConstant(j));
2344 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2347 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2348 SDValue InOp = GetWidenedVector(N->getOperand(0));
2349 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
2350 N->getValueType(0), InOp, N->getOperand(1));
2353 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2354 SDValue InOp = GetWidenedVector(N->getOperand(0));
2355 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
2356 N->getValueType(0), InOp, N->getOperand(1));
2359 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2360 // We have to widen the value but we want only to store the original
2362 StoreSDNode *ST = cast<StoreSDNode>(N);
2364 SmallVector<SDValue, 16> StChain;
2365 if (ST->isTruncatingStore())
2366 GenWidenVectorTruncStores(StChain, ST);
2368 GenWidenVectorStores(StChain, ST);
2370 if (StChain.size() == 1)
2373 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(),
2374 MVT::Other,&StChain[0],StChain.size());
2377 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
2378 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
2379 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2380 DebugLoc dl = N->getDebugLoc();
2382 // WARNING: In this code we widen the compare instruction with garbage.
2383 // This garbage may contain denormal floats which may be slow. Is this a real
2384 // concern ? Should we zero the unused lanes if this is a float compare ?
2386 // Get a new SETCC node to compare the newly widened operands.
2387 // Only some of the compared elements are legal.
2388 EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType());
2389 SDValue WideSETCC = DAG.getNode(ISD::SETCC, N->getDebugLoc(),
2390 SVT, InOp0, InOp1, N->getOperand(2));
2392 // Extract the needed results from the result vector.
2393 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
2394 SVT.getVectorElementType(),
2395 N->getValueType(0).getVectorNumElements());
2396 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
2397 ResVT, WideSETCC, DAG.getIntPtrConstant(0));
2399 return PromoteTargetBoolean(CC, N->getValueType(0));
2403 //===----------------------------------------------------------------------===//
2404 // Vector Widening Utilities
2405 //===----------------------------------------------------------------------===//
2407 // Utility function to find the type to chop up a widen vector for load/store
2408 // TLI: Target lowering used to determine legal types.
2409 // Width: Width left need to load/store.
2410 // WidenVT: The widen vector type to load to/store from
2411 // Align: If 0, don't allow use of a wider type
2412 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2414 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2415 unsigned Width, EVT WidenVT,
2416 unsigned Align = 0, unsigned WidenEx = 0) {
2417 EVT WidenEltVT = WidenVT.getVectorElementType();
2418 unsigned WidenWidth = WidenVT.getSizeInBits();
2419 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2420 unsigned AlignInBits = Align*8;
2422 // If we have one element to load/store, return it.
2423 EVT RetVT = WidenEltVT;
2424 if (Width == WidenEltWidth)
2427 // See if there is larger legal integer than the element type to load/store
2429 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2430 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2431 EVT MemVT((MVT::SimpleValueType) VT);
2432 unsigned MemVTWidth = MemVT.getSizeInBits();
2433 if (MemVT.getSizeInBits() <= WidenEltWidth)
2435 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2436 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2437 (MemVTWidth <= Width ||
2438 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2444 // See if there is a larger vector type to load/store that has the same vector
2445 // element type and is evenly divisible with the WidenVT.
2446 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2447 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2448 EVT MemVT = (MVT::SimpleValueType) VT;
2449 unsigned MemVTWidth = MemVT.getSizeInBits();
2450 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2451 (WidenWidth % MemVTWidth) == 0 &&
2452 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2453 (MemVTWidth <= Width ||
2454 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2455 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2463 // Builds a vector type from scalar loads
2464 // VecTy: Resulting Vector type
2465 // LDOps: Load operators to build a vector type
2466 // [Start,End) the list of loads to use.
2467 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2468 SmallVector<SDValue, 16>& LdOps,
2469 unsigned Start, unsigned End) {
2470 DebugLoc dl = LdOps[Start].getDebugLoc();
2471 EVT LdTy = LdOps[Start].getValueType();
2472 unsigned Width = VecTy.getSizeInBits();
2473 unsigned NumElts = Width / LdTy.getSizeInBits();
2474 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2477 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2479 for (unsigned i = Start + 1; i != End; ++i) {
2480 EVT NewLdTy = LdOps[i].getValueType();
2481 if (NewLdTy != LdTy) {
2482 NumElts = Width / NewLdTy.getSizeInBits();
2483 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2484 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2485 // Readjust position and vector position based on new load type
2486 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2489 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2490 DAG.getIntPtrConstant(Idx++));
2492 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2495 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,
2497 // The strategy assumes that we can efficiently load powers of two widths.
2498 // The routines chops the vector into the largest vector loads with the same
2499 // element type or scalar loads and then recombines it to the widen vector
2501 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2502 unsigned WidenWidth = WidenVT.getSizeInBits();
2503 EVT LdVT = LD->getMemoryVT();
2504 DebugLoc dl = LD->getDebugLoc();
2505 assert(LdVT.isVector() && WidenVT.isVector());
2506 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2509 SDValue Chain = LD->getChain();
2510 SDValue BasePtr = LD->getBasePtr();
2511 unsigned Align = LD->getAlignment();
2512 bool isVolatile = LD->isVolatile();
2513 bool isNonTemporal = LD->isNonTemporal();
2514 bool isInvariant = LD->isInvariant();
2516 int LdWidth = LdVT.getSizeInBits();
2517 int WidthDiff = WidenWidth - LdWidth; // Difference
2518 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
2520 // Find the vector type that can load from.
2521 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2522 int NewVTWidth = NewVT.getSizeInBits();
2523 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
2524 isVolatile, isNonTemporal, isInvariant, Align);
2525 LdChain.push_back(LdOp.getValue(1));
2527 // Check if we can load the element with one instruction
2528 if (LdWidth <= NewVTWidth) {
2529 if (!NewVT.isVector()) {
2530 unsigned NumElts = WidenWidth / NewVTWidth;
2531 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2532 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2533 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2535 if (NewVT == WidenVT)
2538 assert(WidenWidth % NewVTWidth == 0);
2539 unsigned NumConcat = WidenWidth / NewVTWidth;
2540 SmallVector<SDValue, 16> ConcatOps(NumConcat);
2541 SDValue UndefVal = DAG.getUNDEF(NewVT);
2542 ConcatOps[0] = LdOp;
2543 for (unsigned i = 1; i != NumConcat; ++i)
2544 ConcatOps[i] = UndefVal;
2545 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
2549 // Load vector by using multiple loads from largest vector to scalar
2550 SmallVector<SDValue, 16> LdOps;
2551 LdOps.push_back(LdOp);
2553 LdWidth -= NewVTWidth;
2554 unsigned Offset = 0;
2556 while (LdWidth > 0) {
2557 unsigned Increment = NewVTWidth / 8;
2558 Offset += Increment;
2559 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2560 DAG.getIntPtrConstant(Increment));
2563 if (LdWidth < NewVTWidth) {
2564 // Our current type we are using is too large, find a better size
2565 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2566 NewVTWidth = NewVT.getSizeInBits();
2567 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2568 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
2569 isNonTemporal, isInvariant, MinAlign(Align, Increment));
2570 LdChain.push_back(L.getValue(1));
2571 if (L->getValueType(0).isVector()) {
2572 SmallVector<SDValue, 16> Loads;
2574 unsigned size = L->getValueSizeInBits(0);
2575 while (size < LdOp->getValueSizeInBits(0)) {
2576 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
2577 size += L->getValueSizeInBits(0);
2579 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0),
2580 &Loads[0], Loads.size());
2583 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2584 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
2585 isNonTemporal, isInvariant, MinAlign(Align, Increment));
2586 LdChain.push_back(L.getValue(1));
2592 LdWidth -= NewVTWidth;
2595 // Build the vector from the loads operations
2596 unsigned End = LdOps.size();
2597 if (!LdOps[0].getValueType().isVector())
2598 // All the loads are scalar loads.
2599 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
2601 // If the load contains vectors, build the vector using concat vector.
2602 // All of the vectors used to loads are power of 2 and the scalars load
2603 // can be combined to make a power of 2 vector.
2604 SmallVector<SDValue, 16> ConcatOps(End);
2607 EVT LdTy = LdOps[i].getValueType();
2608 // First combine the scalar loads to a vector
2609 if (!LdTy.isVector()) {
2610 for (--i; i >= 0; --i) {
2611 LdTy = LdOps[i].getValueType();
2612 if (LdTy.isVector())
2615 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
2617 ConcatOps[--Idx] = LdOps[i];
2618 for (--i; i >= 0; --i) {
2619 EVT NewLdTy = LdOps[i].getValueType();
2620 if (NewLdTy != LdTy) {
2621 // Create a larger vector
2622 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2623 &ConcatOps[Idx], End - Idx);
2627 ConcatOps[--Idx] = LdOps[i];
2630 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
2631 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2632 &ConcatOps[Idx], End - Idx);
2634 // We need to fill the rest with undefs to build the vector
2635 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
2636 SmallVector<SDValue, 16> WidenOps(NumOps);
2637 SDValue UndefVal = DAG.getUNDEF(LdTy);
2640 for (; i != End-Idx; ++i)
2641 WidenOps[i] = ConcatOps[Idx+i];
2642 for (; i != NumOps; ++i)
2643 WidenOps[i] = UndefVal;
2645 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
2649 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,
2651 ISD::LoadExtType ExtType) {
2652 // For extension loads, it may not be more efficient to chop up the vector
2653 // and then extended it. Instead, we unroll the load and build a new vector.
2654 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2655 EVT LdVT = LD->getMemoryVT();
2656 DebugLoc dl = LD->getDebugLoc();
2657 assert(LdVT.isVector() && WidenVT.isVector());
2660 SDValue Chain = LD->getChain();
2661 SDValue BasePtr = LD->getBasePtr();
2662 unsigned Align = LD->getAlignment();
2663 bool isVolatile = LD->isVolatile();
2664 bool isNonTemporal = LD->isNonTemporal();
2666 EVT EltVT = WidenVT.getVectorElementType();
2667 EVT LdEltVT = LdVT.getVectorElementType();
2668 unsigned NumElts = LdVT.getVectorNumElements();
2670 // Load each element and widen
2671 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2672 SmallVector<SDValue, 16> Ops(WidenNumElts);
2673 unsigned Increment = LdEltVT.getSizeInBits() / 8;
2674 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
2675 LD->getPointerInfo(),
2676 LdEltVT, isVolatile, isNonTemporal, Align);
2677 LdChain.push_back(Ops[0].getValue(1));
2678 unsigned i = 0, Offset = Increment;
2679 for (i=1; i < NumElts; ++i, Offset += Increment) {
2680 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2681 BasePtr, DAG.getIntPtrConstant(Offset));
2682 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
2683 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
2684 isVolatile, isNonTemporal, Align);
2685 LdChain.push_back(Ops[i].getValue(1));
2688 // Fill the rest with undefs
2689 SDValue UndefVal = DAG.getUNDEF(EltVT);
2690 for (; i != WidenNumElts; ++i)
2693 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
2697 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2699 // The strategy assumes that we can efficiently store powers of two widths.
2700 // The routines chops the vector into the largest vector stores with the same
2701 // element type or scalar stores.
2702 SDValue Chain = ST->getChain();
2703 SDValue BasePtr = ST->getBasePtr();
2704 unsigned Align = ST->getAlignment();
2705 bool isVolatile = ST->isVolatile();
2706 bool isNonTemporal = ST->isNonTemporal();
2707 SDValue ValOp = GetWidenedVector(ST->getValue());
2708 DebugLoc dl = ST->getDebugLoc();
2710 EVT StVT = ST->getMemoryVT();
2711 unsigned StWidth = StVT.getSizeInBits();
2712 EVT ValVT = ValOp.getValueType();
2713 unsigned ValWidth = ValVT.getSizeInBits();
2714 EVT ValEltVT = ValVT.getVectorElementType();
2715 unsigned ValEltWidth = ValEltVT.getSizeInBits();
2716 assert(StVT.getVectorElementType() == ValEltVT);
2718 int Idx = 0; // current index to store
2719 unsigned Offset = 0; // offset from base to store
2720 while (StWidth != 0) {
2721 // Find the largest vector type we can store with
2722 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
2723 unsigned NewVTWidth = NewVT.getSizeInBits();
2724 unsigned Increment = NewVTWidth / 8;
2725 if (NewVT.isVector()) {
2726 unsigned NumVTElts = NewVT.getVectorNumElements();
2728 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2729 DAG.getIntPtrConstant(Idx));
2730 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2731 ST->getPointerInfo().getWithOffset(Offset),
2732 isVolatile, isNonTemporal,
2733 MinAlign(Align, Offset)));
2734 StWidth -= NewVTWidth;
2735 Offset += Increment;
2737 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2738 DAG.getIntPtrConstant(Increment));
2739 } while (StWidth != 0 && StWidth >= NewVTWidth);
2741 // Cast the vector to the scalar type we can store
2742 unsigned NumElts = ValWidth / NewVTWidth;
2743 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2744 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
2745 // Readjust index position based on new vector type
2746 Idx = Idx * ValEltWidth / NewVTWidth;
2748 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2749 DAG.getIntPtrConstant(Idx++));
2750 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2751 ST->getPointerInfo().getWithOffset(Offset),
2752 isVolatile, isNonTemporal,
2753 MinAlign(Align, Offset)));
2754 StWidth -= NewVTWidth;
2755 Offset += Increment;
2756 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2757 DAG.getIntPtrConstant(Increment));
2758 } while (StWidth != 0 && StWidth >= NewVTWidth);
2759 // Restore index back to be relative to the original widen element type
2760 Idx = Idx * NewVTWidth / ValEltWidth;
2766 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,
2768 // For extension loads, it may not be more efficient to truncate the vector
2769 // and then store it. Instead, we extract each element and then store it.
2770 SDValue Chain = ST->getChain();
2771 SDValue BasePtr = ST->getBasePtr();
2772 unsigned Align = ST->getAlignment();
2773 bool isVolatile = ST->isVolatile();
2774 bool isNonTemporal = ST->isNonTemporal();
2775 SDValue ValOp = GetWidenedVector(ST->getValue());
2776 DebugLoc dl = ST->getDebugLoc();
2778 EVT StVT = ST->getMemoryVT();
2779 EVT ValVT = ValOp.getValueType();
2781 // It must be true that we the widen vector type is bigger than where
2782 // we need to store.
2783 assert(StVT.isVector() && ValOp.getValueType().isVector());
2784 assert(StVT.bitsLT(ValOp.getValueType()));
2786 // For truncating stores, we can not play the tricks of chopping legal
2787 // vector types and bit cast it to the right type. Instead, we unroll
2789 EVT StEltVT = StVT.getVectorElementType();
2790 EVT ValEltVT = ValVT.getVectorElementType();
2791 unsigned Increment = ValEltVT.getSizeInBits() / 8;
2792 unsigned NumElts = StVT.getVectorNumElements();
2793 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2794 DAG.getIntPtrConstant(0));
2795 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
2796 ST->getPointerInfo(), StEltVT,
2797 isVolatile, isNonTemporal, Align));
2798 unsigned Offset = Increment;
2799 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
2800 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2801 BasePtr, DAG.getIntPtrConstant(Offset));
2802 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2803 DAG.getIntPtrConstant(0));
2804 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
2805 ST->getPointerInfo().getWithOffset(Offset),
2806 StEltVT, isVolatile, isNonTemporal,
2807 MinAlign(Align, Offset)));
2811 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2812 /// input vector must have the same element type as NVT.
2813 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
2814 // Note that InOp might have been widened so it might already have
2815 // the right width or it might need be narrowed.
2816 EVT InVT = InOp.getValueType();
2817 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2818 "input and widen element type must match");
2819 DebugLoc dl = InOp.getDebugLoc();
2821 // Check if InOp already has the right width.
2825 unsigned InNumElts = InVT.getVectorNumElements();
2826 unsigned WidenNumElts = NVT.getVectorNumElements();
2827 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2828 unsigned NumConcat = WidenNumElts / InNumElts;
2829 SmallVector<SDValue, 16> Ops(NumConcat);
2830 SDValue UndefVal = DAG.getUNDEF(InVT);
2832 for (unsigned i = 1; i != NumConcat; ++i)
2835 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2838 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2839 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2840 DAG.getIntPtrConstant(0));
2842 // Fall back to extract and build.
2843 SmallVector<SDValue, 16> Ops(WidenNumElts);
2844 EVT EltVT = NVT.getVectorElementType();
2845 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2847 for (Idx = 0; Idx < MinNumElts; ++Idx)
2848 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2849 DAG.getIntPtrConstant(Idx));
2851 SDValue UndefVal = DAG.getUNDEF(EltVT);
2852 for ( ; Idx < WidenNumElts; ++Idx)
2853 Ops[Idx] = UndefVal;
2854 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);