1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
30 //===----------------------------------------------------------------------===//
31 // Result Vector Scalarization: <1 x ty> -> ty.
32 //===----------------------------------------------------------------------===//
34 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
38 SDValue R = SDValue();
40 switch (N->getOpcode()) {
43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
47 llvm_unreachable("Do not know how to scalarize the result of this operator!");
49 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
50 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
51 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
52 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
53 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
54 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
55 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
56 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
57 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
58 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
59 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
60 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
61 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
62 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
63 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
64 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
84 case ISD::SIGN_EXTEND:
85 case ISD::ZERO_EXTEND:
87 R = ScalarizeVecRes_UnaryOp(N);
109 R = ScalarizeVecRes_BinOp(N);
113 // If R is null, the sub-method took care of registering the result.
115 SetScalarizedVector(SDValue(N, ResNo), R);
118 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
119 SDValue LHS = GetScalarizedVector(N->getOperand(0));
120 SDValue RHS = GetScalarizedVector(N->getOperand(1));
121 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
122 LHS.getValueType(), LHS, RHS);
125 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
126 EVT NewVT = N->getValueType(0).getVectorElementType();
127 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
128 NewVT, N->getOperand(0));
131 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
132 EVT NewVT = N->getValueType(0).getVectorElementType();
133 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
134 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
135 Op0, DAG.getValueType(NewVT),
136 DAG.getValueType(Op0.getValueType()),
139 cast<CvtRndSatSDNode>(N)->getCvtCode());
142 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
143 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
144 N->getValueType(0).getVectorElementType(),
145 N->getOperand(0), N->getOperand(1));
148 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
149 SDValue Op = GetScalarizedVector(N->getOperand(0));
150 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
151 Op.getValueType(), Op, N->getOperand(1));
154 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
155 // The value to insert may have a wider type than the vector element type,
156 // so be sure to truncate it to the element type if necessary.
157 SDValue Op = N->getOperand(1);
158 EVT EltVT = N->getValueType(0).getVectorElementType();
159 if (Op.getValueType() != EltVT)
160 // FIXME: Can this happen for floating point types?
161 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
166 assert(N->isUnindexed() && "Indexed vector load?");
168 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getDebugLoc(),
169 N->getExtensionType(),
170 N->getValueType(0).getVectorElementType(),
171 N->getChain(), N->getBasePtr(),
172 DAG.getUNDEF(N->getBasePtr().getValueType()),
173 N->getSrcValue(), N->getSrcValueOffset(),
174 N->getMemoryVT().getVectorElementType(),
175 N->isVolatile(), N->getOriginalAlignment());
177 // Legalized the chain result - switch anything that used the old chain to
179 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
183 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
184 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
185 EVT DestVT = N->getValueType(0).getVectorElementType();
186 SDValue Op = GetScalarizedVector(N->getOperand(0));
187 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
190 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
191 EVT EltVT = N->getValueType(0).getVectorElementType();
192 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
193 SDValue LHS = GetScalarizedVector(N->getOperand(0));
194 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT,
195 LHS, DAG.getValueType(ExtVT));
198 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
199 // If the operand is wider than the vector element type then it is implicitly
200 // truncated. Make that explicit here.
201 EVT EltVT = N->getValueType(0).getVectorElementType();
202 SDValue InOp = N->getOperand(0);
203 if (InOp.getValueType() != EltVT)
204 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
208 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
209 SDValue LHS = GetScalarizedVector(N->getOperand(1));
210 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
211 LHS.getValueType(), N->getOperand(0), LHS,
212 GetScalarizedVector(N->getOperand(2)));
215 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
216 SDValue LHS = GetScalarizedVector(N->getOperand(2));
217 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
218 N->getOperand(0), N->getOperand(1),
219 LHS, GetScalarizedVector(N->getOperand(3)),
223 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
224 SDValue LHS = GetScalarizedVector(N->getOperand(0));
225 SDValue RHS = GetScalarizedVector(N->getOperand(1));
226 DebugLoc DL = N->getDebugLoc();
228 // Turn it into a scalar SETCC.
229 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
232 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
233 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
236 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
237 // Figure out if the scalar is the LHS or RHS and return it.
238 SDValue Arg = N->getOperand(2).getOperand(0);
239 if (Arg.getOpcode() == ISD::UNDEF)
240 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
241 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
242 return GetScalarizedVector(N->getOperand(Op));
245 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
246 SDValue LHS = GetScalarizedVector(N->getOperand(0));
247 SDValue RHS = GetScalarizedVector(N->getOperand(1));
248 EVT NVT = N->getValueType(0).getVectorElementType();
249 EVT SVT = TLI.getSetCCResultType(LHS.getValueType());
250 DebugLoc DL = N->getDebugLoc();
252 // Turn it into a scalar SETCC.
253 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2));
255 // VSETCC always returns a sign-extended value, while SETCC may not. The
256 // SETCC result type may not match the vector element type. Correct these.
257 if (NVT.bitsLE(SVT)) {
258 // The SETCC result type is bigger than the vector element type.
259 // Ensure the SETCC result is sign-extended.
260 if (TLI.getBooleanContents() !=
261 TargetLowering::ZeroOrNegativeOneBooleanContent)
262 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
263 DAG.getValueType(MVT::i1));
264 // Truncate to the final type.
265 return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
268 // The SETCC result type is smaller than the vector element type.
269 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
270 if (TLI.getBooleanContents() !=
271 TargetLowering::ZeroOrNegativeOneBooleanContent)
272 Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
273 // Sign extend to the final type.
274 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
278 //===----------------------------------------------------------------------===//
279 // Operand Vector Scalarization <1 x ty> -> ty.
280 //===----------------------------------------------------------------------===//
282 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
283 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
286 SDValue Res = SDValue();
288 if (Res.getNode() == 0) {
289 switch (N->getOpcode()) {
292 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
296 llvm_unreachable("Do not know how to scalarize this operator's operand!");
297 case ISD::BIT_CONVERT:
298 Res = ScalarizeVecOp_BIT_CONVERT(N);
300 case ISD::CONCAT_VECTORS:
301 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
303 case ISD::EXTRACT_VECTOR_ELT:
304 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
307 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
312 // If the result is null, the sub-method took care of registering results etc.
313 if (!Res.getNode()) return false;
315 // If the result is N, the sub-method updated N in place. Tell the legalizer
317 if (Res.getNode() == N)
320 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
321 "Invalid operand expansion");
323 ReplaceValueWith(SDValue(N, 0), Res);
327 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
328 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
329 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
330 SDValue Elt = GetScalarizedVector(N->getOperand(0));
331 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
332 N->getValueType(0), Elt);
335 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
336 /// use a BUILD_VECTOR instead.
337 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
338 SmallVector<SDValue, 8> Ops(N->getNumOperands());
339 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
340 Ops[i] = GetScalarizedVector(N->getOperand(i));
341 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
342 &Ops[0], Ops.size());
345 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
346 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
348 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
349 SDValue Res = GetScalarizedVector(N->getOperand(0));
350 if (Res.getValueType() != N->getValueType(0))
351 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
356 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
357 /// scalarized, it must be <1 x ty>. Just store the element.
358 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
359 assert(N->isUnindexed() && "Indexed store of one-element vector?");
360 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
361 DebugLoc dl = N->getDebugLoc();
363 if (N->isTruncatingStore())
364 return DAG.getTruncStore(N->getChain(), dl,
365 GetScalarizedVector(N->getOperand(1)),
367 N->getSrcValue(), N->getSrcValueOffset(),
368 N->getMemoryVT().getVectorElementType(),
369 N->isVolatile(), N->getAlignment());
371 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
372 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
373 N->isVolatile(), N->getOriginalAlignment());
377 //===----------------------------------------------------------------------===//
378 // Result Vector Splitting
379 //===----------------------------------------------------------------------===//
381 /// SplitVectorResult - This method is called when the specified result of the
382 /// specified node is found to need vector splitting. At this point, the node
383 /// may also have invalid operands or may have other results that need
384 /// legalization, we just know that (at least) one result needs vector
386 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
387 DEBUG(dbgs() << "Split node result: ";
392 switch (N->getOpcode()) {
395 dbgs() << "SplitVectorResult #" << ResNo << ": ";
399 llvm_unreachable("Do not know how to split the result of this operator!");
401 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
402 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
403 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
404 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
406 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
407 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
408 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
409 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
410 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
411 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
412 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
413 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
414 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
415 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
417 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
421 SplitVecRes_SETCC(N, Lo, Hi);
423 case ISD::VECTOR_SHUFFLE:
424 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
439 case ISD::FNEARBYINT:
440 case ISD::FP_TO_SINT:
441 case ISD::FP_TO_UINT:
442 case ISD::SINT_TO_FP:
443 case ISD::UINT_TO_FP:
445 case ISD::SIGN_EXTEND:
446 case ISD::ZERO_EXTEND:
447 case ISD::ANY_EXTEND:
448 SplitVecRes_UnaryOp(N, Lo, Hi);
470 SplitVecRes_BinOp(N, Lo, Hi);
474 // If Lo/Hi is null, the sub-method took care of registering results etc.
476 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
479 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
481 SDValue LHSLo, LHSHi;
482 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
483 SDValue RHSLo, RHSHi;
484 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
485 DebugLoc dl = N->getDebugLoc();
487 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
488 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
491 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
493 // We know the result is a vector. The input may be either a vector or a
496 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
497 DebugLoc dl = N->getDebugLoc();
499 SDValue InOp = N->getOperand(0);
500 EVT InVT = InOp.getValueType();
502 // Handle some special cases efficiently.
503 switch (getTypeAction(InVT)) {
505 assert(false && "Unknown type action!");
509 case ScalarizeVector:
513 // A scalar to vector conversion, where the scalar needs expansion.
514 // If the vector is being split in two then we can just convert the
517 GetExpandedOp(InOp, Lo, Hi);
518 if (TLI.isBigEndian())
520 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
521 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
526 // If the input is a vector that needs to be split, convert each split
527 // piece of the input now.
528 GetSplitVector(InOp, Lo, Hi);
529 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
530 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
534 // In the general case, convert the input to an integer and split it by hand.
535 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
536 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
537 if (TLI.isBigEndian())
538 std::swap(LoIntVT, HiIntVT);
540 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
542 if (TLI.isBigEndian())
544 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
545 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
548 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
551 DebugLoc dl = N->getDebugLoc();
552 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
553 unsigned LoNumElts = LoVT.getVectorNumElements();
554 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
555 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
557 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
558 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
561 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
563 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
564 DebugLoc dl = N->getDebugLoc();
565 unsigned NumSubvectors = N->getNumOperands() / 2;
566 if (NumSubvectors == 1) {
567 Lo = N->getOperand(0);
568 Hi = N->getOperand(1);
573 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
575 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
576 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
578 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
579 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
582 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
585 DebugLoc dl = N->getDebugLoc();
586 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
588 SDValue DTyOpLo = DAG.getValueType(LoVT);
589 SDValue DTyOpHi = DAG.getValueType(HiVT);
591 SDValue RndOp = N->getOperand(3);
592 SDValue SatOp = N->getOperand(4);
593 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
597 EVT InVT = N->getOperand(0).getValueType();
598 switch (getTypeAction(InVT)) {
599 default: llvm_unreachable("Unexpected type action!");
601 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
602 LoVT.getVectorNumElements());
603 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
604 DAG.getIntPtrConstant(0));
605 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
606 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
610 GetSplitVector(N->getOperand(0), VLo, VHi);
613 // If the result needs to be split and the input needs to be widened,
614 // the two types must have different lengths. Use the widened result
615 // and extract from it to do the split.
616 SDValue InOp = GetWidenedVector(N->getOperand(0));
617 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
618 LoVT.getVectorNumElements());
619 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
620 DAG.getIntPtrConstant(0));
621 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
622 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
627 SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
628 SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
630 Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
632 Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp,
636 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
638 SDValue Vec = N->getOperand(0);
639 SDValue Idx = N->getOperand(1);
640 EVT IdxVT = Idx.getValueType();
641 DebugLoc dl = N->getDebugLoc();
644 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
646 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
647 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
648 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
649 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, Idx);
652 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
654 DebugLoc dl = N->getDebugLoc();
655 GetSplitVector(N->getOperand(0), Lo, Hi);
656 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
657 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
660 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
662 SDValue LHSLo, LHSHi;
663 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
664 DebugLoc dl = N->getDebugLoc();
667 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT);
669 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
670 DAG.getValueType(LoVT));
671 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
672 DAG.getValueType(HiVT));
675 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
677 SDValue Vec = N->getOperand(0);
678 SDValue Elt = N->getOperand(1);
679 SDValue Idx = N->getOperand(2);
680 DebugLoc dl = N->getDebugLoc();
681 GetSplitVector(Vec, Lo, Hi);
683 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
684 unsigned IdxVal = CIdx->getZExtValue();
685 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
686 if (IdxVal < LoNumElts)
687 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
688 Lo.getValueType(), Lo, Elt, Idx);
690 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
691 DAG.getIntPtrConstant(IdxVal - LoNumElts));
695 // Spill the vector to the stack.
696 EVT VecVT = Vec.getValueType();
697 EVT EltVT = VecVT.getVectorElementType();
698 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
699 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
701 // Store the new element. This may be larger than the vector element type,
702 // so use a truncating store.
703 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
705 TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForEVT(*DAG.getContext()));
706 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT);
708 // Load the Lo part from the stack slot.
709 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, NULL, 0);
711 // Increment the pointer to the other part.
712 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
713 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
714 DAG.getIntPtrConstant(IncrementSize));
716 // Load the Hi part from the stack slot.
717 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, NULL, 0, false,
718 MinAlign(Alignment, IncrementSize));
721 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
724 DebugLoc dl = N->getDebugLoc();
725 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
726 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
727 Hi = DAG.getUNDEF(HiVT);
730 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
732 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
734 DebugLoc dl = LD->getDebugLoc();
735 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
737 ISD::LoadExtType ExtType = LD->getExtensionType();
738 SDValue Ch = LD->getChain();
739 SDValue Ptr = LD->getBasePtr();
740 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
741 const Value *SV = LD->getSrcValue();
742 int SVOffset = LD->getSrcValueOffset();
743 EVT MemoryVT = LD->getMemoryVT();
744 unsigned Alignment = LD->getOriginalAlignment();
745 bool isVolatile = LD->isVolatile();
747 EVT LoMemVT, HiMemVT;
748 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
750 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, LoVT, Ch, Ptr, Offset,
751 SV, SVOffset, LoMemVT, isVolatile, Alignment);
753 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
754 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
755 DAG.getIntPtrConstant(IncrementSize));
756 SVOffset += IncrementSize;
757 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, HiVT, Ch, Ptr, Offset,
758 SV, SVOffset, HiMemVT, isVolatile, Alignment);
760 // Build a factor node to remember that this load is independent of the
762 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
765 // Legalized the chain result - switch anything that used the old chain to
767 ReplaceValueWith(SDValue(LD, 1), Ch);
770 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
772 DebugLoc DL = N->getDebugLoc();
773 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
776 EVT InVT = N->getOperand(0).getValueType();
777 SDValue LL, LH, RL, RH;
778 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
779 LoVT.getVectorNumElements());
780 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
781 DAG.getIntPtrConstant(0));
782 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
783 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
785 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
786 DAG.getIntPtrConstant(0));
787 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
788 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
790 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
791 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
794 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
796 // Get the dest types - they may not match the input types, e.g. int_to_fp.
798 DebugLoc dl = N->getDebugLoc();
799 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
802 EVT InVT = N->getOperand(0).getValueType();
803 switch (getTypeAction(InVT)) {
804 default: llvm_unreachable("Unexpected type action!");
806 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
807 LoVT.getVectorNumElements());
808 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
809 DAG.getIntPtrConstant(0));
810 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
811 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
815 GetSplitVector(N->getOperand(0), Lo, Hi);
818 // If the result needs to be split and the input needs to be widened,
819 // the two types must have different lengths. Use the widened result
820 // and extract from it to do the split.
821 SDValue InOp = GetWidenedVector(N->getOperand(0));
822 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
823 LoVT.getVectorNumElements());
824 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
825 DAG.getIntPtrConstant(0));
826 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
827 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
832 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
833 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
836 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
837 SDValue &Lo, SDValue &Hi) {
838 // The low and high parts of the original input give four input vectors.
840 DebugLoc dl = N->getDebugLoc();
841 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
842 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
843 EVT NewVT = Inputs[0].getValueType();
844 unsigned NewElts = NewVT.getVectorNumElements();
846 // If Lo or Hi uses elements from at most two of the four input vectors, then
847 // express it as a vector shuffle of those two inputs. Otherwise extract the
848 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
849 SmallVector<int, 16> Ops;
850 for (unsigned High = 0; High < 2; ++High) {
851 SDValue &Output = High ? Hi : Lo;
853 // Build a shuffle mask for the output, discovering on the fly which
854 // input vectors to use as shuffle operands (recorded in InputUsed).
855 // If building a suitable shuffle vector proves too hard, then bail
856 // out with useBuildVector set.
857 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
858 unsigned FirstMaskIdx = High * NewElts;
859 bool useBuildVector = false;
860 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
861 // The mask element. This indexes into the input.
862 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
864 // The input vector this mask element indexes into.
865 unsigned Input = (unsigned)Idx / NewElts;
867 if (Input >= array_lengthof(Inputs)) {
868 // The mask element does not index into any input vector.
873 // Turn the index into an offset from the start of the input vector.
874 Idx -= Input * NewElts;
876 // Find or create a shuffle vector operand to hold this input.
878 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
879 if (InputUsed[OpNo] == Input) {
880 // This input vector is already an operand.
882 } else if (InputUsed[OpNo] == -1U) {
883 // Create a new operand for this input vector.
884 InputUsed[OpNo] = Input;
889 if (OpNo >= array_lengthof(InputUsed)) {
890 // More than two input vectors used! Give up on trying to create a
891 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
892 useBuildVector = true;
896 // Add the mask index for the new shuffle vector.
897 Ops.push_back(Idx + OpNo * NewElts);
900 if (useBuildVector) {
901 EVT EltVT = NewVT.getVectorElementType();
902 SmallVector<SDValue, 16> SVOps;
904 // Extract the input elements by hand.
905 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
906 // The mask element. This indexes into the input.
907 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
909 // The input vector this mask element indexes into.
910 unsigned Input = (unsigned)Idx / NewElts;
912 if (Input >= array_lengthof(Inputs)) {
913 // The mask element is "undef" or indexes off the end of the input.
914 SVOps.push_back(DAG.getUNDEF(EltVT));
918 // Turn the index into an offset from the start of the input vector.
919 Idx -= Input * NewElts;
921 // Extract the vector element by hand.
922 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
923 Inputs[Input], DAG.getIntPtrConstant(Idx)));
926 // Construct the Lo/Hi output using a BUILD_VECTOR.
927 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
928 } else if (InputUsed[0] == -1U) {
929 // No input vectors were used! The result is undefined.
930 Output = DAG.getUNDEF(NewVT);
932 SDValue Op0 = Inputs[InputUsed[0]];
933 // If only one input was used, use an undefined vector for the other.
934 SDValue Op1 = InputUsed[1] == -1U ?
935 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
936 // At least one input vector was used. Create a new shuffle vector.
937 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
945 //===----------------------------------------------------------------------===//
946 // Operand Vector Splitting
947 //===----------------------------------------------------------------------===//
949 /// SplitVectorOperand - This method is called when the specified operand of the
950 /// specified node is found to need vector splitting. At this point, all of the
951 /// result types of the node are known to be legal, but other operands of the
952 /// node may need legalization as well as the specified one.
953 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
954 DEBUG(dbgs() << "Split node operand: ";
957 SDValue Res = SDValue();
959 if (Res.getNode() == 0) {
960 switch (N->getOpcode()) {
963 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
967 llvm_unreachable("Do not know how to split this operator's operand!");
969 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
970 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
971 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
973 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
979 case ISD::FP_TO_SINT:
980 case ISD::FP_TO_UINT:
981 case ISD::SINT_TO_FP:
982 case ISD::UINT_TO_FP:
984 case ISD::SIGN_EXTEND:
985 case ISD::ZERO_EXTEND:
986 case ISD::ANY_EXTEND:
987 Res = SplitVecOp_UnaryOp(N);
992 // If the result is null, the sub-method took care of registering results etc.
993 if (!Res.getNode()) return false;
995 // If the result is N, the sub-method updated N in place. Tell the legalizer
997 if (Res.getNode() == N)
1000 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1001 "Invalid operand expansion");
1003 ReplaceValueWith(SDValue(N, 0), Res);
1007 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1008 // The result has a legal vector type, but the input needs splitting.
1009 EVT ResVT = N->getValueType(0);
1011 DebugLoc dl = N->getDebugLoc();
1012 GetSplitVector(N->getOperand(0), Lo, Hi);
1013 EVT InVT = Lo.getValueType();
1015 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1016 InVT.getVectorNumElements());
1018 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1019 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1021 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1024 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
1025 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
1026 // end up being split all the way down to individual components. Convert the
1027 // split pieces into integers and reassemble.
1029 GetSplitVector(N->getOperand(0), Lo, Hi);
1030 Lo = BitConvertToInteger(Lo);
1031 Hi = BitConvertToInteger(Hi);
1033 if (TLI.isBigEndian())
1036 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), N->getValueType(0),
1037 JoinIntegers(Lo, Hi));
1040 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1041 // We know that the extracted result type is legal. For now, assume the index
1043 EVT SubVT = N->getValueType(0);
1044 SDValue Idx = N->getOperand(1);
1045 DebugLoc dl = N->getDebugLoc();
1047 GetSplitVector(N->getOperand(0), Lo, Hi);
1049 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1050 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1052 if (IdxVal < LoElts) {
1053 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1054 "Extracted subvector crosses vector split!");
1055 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1057 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1058 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1062 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1063 SDValue Vec = N->getOperand(0);
1064 SDValue Idx = N->getOperand(1);
1065 EVT VecVT = Vec.getValueType();
1067 if (isa<ConstantSDNode>(Idx)) {
1068 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1069 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1072 GetSplitVector(Vec, Lo, Hi);
1074 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1076 if (IdxVal < LoElts)
1077 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
1078 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
1079 DAG.getConstant(IdxVal - LoElts,
1080 Idx.getValueType()));
1083 // Store the vector to the stack.
1084 EVT EltVT = VecVT.getVectorElementType();
1085 DebugLoc dl = N->getDebugLoc();
1086 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1087 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1088 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1089 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, SV, 0);
1091 // Load back the required element.
1092 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1093 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1097 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1098 assert(N->isUnindexed() && "Indexed store of vector?");
1099 assert(OpNo == 1 && "Can only split the stored value");
1100 DebugLoc dl = N->getDebugLoc();
1102 bool isTruncating = N->isTruncatingStore();
1103 SDValue Ch = N->getChain();
1104 SDValue Ptr = N->getBasePtr();
1105 int SVOffset = N->getSrcValueOffset();
1106 EVT MemoryVT = N->getMemoryVT();
1107 unsigned Alignment = N->getOriginalAlignment();
1108 bool isVol = N->isVolatile();
1110 GetSplitVector(N->getOperand(1), Lo, Hi);
1112 EVT LoMemVT, HiMemVT;
1113 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1115 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1118 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
1119 LoMemVT, isVol, Alignment);
1121 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
1124 // Increment the pointer to the other half.
1125 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1126 DAG.getIntPtrConstant(IncrementSize));
1127 SVOffset += IncrementSize;
1130 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset,
1131 HiMemVT, isVol, Alignment);
1133 Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset,
1136 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1140 //===----------------------------------------------------------------------===//
1141 // Result Vector Widening
1142 //===----------------------------------------------------------------------===//
1144 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1145 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1149 // See if the target wants to custom widen this node.
1150 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1153 SDValue Res = SDValue();
1154 switch (N->getOpcode()) {
1157 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1161 llvm_unreachable("Do not know how to widen the result of this operator!");
1163 case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break;
1164 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1165 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1166 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1167 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1168 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1169 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1170 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1171 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1172 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1173 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1174 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1175 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1176 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1177 case ISD::VECTOR_SHUFFLE:
1178 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1181 Res = WidenVecRes_VSETCC(N);
1188 case ISD::FCOPYSIGN:
1205 Res = WidenVecRes_Binary(N);
1211 Res = WidenVecRes_Shift(N);
1215 case ISD::FP_TO_SINT:
1216 case ISD::FP_TO_UINT:
1217 case ISD::SINT_TO_FP:
1218 case ISD::UINT_TO_FP:
1220 case ISD::SIGN_EXTEND:
1221 case ISD::ZERO_EXTEND:
1222 case ISD::ANY_EXTEND:
1223 Res = WidenVecRes_Convert(N);
1234 Res = WidenVecRes_Unary(N);
1238 // If Res is null, the sub-method took care of registering the result.
1240 SetWidenedVector(SDValue(N, ResNo), Res);
1243 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1244 // Binary op widening.
1245 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1246 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1247 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1248 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp1, InOp2);
1251 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1252 SDValue InOp = N->getOperand(0);
1253 DebugLoc dl = N->getDebugLoc();
1255 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1256 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1258 EVT InVT = InOp.getValueType();
1259 EVT InEltVT = InVT.getVectorElementType();
1260 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1262 unsigned Opcode = N->getOpcode();
1263 unsigned InVTNumElts = InVT.getVectorNumElements();
1265 if (getTypeAction(InVT) == WidenVector) {
1266 InOp = GetWidenedVector(N->getOperand(0));
1267 InVT = InOp.getValueType();
1268 InVTNumElts = InVT.getVectorNumElements();
1269 if (InVTNumElts == WidenNumElts)
1270 return DAG.getNode(Opcode, dl, WidenVT, InOp);
1273 if (TLI.isTypeLegal(InWidenVT)) {
1274 // Because the result and the input are different vector types, widening
1275 // the result could create a legal type but widening the input might make
1276 // it an illegal type that might lead to repeatedly splitting the input
1277 // and then widening it. To avoid this, we widen the input only if
1278 // it results in a legal type.
1279 if (WidenNumElts % InVTNumElts == 0) {
1280 // Widen the input and call convert on the widened input vector.
1281 unsigned NumConcat = WidenNumElts/InVTNumElts;
1282 SmallVector<SDValue, 16> Ops(NumConcat);
1284 SDValue UndefVal = DAG.getUNDEF(InVT);
1285 for (unsigned i = 1; i != NumConcat; ++i)
1287 return DAG.getNode(Opcode, dl, WidenVT,
1288 DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT,
1289 &Ops[0], NumConcat));
1292 if (InVTNumElts % WidenNumElts == 0) {
1293 // Extract the input and convert the shorten input vector.
1294 return DAG.getNode(Opcode, dl, WidenVT,
1295 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT,
1296 InOp, DAG.getIntPtrConstant(0)));
1300 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1301 SmallVector<SDValue, 16> Ops(WidenNumElts);
1302 EVT EltVT = WidenVT.getVectorElementType();
1303 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1305 for (i=0; i < MinElts; ++i)
1306 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
1307 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1308 DAG.getIntPtrConstant(i)));
1310 SDValue UndefVal = DAG.getUNDEF(EltVT);
1311 for (; i < WidenNumElts; ++i)
1314 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1317 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1318 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1319 SDValue InOp = GetWidenedVector(N->getOperand(0));
1320 SDValue ShOp = N->getOperand(1);
1322 EVT ShVT = ShOp.getValueType();
1323 if (getTypeAction(ShVT) == WidenVector) {
1324 ShOp = GetWidenedVector(ShOp);
1325 ShVT = ShOp.getValueType();
1327 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(), ShVT.getVectorElementType(),
1328 WidenVT.getVectorNumElements());
1329 if (ShVT != ShWidenVT)
1330 ShOp = ModifyToType(ShOp, ShWidenVT);
1332 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1335 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1336 // Unary op widening.
1337 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1338 SDValue InOp = GetWidenedVector(N->getOperand(0));
1339 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1342 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
1343 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1344 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
1345 cast<VTSDNode>(N->getOperand(1))->getVT()
1346 .getVectorElementType(),
1347 WidenVT.getVectorNumElements());
1348 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
1349 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
1350 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
1353 SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
1354 SDValue InOp = N->getOperand(0);
1355 EVT InVT = InOp.getValueType();
1356 EVT VT = N->getValueType(0);
1357 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1358 DebugLoc dl = N->getDebugLoc();
1360 switch (getTypeAction(InVT)) {
1362 assert(false && "Unknown type action!");
1366 case PromoteInteger:
1367 // If the InOp is promoted to the same size, convert it. Otherwise,
1368 // fall out of the switch and widen the promoted input.
1369 InOp = GetPromotedInteger(InOp);
1370 InVT = InOp.getValueType();
1371 if (WidenVT.bitsEq(InVT))
1372 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1377 case ScalarizeVector:
1381 // If the InOp is widened to the same size, convert it. Otherwise, fall
1382 // out of the switch and widen the widened input.
1383 InOp = GetWidenedVector(InOp);
1384 InVT = InOp.getValueType();
1385 if (WidenVT.bitsEq(InVT))
1386 // The input widens to the same size. Convert to the widen value.
1387 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1391 unsigned WidenSize = WidenVT.getSizeInBits();
1392 unsigned InSize = InVT.getSizeInBits();
1393 if (WidenSize % InSize == 0) {
1394 // Determine new input vector type. The new input vector type will use
1395 // the same element type (if its a vector) or use the input type as a
1396 // vector. It is the same size as the type to widen to.
1398 unsigned NewNumElts = WidenSize / InSize;
1399 if (InVT.isVector()) {
1400 EVT InEltVT = InVT.getVectorElementType();
1401 NewInVT= EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenSize / InEltVT.getSizeInBits());
1403 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
1406 if (TLI.isTypeLegal(NewInVT)) {
1407 // Because the result and the input are different vector types, widening
1408 // the result could create a legal type but widening the input might make
1409 // it an illegal type that might lead to repeatedly splitting the input
1410 // and then widening it. To avoid this, we widen the input only if
1411 // it results in a legal type.
1412 SmallVector<SDValue, 16> Ops(NewNumElts);
1413 SDValue UndefVal = DAG.getUNDEF(InVT);
1415 for (unsigned i = 1; i < NewNumElts; ++i)
1419 if (InVT.isVector())
1420 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1421 NewInVT, &Ops[0], NewNumElts);
1423 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1424 NewInVT, &Ops[0], NewNumElts);
1425 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, NewVec);
1429 return CreateStackStoreLoad(InOp, WidenVT);
1432 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1433 DebugLoc dl = N->getDebugLoc();
1434 // Build a vector with undefined for the new nodes.
1435 EVT VT = N->getValueType(0);
1436 EVT EltVT = VT.getVectorElementType();
1437 unsigned NumElts = VT.getVectorNumElements();
1439 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1440 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1442 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1443 NewOps.reserve(WidenNumElts);
1444 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1445 NewOps.push_back(DAG.getUNDEF(EltVT));
1447 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1450 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1451 EVT InVT = N->getOperand(0).getValueType();
1452 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1453 DebugLoc dl = N->getDebugLoc();
1454 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1455 unsigned NumOperands = N->getNumOperands();
1457 bool InputWidened = false; // Indicates we need to widen the input.
1458 if (getTypeAction(InVT) != WidenVector) {
1459 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1460 // Add undef vectors to widen to correct length.
1461 unsigned NumConcat = WidenVT.getVectorNumElements() /
1462 InVT.getVectorNumElements();
1463 SDValue UndefVal = DAG.getUNDEF(InVT);
1464 SmallVector<SDValue, 16> Ops(NumConcat);
1465 for (unsigned i=0; i < NumOperands; ++i)
1466 Ops[i] = N->getOperand(i);
1467 for (unsigned i = NumOperands; i != NumConcat; ++i)
1469 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1472 InputWidened = true;
1473 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
1474 // The inputs and the result are widen to the same value.
1476 for (i=1; i < NumOperands; ++i)
1477 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1480 if (i > NumOperands)
1481 // Everything but the first operand is an UNDEF so just return the
1482 // widened first operand.
1483 return GetWidenedVector(N->getOperand(0));
1485 if (NumOperands == 2) {
1486 // Replace concat of two operands with a shuffle.
1487 SmallVector<int, 16> MaskOps(WidenNumElts);
1488 for (unsigned i=0; i < WidenNumElts/2; ++i) {
1490 MaskOps[i+WidenNumElts/2] = i+WidenNumElts;
1492 return DAG.getVectorShuffle(WidenVT, dl,
1493 GetWidenedVector(N->getOperand(0)),
1494 GetWidenedVector(N->getOperand(1)),
1500 // Fall back to use extracts and build vector.
1501 EVT EltVT = WidenVT.getVectorElementType();
1502 unsigned NumInElts = InVT.getVectorNumElements();
1503 SmallVector<SDValue, 16> Ops(WidenNumElts);
1505 for (unsigned i=0; i < NumOperands; ++i) {
1506 SDValue InOp = N->getOperand(i);
1508 InOp = GetWidenedVector(InOp);
1509 for (unsigned j=0; j < NumInElts; ++j)
1510 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1511 DAG.getIntPtrConstant(j));
1513 SDValue UndefVal = DAG.getUNDEF(EltVT);
1514 for (; Idx < WidenNumElts; ++Idx)
1515 Ops[Idx] = UndefVal;
1516 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1519 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1520 DebugLoc dl = N->getDebugLoc();
1521 SDValue InOp = N->getOperand(0);
1522 SDValue RndOp = N->getOperand(3);
1523 SDValue SatOp = N->getOperand(4);
1525 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1526 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1528 EVT InVT = InOp.getValueType();
1529 EVT InEltVT = InVT.getVectorElementType();
1530 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1532 SDValue DTyOp = DAG.getValueType(WidenVT);
1533 SDValue STyOp = DAG.getValueType(InWidenVT);
1534 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1536 unsigned InVTNumElts = InVT.getVectorNumElements();
1537 if (getTypeAction(InVT) == WidenVector) {
1538 InOp = GetWidenedVector(InOp);
1539 InVT = InOp.getValueType();
1540 InVTNumElts = InVT.getVectorNumElements();
1541 if (InVTNumElts == WidenNumElts)
1542 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1546 if (TLI.isTypeLegal(InWidenVT)) {
1547 // Because the result and the input are different vector types, widening
1548 // the result could create a legal type but widening the input might make
1549 // it an illegal type that might lead to repeatedly splitting the input
1550 // and then widening it. To avoid this, we widen the input only if
1551 // it results in a legal type.
1552 if (WidenNumElts % InVTNumElts == 0) {
1553 // Widen the input and call convert on the widened input vector.
1554 unsigned NumConcat = WidenNumElts/InVTNumElts;
1555 SmallVector<SDValue, 16> Ops(NumConcat);
1557 SDValue UndefVal = DAG.getUNDEF(InVT);
1558 for (unsigned i = 1; i != NumConcat; ++i) {
1561 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1562 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1566 if (InVTNumElts % WidenNumElts == 0) {
1567 // Extract the input and convert the shorten input vector.
1568 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1569 DAG.getIntPtrConstant(0));
1570 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1575 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1576 SmallVector<SDValue, 16> Ops(WidenNumElts);
1577 EVT EltVT = WidenVT.getVectorElementType();
1578 DTyOp = DAG.getValueType(EltVT);
1579 STyOp = DAG.getValueType(InEltVT);
1581 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1583 for (i=0; i < MinElts; ++i) {
1584 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1585 DAG.getIntPtrConstant(i));
1586 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1590 SDValue UndefVal = DAG.getUNDEF(EltVT);
1591 for (; i < WidenNumElts; ++i)
1594 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1597 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1598 EVT VT = N->getValueType(0);
1599 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1600 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1601 SDValue InOp = N->getOperand(0);
1602 SDValue Idx = N->getOperand(1);
1603 DebugLoc dl = N->getDebugLoc();
1605 if (getTypeAction(InOp.getValueType()) == WidenVector)
1606 InOp = GetWidenedVector(InOp);
1608 EVT InVT = InOp.getValueType();
1610 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
1612 unsigned IdxVal = CIdx->getZExtValue();
1613 // Check if we can just return the input vector after widening.
1614 if (IdxVal == 0 && InVT == WidenVT)
1617 // Check if we can extract from the vector.
1618 unsigned InNumElts = InVT.getVectorNumElements();
1619 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1620 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1623 // We could try widening the input to the right length but for now, extract
1624 // the original elements, fill the rest with undefs and build a vector.
1625 SmallVector<SDValue, 16> Ops(WidenNumElts);
1626 EVT EltVT = VT.getVectorElementType();
1627 EVT IdxVT = Idx.getValueType();
1628 unsigned NumElts = VT.getVectorNumElements();
1631 unsigned IdxVal = CIdx->getZExtValue();
1632 for (i=0; i < NumElts; ++i)
1633 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1634 DAG.getConstant(IdxVal+i, IdxVT));
1636 Ops[0] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, Idx);
1637 for (i=1; i < NumElts; ++i) {
1638 SDValue NewIdx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1639 DAG.getConstant(i, IdxVT));
1640 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, NewIdx);
1644 SDValue UndefVal = DAG.getUNDEF(EltVT);
1645 for (; i < WidenNumElts; ++i)
1647 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1650 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1651 SDValue InOp = GetWidenedVector(N->getOperand(0));
1652 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1653 InOp.getValueType(), InOp,
1654 N->getOperand(1), N->getOperand(2));
1657 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1658 LoadSDNode *LD = cast<LoadSDNode>(N);
1659 ISD::LoadExtType ExtType = LD->getExtensionType();
1662 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1663 if (ExtType != ISD::NON_EXTLOAD)
1664 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
1666 Result = GenWidenVectorLoads(LdChain, LD);
1668 // If we generate a single load, we can use that for the chain. Otherwise,
1669 // build a factor node to remember the multiple loads are independent and
1672 if (LdChain.size() == 1)
1673 NewChain = LdChain[0];
1675 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other,
1676 &LdChain[0], LdChain.size());
1678 // Modified the chain - switch anything that used the old chain to use
1680 ReplaceValueWith(SDValue(N, 1), NewChain);
1685 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1686 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1687 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1688 WidenVT, N->getOperand(0));
1691 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1692 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1693 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1695 SDValue Cond1 = N->getOperand(0);
1696 EVT CondVT = Cond1.getValueType();
1697 if (CondVT.isVector()) {
1698 EVT CondEltVT = CondVT.getVectorElementType();
1699 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), CondEltVT, WidenNumElts);
1700 if (getTypeAction(CondVT) == WidenVector)
1701 Cond1 = GetWidenedVector(Cond1);
1703 if (Cond1.getValueType() != CondWidenVT)
1704 Cond1 = ModifyToType(Cond1, CondWidenVT);
1707 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1708 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1709 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1710 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
1711 WidenVT, Cond1, InOp1, InOp2);
1714 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1715 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1716 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1717 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1718 InOp1.getValueType(), N->getOperand(0),
1719 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1722 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
1723 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1724 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1725 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1726 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
1727 InOp1, InOp2, N->getOperand(2));
1730 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1731 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1732 return DAG.getUNDEF(WidenVT);
1735 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
1736 EVT VT = N->getValueType(0);
1737 DebugLoc dl = N->getDebugLoc();
1739 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1740 unsigned NumElts = VT.getVectorNumElements();
1741 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1743 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1744 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1746 // Adjust mask based on new input vector length.
1747 SmallVector<int, 16> NewMask;
1748 for (unsigned i = 0; i != NumElts; ++i) {
1749 int Idx = N->getMaskElt(i);
1750 if (Idx < (int)NumElts)
1751 NewMask.push_back(Idx);
1753 NewMask.push_back(Idx - NumElts + WidenNumElts);
1755 for (unsigned i = NumElts; i != WidenNumElts; ++i)
1756 NewMask.push_back(-1);
1757 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
1760 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1761 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1762 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1764 SDValue InOp1 = N->getOperand(0);
1765 EVT InVT = InOp1.getValueType();
1766 assert(InVT.isVector() && "can not widen non vector type");
1767 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), WidenNumElts);
1768 InOp1 = GetWidenedVector(InOp1);
1769 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1771 // Assume that the input and output will be widen appropriately. If not,
1772 // we will have to unroll it at some point.
1773 assert(InOp1.getValueType() == WidenInVT &&
1774 InOp2.getValueType() == WidenInVT &&
1775 "Input not widened to expected type!");
1776 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(),
1777 WidenVT, InOp1, InOp2, N->getOperand(2));
1781 //===----------------------------------------------------------------------===//
1782 // Widen Vector Operand
1783 //===----------------------------------------------------------------------===//
1784 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
1785 DEBUG(dbgs() << "Widen node operand " << ResNo << ": ";
1788 SDValue Res = SDValue();
1790 switch (N->getOpcode()) {
1793 dbgs() << "WidenVectorOperand op #" << ResNo << ": ";
1797 llvm_unreachable("Do not know how to widen this operator's operand!");
1799 case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break;
1800 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
1801 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
1802 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
1803 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
1806 case ISD::FP_TO_SINT:
1807 case ISD::FP_TO_UINT:
1808 case ISD::SINT_TO_FP:
1809 case ISD::UINT_TO_FP:
1811 case ISD::SIGN_EXTEND:
1812 case ISD::ZERO_EXTEND:
1813 case ISD::ANY_EXTEND:
1814 Res = WidenVecOp_Convert(N);
1818 // If Res is null, the sub-method took care of registering the result.
1819 if (!Res.getNode()) return false;
1821 // If the result is N, the sub-method updated N in place. Tell the legalizer
1823 if (Res.getNode() == N)
1827 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1828 "Invalid operand expansion");
1830 ReplaceValueWith(SDValue(N, 0), Res);
1834 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
1835 // Since the result is legal and the input is illegal, it is unlikely
1836 // that we can fix the input to a legal type so unroll the convert
1837 // into some scalar code and create a nasty build vector.
1838 EVT VT = N->getValueType(0);
1839 EVT EltVT = VT.getVectorElementType();
1840 DebugLoc dl = N->getDebugLoc();
1841 unsigned NumElts = VT.getVectorNumElements();
1842 SDValue InOp = N->getOperand(0);
1843 if (getTypeAction(InOp.getValueType()) == WidenVector)
1844 InOp = GetWidenedVector(InOp);
1845 EVT InVT = InOp.getValueType();
1846 EVT InEltVT = InVT.getVectorElementType();
1848 unsigned Opcode = N->getOpcode();
1849 SmallVector<SDValue, 16> Ops(NumElts);
1850 for (unsigned i=0; i < NumElts; ++i)
1851 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
1852 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1853 DAG.getIntPtrConstant(i)));
1855 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
1858 SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) {
1859 EVT VT = N->getValueType(0);
1860 SDValue InOp = GetWidenedVector(N->getOperand(0));
1861 EVT InWidenVT = InOp.getValueType();
1862 DebugLoc dl = N->getDebugLoc();
1864 // Check if we can convert between two legal vector types and extract.
1865 unsigned InWidenSize = InWidenVT.getSizeInBits();
1866 unsigned Size = VT.getSizeInBits();
1867 if (InWidenSize % Size == 0 && !VT.isVector()) {
1868 unsigned NewNumElts = InWidenSize / Size;
1869 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
1870 if (TLI.isTypeLegal(NewVT)) {
1871 SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp);
1872 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
1873 DAG.getIntPtrConstant(0));
1877 return CreateStackStoreLoad(InOp, VT);
1880 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
1881 // If the input vector is not legal, it is likely that we will not find a
1882 // legal vector of the same size. Replace the concatenate vector with a
1883 // nasty build vector.
1884 EVT VT = N->getValueType(0);
1885 EVT EltVT = VT.getVectorElementType();
1886 DebugLoc dl = N->getDebugLoc();
1887 unsigned NumElts = VT.getVectorNumElements();
1888 SmallVector<SDValue, 16> Ops(NumElts);
1890 EVT InVT = N->getOperand(0).getValueType();
1891 unsigned NumInElts = InVT.getVectorNumElements();
1894 unsigned NumOperands = N->getNumOperands();
1895 for (unsigned i=0; i < NumOperands; ++i) {
1896 SDValue InOp = N->getOperand(i);
1897 if (getTypeAction(InOp.getValueType()) == WidenVector)
1898 InOp = GetWidenedVector(InOp);
1899 for (unsigned j=0; j < NumInElts; ++j)
1900 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1901 DAG.getIntPtrConstant(j));
1903 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
1906 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1907 SDValue InOp = GetWidenedVector(N->getOperand(0));
1908 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
1909 N->getValueType(0), InOp, N->getOperand(1));
1912 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1913 SDValue InOp = GetWidenedVector(N->getOperand(0));
1914 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
1915 N->getValueType(0), InOp, N->getOperand(1));
1918 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
1919 // We have to widen the value but we want only to store the original
1921 StoreSDNode *ST = cast<StoreSDNode>(N);
1923 SmallVector<SDValue, 16> StChain;
1924 if (ST->isTruncatingStore())
1925 GenWidenVectorTruncStores(StChain, ST);
1927 GenWidenVectorStores(StChain, ST);
1929 if (StChain.size() == 1)
1932 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(),
1933 MVT::Other,&StChain[0],StChain.size());
1936 //===----------------------------------------------------------------------===//
1937 // Vector Widening Utilities
1938 //===----------------------------------------------------------------------===//
1940 // Utility function to find the type to chop up a widen vector for load/store
1941 // TLI: Target lowering used to determine legal types.
1942 // Width: Width left need to load/store.
1943 // WidenVT: The widen vector type to load to/store from
1944 // Align: If 0, don't allow use of a wider type
1945 // WidenEx: If Align is not 0, the amount additional we can load/store from.
1947 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
1948 unsigned Width, EVT WidenVT,
1949 unsigned Align = 0, unsigned WidenEx = 0) {
1950 EVT WidenEltVT = WidenVT.getVectorElementType();
1951 unsigned WidenWidth = WidenVT.getSizeInBits();
1952 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
1953 unsigned AlignInBits = Align*8;
1955 // If we have one element to load/store, return it.
1956 EVT RetVT = WidenEltVT;
1957 if (Width == WidenEltWidth)
1960 // See if there is larger legal integer than the element type to load/store
1962 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
1963 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
1964 EVT MemVT((MVT::SimpleValueType) VT);
1965 unsigned MemVTWidth = MemVT.getSizeInBits();
1966 if (MemVT.getSizeInBits() <= WidenEltWidth)
1968 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
1969 (MemVTWidth <= Width ||
1970 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
1976 // See if there is a larger vector type to load/store that has the same vector
1977 // element type and is evenly divisible with the WidenVT.
1978 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
1979 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
1980 EVT MemVT = (MVT::SimpleValueType) VT;
1981 unsigned MemVTWidth = MemVT.getSizeInBits();
1982 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
1983 (WidenWidth % MemVTWidth) == 0 &&
1984 (MemVTWidth <= Width ||
1985 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
1986 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
1994 // Builds a vector type from scalar loads
1995 // VecTy: Resulting Vector type
1996 // LDOps: Load operators to build a vector type
1997 // [Start,End) the list of loads to use.
1998 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
1999 SmallVector<SDValue, 16>& LdOps,
2000 unsigned Start, unsigned End) {
2001 DebugLoc dl = LdOps[Start].getDebugLoc();
2002 EVT LdTy = LdOps[Start].getValueType();
2003 unsigned Width = VecTy.getSizeInBits();
2004 unsigned NumElts = Width / LdTy.getSizeInBits();
2005 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2008 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2010 for (unsigned i = Start + 1; i != End; ++i) {
2011 EVT NewLdTy = LdOps[i].getValueType();
2012 if (NewLdTy != LdTy) {
2013 NumElts = Width / NewLdTy.getSizeInBits();
2014 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2015 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp);
2016 // Readjust position and vector position based on new load type
2017 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2020 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2021 DAG.getIntPtrConstant(Idx++));
2023 return DAG.getNode(ISD::BIT_CONVERT, dl, VecTy, VecOp);
2026 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain,
2028 // The strategy assumes that we can efficiently load powers of two widths.
2029 // The routines chops the vector into the largest vector loads with the same
2030 // element type or scalar loads and then recombines it to the widen vector
2032 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), LD->getValueType(0));
2033 unsigned WidenWidth = WidenVT.getSizeInBits();
2034 EVT LdVT = LD->getMemoryVT();
2035 DebugLoc dl = LD->getDebugLoc();
2036 assert(LdVT.isVector() && WidenVT.isVector());
2037 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2040 SDValue Chain = LD->getChain();
2041 SDValue BasePtr = LD->getBasePtr();
2042 int SVOffset = LD->getSrcValueOffset();
2043 unsigned Align = LD->getAlignment();
2044 bool isVolatile = LD->isVolatile();
2045 const Value *SV = LD->getSrcValue();
2047 int LdWidth = LdVT.getSizeInBits();
2048 int WidthDiff = WidenWidth - LdWidth; // Difference
2049 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
2051 // Find the vector type that can load from.
2052 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2053 int NewVTWidth = NewVT.getSizeInBits();
2054 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, SV, SVOffset,
2056 LdChain.push_back(LdOp.getValue(1));
2058 // Check if we can load the element with one instruction
2059 if (LdWidth <= NewVTWidth) {
2060 if (NewVT.isVector()) {
2061 if (NewVT != WidenVT) {
2062 assert(WidenWidth % NewVTWidth == 0);
2063 unsigned NumConcat = WidenWidth / NewVTWidth;
2064 SmallVector<SDValue, 16> ConcatOps(NumConcat);
2065 SDValue UndefVal = DAG.getUNDEF(NewVT);
2066 ConcatOps[0] = LdOp;
2067 for (unsigned i = 1; i != NumConcat; ++i)
2068 ConcatOps[i] = UndefVal;
2069 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
2074 unsigned NumElts = WidenWidth / LdWidth;
2075 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2076 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2077 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, VecOp);
2081 // Load vector by using multiple loads from largest vector to scalar
2082 SmallVector<SDValue, 16> LdOps;
2083 LdOps.push_back(LdOp);
2085 LdWidth -= NewVTWidth;
2086 unsigned Offset = 0;
2088 while (LdWidth > 0) {
2089 unsigned Increment = NewVTWidth / 8;
2090 Offset += Increment;
2091 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2092 DAG.getIntPtrConstant(Increment));
2094 if (LdWidth < NewVTWidth) {
2095 // Our current type we are using is too large, find a better size
2096 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2097 NewVTWidth = NewVT.getSizeInBits();
2100 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, SV,
2101 SVOffset+Offset, isVolatile,
2102 MinAlign(Align, Increment));
2103 LdChain.push_back(LdOp.getValue(1));
2104 LdOps.push_back(LdOp);
2106 LdWidth -= NewVTWidth;
2109 // Build the vector from the loads operations
2110 unsigned End = LdOps.size();
2111 if (LdOps[0].getValueType().isVector()) {
2112 // If the load contains vectors, build the vector using concat vector.
2113 // All of the vectors used to loads are power of 2 and the scalars load
2114 // can be combined to make a power of 2 vector.
2115 SmallVector<SDValue, 16> ConcatOps(End);
2118 EVT LdTy = LdOps[i].getValueType();
2119 // First combine the scalar loads to a vector
2120 if (!LdTy.isVector()) {
2121 for (--i; i >= 0; --i) {
2122 LdTy = LdOps[i].getValueType();
2123 if (LdTy.isVector())
2126 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
2128 ConcatOps[--Idx] = LdOps[i];
2129 for (--i; i >= 0; --i) {
2130 EVT NewLdTy = LdOps[i].getValueType();
2131 if (NewLdTy != LdTy) {
2132 // Create a larger vector
2133 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2134 &ConcatOps[Idx], End - Idx);
2138 ConcatOps[--Idx] = LdOps[i];
2141 if (WidenWidth != LdTy.getSizeInBits()*(End - Idx)) {
2142 // We need to fill the rest with undefs to build the vector
2143 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
2144 SmallVector<SDValue, 16> WidenOps(NumOps);
2145 SDValue UndefVal = DAG.getUNDEF(LdTy);
2147 for (; i != End-Idx; ++i)
2148 WidenOps[i] = ConcatOps[Idx+i];
2149 for (; i != NumOps; ++i)
2150 WidenOps[i] = UndefVal;
2151 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
2153 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2154 &ConcatOps[Idx], End - Idx);
2155 } else // All the loads are scalar loads.
2156 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
2160 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,
2162 ISD::LoadExtType ExtType) {
2163 // For extension loads, it may not be more efficient to chop up the vector
2164 // and then extended it. Instead, we unroll the load and build a new vector.
2165 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2166 EVT LdVT = LD->getMemoryVT();
2167 DebugLoc dl = LD->getDebugLoc();
2168 assert(LdVT.isVector() && WidenVT.isVector());
2171 SDValue Chain = LD->getChain();
2172 SDValue BasePtr = LD->getBasePtr();
2173 int SVOffset = LD->getSrcValueOffset();
2174 unsigned Align = LD->getAlignment();
2175 bool isVolatile = LD->isVolatile();
2176 const Value *SV = LD->getSrcValue();
2178 EVT EltVT = WidenVT.getVectorElementType();
2179 EVT LdEltVT = LdVT.getVectorElementType();
2180 unsigned NumElts = LdVT.getVectorNumElements();
2182 // Load each element and widen
2183 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2184 SmallVector<SDValue, 16> Ops(WidenNumElts);
2185 unsigned Increment = LdEltVT.getSizeInBits() / 8;
2186 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, SV, SVOffset,
2187 LdEltVT, isVolatile, Align);
2188 LdChain.push_back(Ops[0].getValue(1));
2189 unsigned i = 0, Offset = Increment;
2190 for (i=1; i < NumElts; ++i, Offset += Increment) {
2191 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2192 BasePtr, DAG.getIntPtrConstant(Offset));
2193 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, SV,
2194 SVOffset + Offset, LdEltVT, isVolatile, Align);
2195 LdChain.push_back(Ops[i].getValue(1));
2198 // Fill the rest with undefs
2199 SDValue UndefVal = DAG.getUNDEF(EltVT);
2200 for (; i != WidenNumElts; ++i)
2203 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
2207 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2209 // The strategy assumes that we can efficiently store powers of two widths.
2210 // The routines chops the vector into the largest vector stores with the same
2211 // element type or scalar stores.
2212 SDValue Chain = ST->getChain();
2213 SDValue BasePtr = ST->getBasePtr();
2214 const Value *SV = ST->getSrcValue();
2215 int SVOffset = ST->getSrcValueOffset();
2216 unsigned Align = ST->getAlignment();
2217 bool isVolatile = ST->isVolatile();
2218 SDValue ValOp = GetWidenedVector(ST->getValue());
2219 DebugLoc dl = ST->getDebugLoc();
2221 EVT StVT = ST->getMemoryVT();
2222 unsigned StWidth = StVT.getSizeInBits();
2223 EVT ValVT = ValOp.getValueType();
2224 unsigned ValWidth = ValVT.getSizeInBits();
2225 EVT ValEltVT = ValVT.getVectorElementType();
2226 unsigned ValEltWidth = ValEltVT.getSizeInBits();
2227 assert(StVT.getVectorElementType() == ValEltVT);
2229 int Idx = 0; // current index to store
2230 unsigned Offset = 0; // offset from base to store
2231 while (StWidth != 0) {
2232 // Find the largest vector type we can store with
2233 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
2234 unsigned NewVTWidth = NewVT.getSizeInBits();
2235 unsigned Increment = NewVTWidth / 8;
2236 if (NewVT.isVector()) {
2237 unsigned NumVTElts = NewVT.getVectorNumElements();
2239 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2240 DAG.getIntPtrConstant(Idx));
2241 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
2242 SVOffset + Offset, isVolatile,
2243 MinAlign(Align, Offset)));
2244 StWidth -= NewVTWidth;
2245 Offset += Increment;
2247 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2248 DAG.getIntPtrConstant(Increment));
2249 } while (StWidth != 0 && StWidth >= NewVTWidth);
2251 // Cast the vector to the scalar type we can store
2252 unsigned NumElts = ValWidth / NewVTWidth;
2253 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2254 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, ValOp);
2255 // Readjust index position based on new vector type
2256 Idx = Idx * ValEltWidth / NewVTWidth;
2258 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2259 DAG.getIntPtrConstant(Idx++));
2260 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
2261 SVOffset + Offset, isVolatile,
2262 MinAlign(Align, Offset)));
2263 StWidth -= NewVTWidth;
2264 Offset += Increment;
2265 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2266 DAG.getIntPtrConstant(Increment));
2267 } while (StWidth != 0 && StWidth >= NewVTWidth);
2268 // Restore index back to be relative to the original widen element type
2269 Idx = Idx * NewVTWidth / ValEltWidth;
2275 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,
2277 // For extension loads, it may not be more efficient to truncate the vector
2278 // and then store it. Instead, we extract each element and then store it.
2279 SDValue Chain = ST->getChain();
2280 SDValue BasePtr = ST->getBasePtr();
2281 const Value *SV = ST->getSrcValue();
2282 int SVOffset = ST->getSrcValueOffset();
2283 unsigned Align = ST->getAlignment();
2284 bool isVolatile = ST->isVolatile();
2285 SDValue ValOp = GetWidenedVector(ST->getValue());
2286 DebugLoc dl = ST->getDebugLoc();
2288 EVT StVT = ST->getMemoryVT();
2289 EVT ValVT = ValOp.getValueType();
2291 // It must be true that we the widen vector type is bigger than where
2292 // we need to store.
2293 assert(StVT.isVector() && ValOp.getValueType().isVector());
2294 assert(StVT.bitsLT(ValOp.getValueType()));
2296 // For truncating stores, we can not play the tricks of chopping legal
2297 // vector types and bit cast it to the right type. Instead, we unroll
2299 EVT StEltVT = StVT.getVectorElementType();
2300 EVT ValEltVT = ValVT.getVectorElementType();
2301 unsigned Increment = ValEltVT.getSizeInBits() / 8;
2302 unsigned NumElts = StVT.getVectorNumElements();
2303 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2304 DAG.getIntPtrConstant(0));
2305 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, SV,
2307 isVolatile, Align));
2308 unsigned Offset = Increment;
2309 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
2310 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2311 BasePtr, DAG.getIntPtrConstant(Offset));
2312 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2313 DAG.getIntPtrConstant(0));
2314 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, SV,
2315 SVOffset + Offset, StEltVT,
2316 isVolatile, MinAlign(Align, Offset)));
2320 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2321 /// input vector must have the same element type as NVT.
2322 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
2323 // Note that InOp might have been widened so it might already have
2324 // the right width or it might need be narrowed.
2325 EVT InVT = InOp.getValueType();
2326 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2327 "input and widen element type must match");
2328 DebugLoc dl = InOp.getDebugLoc();
2330 // Check if InOp already has the right width.
2334 unsigned InNumElts = InVT.getVectorNumElements();
2335 unsigned WidenNumElts = NVT.getVectorNumElements();
2336 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2337 unsigned NumConcat = WidenNumElts / InNumElts;
2338 SmallVector<SDValue, 16> Ops(NumConcat);
2339 SDValue UndefVal = DAG.getUNDEF(InVT);
2341 for (unsigned i = 1; i != NumConcat; ++i)
2344 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2347 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2348 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2349 DAG.getIntPtrConstant(0));
2351 // Fall back to extract and build.
2352 SmallVector<SDValue, 16> Ops(WidenNumElts);
2353 EVT EltVT = NVT.getVectorElementType();
2354 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2356 for (Idx = 0; Idx < MinNumElts; ++Idx)
2357 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2358 DAG.getIntPtrConstant(Idx));
2360 SDValue UndefVal = DAG.getUNDEF(EltVT);
2361 for ( ; Idx < WidenNumElts; ++Idx)
2362 Ops[Idx] = UndefVal;
2363 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);