1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
73 case ISD::CTLZ_ZERO_UNDEF:
76 case ISD::CTTZ_ZERO_UNDEF:
96 case ISD::SIGN_EXTEND:
100 case ISD::ZERO_EXTEND:
101 R = ScalarizeVecRes_UnaryOp(N);
129 R = ScalarizeVecRes_BinOp(N);
132 R = ScalarizeVecRes_TernaryOp(N);
136 // If R is null, the sub-method took care of registering the result.
138 SetScalarizedVector(SDValue(N, ResNo), R);
141 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
142 SDValue LHS = GetScalarizedVector(N->getOperand(0));
143 SDValue RHS = GetScalarizedVector(N->getOperand(1));
144 return DAG.getNode(N->getOpcode(), SDLoc(N),
145 LHS.getValueType(), LHS, RHS, N->getFlags());
148 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
149 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
150 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
151 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
152 return DAG.getNode(N->getOpcode(), SDLoc(N),
153 Op0.getValueType(), Op0, Op1, Op2);
156 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
158 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
159 return GetScalarizedVector(Op);
162 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
163 EVT NewVT = N->getValueType(0).getVectorElementType();
164 return DAG.getNode(ISD::BITCAST, SDLoc(N),
165 NewVT, N->getOperand(0));
168 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
169 EVT EltVT = N->getValueType(0).getVectorElementType();
170 SDValue InOp = N->getOperand(0);
171 // The BUILD_VECTOR operands may be of wider element types and
172 // we may need to truncate them back to the requested return type.
173 if (EltVT.isInteger())
174 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
178 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
179 EVT NewVT = N->getValueType(0).getVectorElementType();
180 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
181 return DAG.getConvertRndSat(NewVT, SDLoc(N),
182 Op0, DAG.getValueType(NewVT),
183 DAG.getValueType(Op0.getValueType()),
186 cast<CvtRndSatSDNode>(N)->getCvtCode());
189 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
190 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
191 N->getValueType(0).getVectorElementType(),
192 N->getOperand(0), N->getOperand(1));
195 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
196 EVT NewVT = N->getValueType(0).getVectorElementType();
197 SDValue Op = GetScalarizedVector(N->getOperand(0));
198 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
199 NewVT, Op, N->getOperand(1));
202 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
203 SDValue Op = GetScalarizedVector(N->getOperand(0));
204 return DAG.getNode(ISD::FPOWI, SDLoc(N),
205 Op.getValueType(), Op, N->getOperand(1));
208 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
209 // The value to insert may have a wider type than the vector element type,
210 // so be sure to truncate it to the element type if necessary.
211 SDValue Op = N->getOperand(1);
212 EVT EltVT = N->getValueType(0).getVectorElementType();
213 if (Op.getValueType() != EltVT)
214 // FIXME: Can this happen for floating point types?
215 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
219 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
220 assert(N->isUnindexed() && "Indexed vector load?");
222 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
223 N->getExtensionType(),
224 N->getValueType(0).getVectorElementType(),
226 N->getChain(), N->getBasePtr(),
227 DAG.getUNDEF(N->getBasePtr().getValueType()),
229 N->getMemoryVT().getVectorElementType(),
230 N->isVolatile(), N->isNonTemporal(),
231 N->isInvariant(), N->getOriginalAlignment(),
234 // Legalized the chain result - switch anything that used the old chain to
236 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
240 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
241 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
242 EVT DestVT = N->getValueType(0).getVectorElementType();
243 SDValue Op = N->getOperand(0);
244 EVT OpVT = Op.getValueType();
246 // The result needs scalarizing, but it's not a given that the source does.
247 // This is a workaround for targets where it's impossible to scalarize the
248 // result of a conversion, because the source type is legal.
249 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
250 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
251 // legal and was not scalarized.
252 // See the similar logic in ScalarizeVecRes_VSETCC
253 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
254 Op = GetScalarizedVector(Op);
256 EVT VT = OpVT.getVectorElementType();
258 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
259 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
261 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
264 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
265 EVT EltVT = N->getValueType(0).getVectorElementType();
266 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
267 SDValue LHS = GetScalarizedVector(N->getOperand(0));
268 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
269 LHS, DAG.getValueType(ExtVT));
272 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
273 // If the operand is wider than the vector element type then it is implicitly
274 // truncated. Make that explicit here.
275 EVT EltVT = N->getValueType(0).getVectorElementType();
276 SDValue InOp = N->getOperand(0);
277 if (InOp.getValueType() != EltVT)
278 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
282 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
283 SDValue Cond = GetScalarizedVector(N->getOperand(0));
284 SDValue LHS = GetScalarizedVector(N->getOperand(1));
285 TargetLowering::BooleanContent ScalarBool =
286 TLI.getBooleanContents(false, false);
287 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
289 // If integer and float booleans have different contents then we can't
290 // reliably optimize in all cases. There is a full explanation for this in
291 // DAGCombiner::visitSELECT() where the same issue affects folding
292 // (select C, 0, 1) to (xor C, 1).
293 if (TLI.getBooleanContents(false, false) !=
294 TLI.getBooleanContents(false, true)) {
295 // At least try the common case where the boolean is generated by a
297 if (Cond->getOpcode() == ISD::SETCC) {
298 EVT OpVT = Cond->getOperand(0)->getValueType(0);
299 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
300 VecBool = TLI.getBooleanContents(OpVT);
302 ScalarBool = TargetLowering::UndefinedBooleanContent;
305 if (ScalarBool != VecBool) {
306 EVT CondVT = Cond.getValueType();
307 switch (ScalarBool) {
308 case TargetLowering::UndefinedBooleanContent:
310 case TargetLowering::ZeroOrOneBooleanContent:
311 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
312 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
313 // Vector read from all ones, scalar expects a single 1 so mask.
314 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
315 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
317 case TargetLowering::ZeroOrNegativeOneBooleanContent:
318 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
319 VecBool == TargetLowering::ZeroOrOneBooleanContent);
320 // Vector reads from a one, scalar from all ones so sign extend.
321 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
322 Cond, DAG.getValueType(MVT::i1));
327 return DAG.getSelect(SDLoc(N),
328 LHS.getValueType(), Cond, LHS,
329 GetScalarizedVector(N->getOperand(2)));
332 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
333 SDValue LHS = GetScalarizedVector(N->getOperand(1));
334 return DAG.getSelect(SDLoc(N),
335 LHS.getValueType(), N->getOperand(0), LHS,
336 GetScalarizedVector(N->getOperand(2)));
339 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
340 SDValue LHS = GetScalarizedVector(N->getOperand(2));
341 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
342 N->getOperand(0), N->getOperand(1),
343 LHS, GetScalarizedVector(N->getOperand(3)),
347 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
348 assert(N->getValueType(0).isVector() ==
349 N->getOperand(0).getValueType().isVector() &&
350 "Scalar/Vector type mismatch");
352 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
354 SDValue LHS = GetScalarizedVector(N->getOperand(0));
355 SDValue RHS = GetScalarizedVector(N->getOperand(1));
358 // Turn it into a scalar SETCC.
359 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
362 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
363 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
366 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
367 // Figure out if the scalar is the LHS or RHS and return it.
368 SDValue Arg = N->getOperand(2).getOperand(0);
369 if (Arg.getOpcode() == ISD::UNDEF)
370 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
371 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
372 return GetScalarizedVector(N->getOperand(Op));
375 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
376 assert(N->getValueType(0).isVector() &&
377 N->getOperand(0).getValueType().isVector() &&
378 "Operand types must be vectors");
379 SDValue LHS = N->getOperand(0);
380 SDValue RHS = N->getOperand(1);
381 EVT OpVT = LHS.getValueType();
382 EVT NVT = N->getValueType(0).getVectorElementType();
385 // The result needs scalarizing, but it's not a given that the source does.
386 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
387 LHS = GetScalarizedVector(LHS);
388 RHS = GetScalarizedVector(RHS);
390 EVT VT = OpVT.getVectorElementType();
392 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
393 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
395 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
396 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
399 // Turn it into a scalar SETCC.
400 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
402 // Vectors may have a different boolean contents to scalars. Promote the
403 // value appropriately.
404 ISD::NodeType ExtendCode =
405 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
406 return DAG.getNode(ExtendCode, DL, NVT, Res);
410 //===----------------------------------------------------------------------===//
411 // Operand Vector Scalarization <1 x ty> -> ty.
412 //===----------------------------------------------------------------------===//
414 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
415 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
418 SDValue Res = SDValue();
420 if (!Res.getNode()) {
421 switch (N->getOpcode()) {
424 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
428 llvm_unreachable("Do not know how to scalarize this operator's operand!");
430 Res = ScalarizeVecOp_BITCAST(N);
432 case ISD::ANY_EXTEND:
433 case ISD::ZERO_EXTEND:
434 case ISD::SIGN_EXTEND:
436 case ISD::FP_TO_SINT:
437 case ISD::FP_TO_UINT:
438 case ISD::SINT_TO_FP:
439 case ISD::UINT_TO_FP:
440 Res = ScalarizeVecOp_UnaryOp(N);
442 case ISD::CONCAT_VECTORS:
443 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
445 case ISD::EXTRACT_VECTOR_ELT:
446 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
449 Res = ScalarizeVecOp_VSELECT(N);
452 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
455 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
460 // If the result is null, the sub-method took care of registering results etc.
461 if (!Res.getNode()) return false;
463 // If the result is N, the sub-method updated N in place. Tell the legalizer
465 if (Res.getNode() == N)
468 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
469 "Invalid operand expansion");
471 ReplaceValueWith(SDValue(N, 0), Res);
475 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
476 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
477 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
478 SDValue Elt = GetScalarizedVector(N->getOperand(0));
479 return DAG.getNode(ISD::BITCAST, SDLoc(N),
480 N->getValueType(0), Elt);
483 /// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
484 /// scalarized, it must be <1 x ty>. Do the operation on the element instead.
485 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
486 assert(N->getValueType(0).getVectorNumElements() == 1 &&
487 "Unexpected vector type!");
488 SDValue Elt = GetScalarizedVector(N->getOperand(0));
489 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
490 N->getValueType(0).getScalarType(), Elt);
491 // Revectorize the result so the types line up with what the uses of this
492 // expression expect.
493 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
496 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
497 /// use a BUILD_VECTOR instead.
498 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
499 SmallVector<SDValue, 8> Ops(N->getNumOperands());
500 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
501 Ops[i] = GetScalarizedVector(N->getOperand(i));
502 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
505 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
506 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
508 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
509 SDValue Res = GetScalarizedVector(N->getOperand(0));
510 if (Res.getValueType() != N->getValueType(0))
511 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
517 /// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
518 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
519 /// (still with vector output type since that was acceptable if we got here).
520 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
521 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
522 EVT VT = N->getValueType(0);
524 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
528 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
529 /// scalarized, it must be <1 x ty>. Just store the element.
530 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
531 assert(N->isUnindexed() && "Indexed store of one-element vector?");
532 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
535 if (N->isTruncatingStore())
536 return DAG.getTruncStore(N->getChain(), dl,
537 GetScalarizedVector(N->getOperand(1)),
538 N->getBasePtr(), N->getPointerInfo(),
539 N->getMemoryVT().getVectorElementType(),
540 N->isVolatile(), N->isNonTemporal(),
541 N->getAlignment(), N->getAAInfo());
543 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
544 N->getBasePtr(), N->getPointerInfo(),
545 N->isVolatile(), N->isNonTemporal(),
546 N->getOriginalAlignment(), N->getAAInfo());
549 /// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
550 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
551 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
552 SDValue Elt = GetScalarizedVector(N->getOperand(0));
553 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
554 N->getValueType(0).getVectorElementType(), Elt,
556 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
559 //===----------------------------------------------------------------------===//
560 // Result Vector Splitting
561 //===----------------------------------------------------------------------===//
563 /// SplitVectorResult - This method is called when the specified result of the
564 /// specified node is found to need vector splitting. At this point, the node
565 /// may also have invalid operands or may have other results that need
566 /// legalization, we just know that (at least) one result needs vector
568 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
569 DEBUG(dbgs() << "Split node result: ";
574 // See if the target wants to custom expand this node.
575 if (CustomLowerNode(N, N->getValueType(ResNo), true))
578 switch (N->getOpcode()) {
581 dbgs() << "SplitVectorResult #" << ResNo << ": ";
585 report_fatal_error("Do not know how to split the result of this "
588 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
590 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
591 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
592 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
593 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
594 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
595 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
596 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
597 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
598 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
599 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
600 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
601 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
602 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
603 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
605 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
608 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
611 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
614 SplitVecRes_SETCC(N, Lo, Hi);
616 case ISD::VECTOR_SHUFFLE:
617 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
620 case ISD::BITREVERSE:
622 case ISD::CONVERT_RNDSAT:
625 case ISD::CTLZ_ZERO_UNDEF:
626 case ISD::CTTZ_ZERO_UNDEF:
637 case ISD::FNEARBYINT:
641 case ISD::FP_TO_SINT:
642 case ISD::FP_TO_UINT:
648 case ISD::SINT_TO_FP:
650 case ISD::UINT_TO_FP:
651 SplitVecRes_UnaryOp(N, Lo, Hi);
654 case ISD::ANY_EXTEND:
655 case ISD::SIGN_EXTEND:
656 case ISD::ZERO_EXTEND:
657 SplitVecRes_ExtendOp(N, Lo, Hi);
687 SplitVecRes_BinOp(N, Lo, Hi);
690 SplitVecRes_TernaryOp(N, Lo, Hi);
694 // If Lo/Hi is null, the sub-method took care of registering results etc.
696 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
699 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
701 SDValue LHSLo, LHSHi;
702 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
703 SDValue RHSLo, RHSHi;
704 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
707 const SDNodeFlags *Flags = N->getFlags();
708 unsigned Opcode = N->getOpcode();
709 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
710 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
713 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
715 SDValue Op0Lo, Op0Hi;
716 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
717 SDValue Op1Lo, Op1Hi;
718 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
719 SDValue Op2Lo, Op2Hi;
720 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
723 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
724 Op0Lo, Op1Lo, Op2Lo);
725 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
726 Op0Hi, Op1Hi, Op2Hi);
729 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
731 // We know the result is a vector. The input may be either a vector or a
734 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
737 SDValue InOp = N->getOperand(0);
738 EVT InVT = InOp.getValueType();
740 // Handle some special cases efficiently.
741 switch (getTypeAction(InVT)) {
742 case TargetLowering::TypeLegal:
743 case TargetLowering::TypePromoteInteger:
744 case TargetLowering::TypePromoteFloat:
745 case TargetLowering::TypeSoftenFloat:
746 case TargetLowering::TypeScalarizeVector:
747 case TargetLowering::TypeWidenVector:
749 case TargetLowering::TypeExpandInteger:
750 case TargetLowering::TypeExpandFloat:
751 // A scalar to vector conversion, where the scalar needs expansion.
752 // If the vector is being split in two then we can just convert the
755 GetExpandedOp(InOp, Lo, Hi);
756 if (DAG.getDataLayout().isBigEndian())
758 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
759 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
763 case TargetLowering::TypeSplitVector:
764 // If the input is a vector that needs to be split, convert each split
765 // piece of the input now.
766 GetSplitVector(InOp, Lo, Hi);
767 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
768 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
772 // In the general case, convert the input to an integer and split it by hand.
773 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
774 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
775 if (DAG.getDataLayout().isBigEndian())
776 std::swap(LoIntVT, HiIntVT);
778 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
780 if (DAG.getDataLayout().isBigEndian())
782 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
783 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
786 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
790 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
791 unsigned LoNumElts = LoVT.getVectorNumElements();
792 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
793 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
795 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
796 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
799 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
801 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
803 unsigned NumSubvectors = N->getNumOperands() / 2;
804 if (NumSubvectors == 1) {
805 Lo = N->getOperand(0);
806 Hi = N->getOperand(1);
811 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
813 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
814 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
816 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
817 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
820 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
822 SDValue Vec = N->getOperand(0);
823 SDValue Idx = N->getOperand(1);
827 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
829 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
830 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
831 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
832 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
833 TLI.getVectorIdxTy(DAG.getDataLayout())));
836 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
838 SDValue Vec = N->getOperand(0);
839 SDValue SubVec = N->getOperand(1);
840 SDValue Idx = N->getOperand(2);
842 GetSplitVector(Vec, Lo, Hi);
844 // Spill the vector to the stack.
845 EVT VecVT = Vec.getValueType();
846 EVT SubVecVT = VecVT.getVectorElementType();
847 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
848 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
849 MachinePointerInfo(), false, false, 0);
851 // Store the new subvector into the specified index.
852 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
853 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
854 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
855 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
858 // Load the Lo part from the stack slot.
859 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
860 false, false, false, 0);
862 // Increment the pointer to the other part.
863 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
865 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
866 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
868 // Load the Hi part from the stack slot.
869 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
870 false, false, false, MinAlign(Alignment, IncrementSize));
873 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
876 GetSplitVector(N->getOperand(0), Lo, Hi);
877 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
878 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
881 void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
883 SDValue LHSLo, LHSHi;
884 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
887 SDValue RHSLo, RHSHi;
888 SDValue RHS = N->getOperand(1);
889 EVT RHSVT = RHS.getValueType();
890 if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
891 GetSplitVector(RHS, RHSLo, RHSHi);
893 std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
896 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
897 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
900 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
902 SDValue LHSLo, LHSHi;
903 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
907 std::tie(LoVT, HiVT) =
908 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
910 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
911 DAG.getValueType(LoVT));
912 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
913 DAG.getValueType(HiVT));
916 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
918 SDValue Vec = N->getOperand(0);
919 SDValue Elt = N->getOperand(1);
920 SDValue Idx = N->getOperand(2);
922 GetSplitVector(Vec, Lo, Hi);
924 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
925 unsigned IdxVal = CIdx->getZExtValue();
926 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
927 if (IdxVal < LoNumElts)
928 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
929 Lo.getValueType(), Lo, Elt, Idx);
932 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
933 DAG.getConstant(IdxVal - LoNumElts, dl,
934 TLI.getVectorIdxTy(DAG.getDataLayout())));
938 // See if the target wants to custom expand this node.
939 if (CustomLowerNode(N, N->getValueType(0), true))
942 // Spill the vector to the stack.
943 EVT VecVT = Vec.getValueType();
944 EVT EltVT = VecVT.getVectorElementType();
945 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
946 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
947 MachinePointerInfo(), false, false, 0);
949 // Store the new element. This may be larger than the vector element type,
950 // so use a truncating store.
951 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
952 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
953 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
954 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
957 // Load the Lo part from the stack slot.
958 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
959 false, false, false, 0);
961 // Increment the pointer to the other part.
962 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
963 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
964 DAG.getConstant(IncrementSize, dl,
965 StackPtr.getValueType()));
967 // Load the Hi part from the stack slot.
968 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
969 false, false, false, MinAlign(Alignment, IncrementSize));
972 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
976 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
977 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
978 Hi = DAG.getUNDEF(HiVT);
981 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
983 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
986 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
988 ISD::LoadExtType ExtType = LD->getExtensionType();
989 SDValue Ch = LD->getChain();
990 SDValue Ptr = LD->getBasePtr();
991 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
992 EVT MemoryVT = LD->getMemoryVT();
993 unsigned Alignment = LD->getOriginalAlignment();
994 bool isVolatile = LD->isVolatile();
995 bool isNonTemporal = LD->isNonTemporal();
996 bool isInvariant = LD->isInvariant();
997 AAMDNodes AAInfo = LD->getAAInfo();
999 EVT LoMemVT, HiMemVT;
1000 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1002 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1003 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
1004 isInvariant, Alignment, AAInfo);
1006 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1007 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1008 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1009 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
1010 LD->getPointerInfo().getWithOffset(IncrementSize),
1011 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
1014 // Build a factor node to remember that this load is independent of the
1016 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1019 // Legalized the chain result - switch anything that used the old chain to
1021 ReplaceValueWith(SDValue(LD, 1), Ch);
1024 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1025 SDValue &Lo, SDValue &Hi) {
1028 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1030 SDValue Ch = MLD->getChain();
1031 SDValue Ptr = MLD->getBasePtr();
1032 SDValue Mask = MLD->getMask();
1033 unsigned Alignment = MLD->getOriginalAlignment();
1034 ISD::LoadExtType ExtType = MLD->getExtensionType();
1036 // if Alignment is equal to the vector size,
1037 // take the half of it for the second part
1038 unsigned SecondHalfAlignment =
1039 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1040 Alignment/2 : Alignment;
1042 SDValue MaskLo, MaskHi;
1043 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1045 EVT MemoryVT = MLD->getMemoryVT();
1046 EVT LoMemVT, HiMemVT;
1047 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1049 SDValue Src0 = MLD->getSrc0();
1050 SDValue Src0Lo, Src0Hi;
1051 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1053 MachineMemOperand *MMO = DAG.getMachineFunction().
1054 getMachineMemOperand(MLD->getPointerInfo(),
1055 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1056 Alignment, MLD->getAAInfo(), MLD->getRanges());
1058 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1061 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1062 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1063 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1065 MMO = DAG.getMachineFunction().
1066 getMachineMemOperand(MLD->getPointerInfo(),
1067 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1068 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1070 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1074 // Build a factor node to remember that this load is independent of the
1076 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1079 // Legalized the chain result - switch anything that used the old chain to
1081 ReplaceValueWith(SDValue(MLD, 1), Ch);
1085 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1086 SDValue &Lo, SDValue &Hi) {
1089 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1091 SDValue Ch = MGT->getChain();
1092 SDValue Ptr = MGT->getBasePtr();
1093 SDValue Mask = MGT->getMask();
1094 unsigned Alignment = MGT->getOriginalAlignment();
1096 SDValue MaskLo, MaskHi;
1097 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1099 EVT MemoryVT = MGT->getMemoryVT();
1100 EVT LoMemVT, HiMemVT;
1101 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1103 SDValue Src0Lo, Src0Hi;
1104 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
1106 SDValue IndexHi, IndexLo;
1107 std::tie(IndexLo, IndexHi) = DAG.SplitVector(MGT->getIndex(), dl);
1109 MachineMemOperand *MMO = DAG.getMachineFunction().
1110 getMachineMemOperand(MGT->getPointerInfo(),
1111 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1112 Alignment, MGT->getAAInfo(), MGT->getRanges());
1114 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1115 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1118 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1119 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1122 // Build a factor node to remember that this load is independent of the
1124 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1127 // Legalized the chain result - switch anything that used the old chain to
1129 ReplaceValueWith(SDValue(MGT, 1), Ch);
1133 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1134 assert(N->getValueType(0).isVector() &&
1135 N->getOperand(0).getValueType().isVector() &&
1136 "Operand types must be vectors");
1140 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1143 SDValue LL, LH, RL, RH;
1144 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1145 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1147 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1148 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1151 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1153 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1156 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1158 // If the input also splits, handle it directly for a compile time speedup.
1159 // Otherwise split it by hand.
1160 EVT InVT = N->getOperand(0).getValueType();
1161 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1162 GetSplitVector(N->getOperand(0), Lo, Hi);
1164 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1166 if (N->getOpcode() == ISD::FP_ROUND) {
1167 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1168 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1169 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1170 SDValue DTyOpLo = DAG.getValueType(LoVT);
1171 SDValue DTyOpHi = DAG.getValueType(HiVT);
1172 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1173 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1174 SDValue RndOp = N->getOperand(3);
1175 SDValue SatOp = N->getOperand(4);
1176 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1177 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1179 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1182 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1183 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1187 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1190 EVT SrcVT = N->getOperand(0).getValueType();
1191 EVT DestVT = N->getValueType(0);
1193 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1195 // We can do better than a generic split operation if the extend is doing
1196 // more than just doubling the width of the elements and the following are
1198 // - The number of vector elements is even,
1199 // - the source type is legal,
1200 // - the type of a split source is illegal,
1201 // - the type of an extended (by doubling element size) source is legal, and
1202 // - the type of that extended source when split is legal.
1204 // This won't necessarily completely legalize the operation, but it will
1205 // more effectively move in the right direction and prevent falling down
1206 // to scalarization in many cases due to the input vector being split too
1208 unsigned NumElements = SrcVT.getVectorNumElements();
1209 if ((NumElements & 1) == 0 &&
1210 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1211 LLVMContext &Ctx = *DAG.getContext();
1212 EVT NewSrcVT = EVT::getVectorVT(
1213 Ctx, EVT::getIntegerVT(
1214 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1217 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1218 EVT SplitLoVT, SplitHiVT;
1219 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1220 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1221 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1222 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1223 N->dump(&DAG); dbgs() << "\n");
1224 // Extend the source vector by one step.
1226 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1227 // Get the low and high halves of the new, extended one step, vector.
1228 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1229 // Extend those vector halves the rest of the way.
1230 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1231 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1235 // Fall back to the generic unary operator splitting otherwise.
1236 SplitVecRes_UnaryOp(N, Lo, Hi);
1239 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1240 SDValue &Lo, SDValue &Hi) {
1241 // The low and high parts of the original input give four input vectors.
1244 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1245 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1246 EVT NewVT = Inputs[0].getValueType();
1247 unsigned NewElts = NewVT.getVectorNumElements();
1249 // If Lo or Hi uses elements from at most two of the four input vectors, then
1250 // express it as a vector shuffle of those two inputs. Otherwise extract the
1251 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1252 SmallVector<int, 16> Ops;
1253 for (unsigned High = 0; High < 2; ++High) {
1254 SDValue &Output = High ? Hi : Lo;
1256 // Build a shuffle mask for the output, discovering on the fly which
1257 // input vectors to use as shuffle operands (recorded in InputUsed).
1258 // If building a suitable shuffle vector proves too hard, then bail
1259 // out with useBuildVector set.
1260 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1261 unsigned FirstMaskIdx = High * NewElts;
1262 bool useBuildVector = false;
1263 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1264 // The mask element. This indexes into the input.
1265 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1267 // The input vector this mask element indexes into.
1268 unsigned Input = (unsigned)Idx / NewElts;
1270 if (Input >= array_lengthof(Inputs)) {
1271 // The mask element does not index into any input vector.
1276 // Turn the index into an offset from the start of the input vector.
1277 Idx -= Input * NewElts;
1279 // Find or create a shuffle vector operand to hold this input.
1281 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1282 if (InputUsed[OpNo] == Input) {
1283 // This input vector is already an operand.
1285 } else if (InputUsed[OpNo] == -1U) {
1286 // Create a new operand for this input vector.
1287 InputUsed[OpNo] = Input;
1292 if (OpNo >= array_lengthof(InputUsed)) {
1293 // More than two input vectors used! Give up on trying to create a
1294 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1295 useBuildVector = true;
1299 // Add the mask index for the new shuffle vector.
1300 Ops.push_back(Idx + OpNo * NewElts);
1303 if (useBuildVector) {
1304 EVT EltVT = NewVT.getVectorElementType();
1305 SmallVector<SDValue, 16> SVOps;
1307 // Extract the input elements by hand.
1308 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1309 // The mask element. This indexes into the input.
1310 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1312 // The input vector this mask element indexes into.
1313 unsigned Input = (unsigned)Idx / NewElts;
1315 if (Input >= array_lengthof(Inputs)) {
1316 // The mask element is "undef" or indexes off the end of the input.
1317 SVOps.push_back(DAG.getUNDEF(EltVT));
1321 // Turn the index into an offset from the start of the input vector.
1322 Idx -= Input * NewElts;
1324 // Extract the vector element by hand.
1325 SVOps.push_back(DAG.getNode(
1326 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input],
1327 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1330 // Construct the Lo/Hi output using a BUILD_VECTOR.
1331 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1332 } else if (InputUsed[0] == -1U) {
1333 // No input vectors were used! The result is undefined.
1334 Output = DAG.getUNDEF(NewVT);
1336 SDValue Op0 = Inputs[InputUsed[0]];
1337 // If only one input was used, use an undefined vector for the other.
1338 SDValue Op1 = InputUsed[1] == -1U ?
1339 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1340 // At least one input vector was used. Create a new shuffle vector.
1341 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
1349 //===----------------------------------------------------------------------===//
1350 // Operand Vector Splitting
1351 //===----------------------------------------------------------------------===//
1353 /// SplitVectorOperand - This method is called when the specified operand of the
1354 /// specified node is found to need vector splitting. At this point, all of the
1355 /// result types of the node are known to be legal, but other operands of the
1356 /// node may need legalization as well as the specified one.
1357 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1358 DEBUG(dbgs() << "Split node operand: ";
1361 SDValue Res = SDValue();
1363 // See if the target wants to custom split this node.
1364 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1367 if (!Res.getNode()) {
1368 switch (N->getOpcode()) {
1371 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1375 report_fatal_error("Do not know how to split this operator's "
1378 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1379 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1380 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1381 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1382 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1384 Res = SplitVecOp_TruncateHelper(N);
1386 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1387 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1389 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1392 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1395 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1398 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1401 Res = SplitVecOp_VSELECT(N, OpNo);
1403 case ISD::FP_TO_SINT:
1404 case ISD::FP_TO_UINT:
1405 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1406 Res = SplitVecOp_TruncateHelper(N);
1408 Res = SplitVecOp_UnaryOp(N);
1410 case ISD::SINT_TO_FP:
1411 case ISD::UINT_TO_FP:
1412 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1413 Res = SplitVecOp_TruncateHelper(N);
1415 Res = SplitVecOp_UnaryOp(N);
1420 case ISD::FP_EXTEND:
1421 case ISD::SIGN_EXTEND:
1422 case ISD::ZERO_EXTEND:
1423 case ISD::ANY_EXTEND:
1425 Res = SplitVecOp_UnaryOp(N);
1430 // If the result is null, the sub-method took care of registering results etc.
1431 if (!Res.getNode()) return false;
1433 // If the result is N, the sub-method updated N in place. Tell the legalizer
1435 if (Res.getNode() == N)
1438 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1439 "Invalid operand expansion");
1441 ReplaceValueWith(SDValue(N, 0), Res);
1445 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1446 // The only possibility for an illegal operand is the mask, since result type
1447 // legalization would have handled this node already otherwise.
1448 assert(OpNo == 0 && "Illegal operand must be mask");
1450 SDValue Mask = N->getOperand(0);
1451 SDValue Src0 = N->getOperand(1);
1452 SDValue Src1 = N->getOperand(2);
1453 EVT Src0VT = Src0.getValueType();
1455 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1458 GetSplitVector(N->getOperand(0), Lo, Hi);
1459 assert(Lo.getValueType() == Hi.getValueType() &&
1460 "Lo and Hi have differing types");
1463 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1464 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1466 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1467 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1468 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1469 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1472 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1474 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1476 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1479 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1480 // The result has a legal vector type, but the input needs splitting.
1481 EVT ResVT = N->getValueType(0);
1484 GetSplitVector(N->getOperand(0), Lo, Hi);
1485 EVT InVT = Lo.getValueType();
1487 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1488 InVT.getVectorNumElements());
1490 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1491 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1493 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1496 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1497 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1498 // end up being split all the way down to individual components. Convert the
1499 // split pieces into integers and reassemble.
1501 GetSplitVector(N->getOperand(0), Lo, Hi);
1502 Lo = BitConvertToInteger(Lo);
1503 Hi = BitConvertToInteger(Hi);
1505 if (DAG.getDataLayout().isBigEndian())
1508 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1509 JoinIntegers(Lo, Hi));
1512 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1513 // We know that the extracted result type is legal.
1514 EVT SubVT = N->getValueType(0);
1515 SDValue Idx = N->getOperand(1);
1518 GetSplitVector(N->getOperand(0), Lo, Hi);
1520 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1521 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1523 if (IdxVal < LoElts) {
1524 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1525 "Extracted subvector crosses vector split!");
1526 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1528 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1529 DAG.getConstant(IdxVal - LoElts, dl,
1530 Idx.getValueType()));
1534 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1535 SDValue Vec = N->getOperand(0);
1536 SDValue Idx = N->getOperand(1);
1537 EVT VecVT = Vec.getValueType();
1539 if (isa<ConstantSDNode>(Idx)) {
1540 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1541 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1544 GetSplitVector(Vec, Lo, Hi);
1546 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1548 if (IdxVal < LoElts)
1549 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1550 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1551 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1552 Idx.getValueType())), 0);
1555 // See if the target wants to custom expand this node.
1556 if (CustomLowerNode(N, N->getValueType(0), true))
1559 // Make the vector elements byte-addressable if they aren't already.
1561 EVT EltVT = VecVT.getVectorElementType();
1562 if (EltVT.getSizeInBits() < 8) {
1563 SmallVector<SDValue, 4> ElementOps;
1564 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) {
1565 ElementOps.push_back(DAG.getAnyExtOrTrunc(
1566 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec,
1567 DAG.getConstant(i, dl, MVT::i8)),
1572 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1573 VecVT.getVectorNumElements());
1574 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, ElementOps);
1577 // Store the vector to the stack.
1578 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1579 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1580 MachinePointerInfo(), false, false, 0);
1582 // Load back the required element.
1583 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1584 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1585 MachinePointerInfo(), EltVT, false, false, false, 0);
1588 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1592 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1594 SDValue Ch = MGT->getChain();
1595 SDValue Ptr = MGT->getBasePtr();
1596 SDValue Index = MGT->getIndex();
1597 SDValue Mask = MGT->getMask();
1598 unsigned Alignment = MGT->getOriginalAlignment();
1600 SDValue MaskLo, MaskHi;
1601 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1603 EVT MemoryVT = MGT->getMemoryVT();
1604 EVT LoMemVT, HiMemVT;
1605 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1607 SDValue Src0Lo, Src0Hi;
1608 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
1610 SDValue IndexHi, IndexLo;
1611 if (Index.getNode())
1612 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1614 IndexLo = IndexHi = Index;
1616 MachineMemOperand *MMO = DAG.getMachineFunction().
1617 getMachineMemOperand(MGT->getPointerInfo(),
1618 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1619 Alignment, MGT->getAAInfo(), MGT->getRanges());
1621 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1622 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1625 MMO = DAG.getMachineFunction().
1626 getMachineMemOperand(MGT->getPointerInfo(),
1627 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1628 Alignment, MGT->getAAInfo(),
1631 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1632 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1635 // Build a factor node to remember that this load is independent of the
1637 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1640 // Legalized the chain result - switch anything that used the old chain to
1642 ReplaceValueWith(SDValue(MGT, 1), Ch);
1644 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
1646 ReplaceValueWith(SDValue(MGT, 0), Res);
1650 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1652 SDValue Ch = N->getChain();
1653 SDValue Ptr = N->getBasePtr();
1654 SDValue Mask = N->getMask();
1655 SDValue Data = N->getValue();
1656 EVT MemoryVT = N->getMemoryVT();
1657 unsigned Alignment = N->getOriginalAlignment();
1660 EVT LoMemVT, HiMemVT;
1661 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1663 SDValue DataLo, DataHi;
1664 GetSplitVector(Data, DataLo, DataHi);
1665 SDValue MaskLo, MaskHi;
1666 GetSplitVector(Mask, MaskLo, MaskHi);
1668 // if Alignment is equal to the vector size,
1669 // take the half of it for the second part
1670 unsigned SecondHalfAlignment =
1671 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1672 Alignment/2 : Alignment;
1675 MachineMemOperand *MMO = DAG.getMachineFunction().
1676 getMachineMemOperand(N->getPointerInfo(),
1677 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1678 Alignment, N->getAAInfo(), N->getRanges());
1680 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1681 N->isTruncatingStore());
1683 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1684 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1685 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1687 MMO = DAG.getMachineFunction().
1688 getMachineMemOperand(N->getPointerInfo(),
1689 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1690 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1692 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1693 N->isTruncatingStore());
1695 // Build a factor node to remember that this store is independent of the
1697 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1700 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
1702 SDValue Ch = N->getChain();
1703 SDValue Ptr = N->getBasePtr();
1704 SDValue Mask = N->getMask();
1705 SDValue Index = N->getIndex();
1706 SDValue Data = N->getValue();
1707 EVT MemoryVT = N->getMemoryVT();
1708 unsigned Alignment = N->getOriginalAlignment();
1711 EVT LoMemVT, HiMemVT;
1712 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1714 SDValue DataLo, DataHi;
1715 GetSplitVector(Data, DataLo, DataHi);
1716 SDValue MaskLo, MaskHi;
1717 GetSplitVector(Mask, MaskLo, MaskHi);
1719 SDValue PtrLo, PtrHi;
1720 if (Ptr.getValueType().isVector()) // gather form vector of pointers
1721 std::tie(PtrLo, PtrHi) = DAG.SplitVector(Ptr, DL);
1723 PtrLo = PtrHi = Ptr;
1725 SDValue IndexHi, IndexLo;
1726 if (Index.getNode())
1727 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
1729 IndexLo = IndexHi = Index;
1732 MachineMemOperand *MMO = DAG.getMachineFunction().
1733 getMachineMemOperand(N->getPointerInfo(),
1734 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1735 Alignment, N->getAAInfo(), N->getRanges());
1737 SDValue OpsLo[] = {Ch, DataLo, MaskLo, PtrLo, IndexLo};
1738 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
1741 MMO = DAG.getMachineFunction().
1742 getMachineMemOperand(N->getPointerInfo(),
1743 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1744 Alignment, N->getAAInfo(), N->getRanges());
1746 SDValue OpsHi[] = {Ch, DataHi, MaskHi, PtrHi, IndexHi};
1747 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
1750 // Build a factor node to remember that this store is independent of the
1752 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1755 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1756 assert(N->isUnindexed() && "Indexed store of vector?");
1757 assert(OpNo == 1 && "Can only split the stored value");
1760 bool isTruncating = N->isTruncatingStore();
1761 SDValue Ch = N->getChain();
1762 SDValue Ptr = N->getBasePtr();
1763 EVT MemoryVT = N->getMemoryVT();
1764 unsigned Alignment = N->getOriginalAlignment();
1765 bool isVol = N->isVolatile();
1766 bool isNT = N->isNonTemporal();
1767 AAMDNodes AAInfo = N->getAAInfo();
1769 GetSplitVector(N->getOperand(1), Lo, Hi);
1771 EVT LoMemVT, HiMemVT;
1772 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1774 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1777 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1778 LoMemVT, isVol, isNT, Alignment, AAInfo);
1780 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1781 isVol, isNT, Alignment, AAInfo);
1783 // Increment the pointer to the other half.
1784 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1785 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1788 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1789 N->getPointerInfo().getWithOffset(IncrementSize),
1790 HiMemVT, isVol, isNT, Alignment, AAInfo);
1792 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1793 N->getPointerInfo().getWithOffset(IncrementSize),
1794 isVol, isNT, Alignment, AAInfo);
1796 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1799 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1802 // The input operands all must have the same type, and we know the result
1803 // type is valid. Convert this to a buildvector which extracts all the
1805 // TODO: If the input elements are power-two vectors, we could convert this to
1806 // a new CONCAT_VECTORS node with elements that are half-wide.
1807 SmallVector<SDValue, 32> Elts;
1808 EVT EltVT = N->getValueType(0).getVectorElementType();
1809 for (const SDValue &Op : N->op_values()) {
1810 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1812 Elts.push_back(DAG.getNode(
1813 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
1814 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1818 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1821 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
1822 // The result type is legal, but the input type is illegal. If splitting
1823 // ends up with the result type of each half still being legal, just
1824 // do that. If, however, that would result in an illegal result type,
1825 // we can try to get more clever with power-two vectors. Specifically,
1826 // split the input type, but also widen the result element size, then
1827 // concatenate the halves and truncate again. For example, consider a target
1828 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1829 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1830 // %inlo = v4i32 extract_subvector %in, 0
1831 // %inhi = v4i32 extract_subvector %in, 4
1832 // %lo16 = v4i16 trunc v4i32 %inlo
1833 // %hi16 = v4i16 trunc v4i32 %inhi
1834 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1835 // %res = v8i8 trunc v8i16 %in16
1837 // Without this transform, the original truncate would end up being
1838 // scalarized, which is pretty much always a last resort.
1839 SDValue InVec = N->getOperand(0);
1840 EVT InVT = InVec->getValueType(0);
1841 EVT OutVT = N->getValueType(0);
1842 unsigned NumElements = OutVT.getVectorNumElements();
1843 bool IsFloat = OutVT.isFloatingPoint();
1845 // Widening should have already made sure this is a power-two vector
1846 // if we're trying to split it at all. assert() that's true, just in case.
1847 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1849 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1850 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1852 // If the input elements are only 1/2 the width of the result elements,
1853 // just use the normal splitting. Our trick only work if there's room
1854 // to split more than once.
1855 if (InElementSize <= OutElementSize * 2)
1856 return SplitVecOp_UnaryOp(N);
1859 // Extract the halves of the input via extract_subvector.
1860 SDValue InLoVec, InHiVec;
1861 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1862 // Truncate them to 1/2 the element size.
1863 EVT HalfElementVT = IsFloat ?
1864 EVT::getFloatingPointVT(InElementSize/2) :
1865 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1866 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1868 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1869 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1870 // Concatenate them to get the full intermediate truncation result.
1871 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1872 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1874 // Now finish up by truncating all the way down to the original result
1875 // type. This should normally be something that ends up being legal directly,
1876 // but in theory if a target has very wide vectors and an annoyingly
1877 // restricted set of legal types, this split can chain to build things up.
1879 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
1880 DAG.getTargetConstant(
1881 0, DL, TLI.getPointerTy(DAG.getDataLayout())))
1882 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1885 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1886 assert(N->getValueType(0).isVector() &&
1887 N->getOperand(0).getValueType().isVector() &&
1888 "Operand types must be vectors");
1889 // The result has a legal vector type, but the input needs splitting.
1890 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1892 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1893 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1894 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1895 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1896 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1898 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1899 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1900 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1901 return PromoteTargetBoolean(Con, N->getValueType(0));
1905 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1906 // The result has a legal vector type, but the input needs splitting.
1907 EVT ResVT = N->getValueType(0);
1910 GetSplitVector(N->getOperand(0), Lo, Hi);
1911 EVT InVT = Lo.getValueType();
1913 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1914 InVT.getVectorNumElements());
1916 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1917 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1919 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1922 SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
1923 // The result (and the first input) has a legal vector type, but the second
1924 // input needs splitting.
1925 return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
1929 //===----------------------------------------------------------------------===//
1930 // Result Vector Widening
1931 //===----------------------------------------------------------------------===//
1933 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1934 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1938 // See if the target wants to custom widen this node.
1939 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1942 SDValue Res = SDValue();
1943 switch (N->getOpcode()) {
1946 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1950 llvm_unreachable("Do not know how to widen the result of this operator!");
1952 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1953 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1954 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1955 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1956 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1957 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1958 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1959 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1960 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1961 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1962 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1964 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1965 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1966 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1967 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1968 case ISD::VECTOR_SHUFFLE:
1969 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1972 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
1987 Res = WidenVecRes_Binary(N);
2000 Res = WidenVecRes_BinaryCanTrap(N);
2003 case ISD::FCOPYSIGN:
2004 Res = WidenVecRes_FCOPYSIGN(N);
2008 Res = WidenVecRes_POWI(N);
2014 Res = WidenVecRes_Shift(N);
2017 case ISD::ANY_EXTEND:
2018 case ISD::FP_EXTEND:
2020 case ISD::FP_TO_SINT:
2021 case ISD::FP_TO_UINT:
2022 case ISD::SIGN_EXTEND:
2023 case ISD::SINT_TO_FP:
2025 case ISD::UINT_TO_FP:
2026 case ISD::ZERO_EXTEND:
2027 Res = WidenVecRes_Convert(N);
2030 case ISD::BITREVERSE:
2044 case ISD::FNEARBYINT:
2051 Res = WidenVecRes_Unary(N);
2054 Res = WidenVecRes_Ternary(N);
2058 // If Res is null, the sub-method took care of registering the result.
2060 SetWidenedVector(SDValue(N, ResNo), Res);
2063 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2064 // Ternary op widening.
2066 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2067 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2068 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2069 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2070 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2073 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2074 // Binary op widening.
2076 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2077 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2078 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2079 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2082 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2083 // Binary op widening for operations that can trap.
2084 unsigned Opcode = N->getOpcode();
2086 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2087 EVT WidenEltVT = WidenVT.getVectorElementType();
2089 unsigned NumElts = VT.getVectorNumElements();
2090 const SDNodeFlags *Flags = N->getFlags();
2091 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2092 NumElts = NumElts / 2;
2093 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2096 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2097 // Operation doesn't trap so just widen as normal.
2098 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2099 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2100 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
2103 // No legal vector version so unroll the vector operation and then widen.
2105 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2107 // Since the operation can trap, apply operation on the original vector.
2109 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2110 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2111 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2113 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2114 unsigned ConcatEnd = 0; // Current ConcatOps index.
2115 int Idx = 0; // Current Idx into input vectors.
2117 // NumElts := greatest legal vector size (at most WidenVT)
2118 // while (orig. vector has unhandled elements) {
2119 // take munches of size NumElts from the beginning and add to ConcatOps
2120 // NumElts := next smaller supported vector size or 1
2122 while (CurNumElts != 0) {
2123 while (CurNumElts >= NumElts) {
2124 SDValue EOp1 = DAG.getNode(
2125 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2126 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2127 SDValue EOp2 = DAG.getNode(
2128 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2129 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2130 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2, Flags);
2132 CurNumElts -= NumElts;
2135 NumElts = NumElts / 2;
2136 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2137 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2140 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2141 SDValue EOp1 = DAG.getNode(
2142 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1,
2143 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2144 SDValue EOp2 = DAG.getNode(
2145 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2,
2146 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2147 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2154 // Check to see if we have a single operation with the widen type.
2155 if (ConcatEnd == 1) {
2156 VT = ConcatOps[0].getValueType();
2158 return ConcatOps[0];
2161 // while (Some element of ConcatOps is not of type MaxVT) {
2162 // From the end of ConcatOps, collect elements of the same type and put
2163 // them into an op of the next larger supported type
2165 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2166 Idx = ConcatEnd - 1;
2167 VT = ConcatOps[Idx--].getValueType();
2168 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2171 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2175 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2176 } while (!TLI.isTypeLegal(NextVT));
2178 if (!VT.isVector()) {
2179 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2180 SDValue VecOp = DAG.getUNDEF(NextVT);
2181 unsigned NumToInsert = ConcatEnd - Idx - 1;
2182 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2183 VecOp = DAG.getNode(
2184 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2185 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2187 ConcatOps[Idx+1] = VecOp;
2188 ConcatEnd = Idx + 2;
2190 // Vector type, create a CONCAT_VECTORS of type NextVT
2191 SDValue undefVec = DAG.getUNDEF(VT);
2192 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2193 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2194 unsigned RealVals = ConcatEnd - Idx - 1;
2195 unsigned SubConcatEnd = 0;
2196 unsigned SubConcatIdx = Idx + 1;
2197 while (SubConcatEnd < RealVals)
2198 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2199 while (SubConcatEnd < OpsToConcat)
2200 SubConcatOps[SubConcatEnd++] = undefVec;
2201 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2202 NextVT, SubConcatOps);
2203 ConcatEnd = SubConcatIdx + 1;
2207 // Check to see if we have a single operation with the widen type.
2208 if (ConcatEnd == 1) {
2209 VT = ConcatOps[0].getValueType();
2211 return ConcatOps[0];
2214 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2215 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2216 if (NumOps != ConcatEnd ) {
2217 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2218 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2219 ConcatOps[j] = UndefVal;
2221 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2222 makeArrayRef(ConcatOps.data(), NumOps));
2225 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2226 SDValue InOp = N->getOperand(0);
2229 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2230 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2232 EVT InVT = InOp.getValueType();
2233 EVT InEltVT = InVT.getVectorElementType();
2234 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2236 unsigned Opcode = N->getOpcode();
2237 unsigned InVTNumElts = InVT.getVectorNumElements();
2238 const SDNodeFlags *Flags = N->getFlags();
2239 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2240 InOp = GetWidenedVector(N->getOperand(0));
2241 InVT = InOp.getValueType();
2242 InVTNumElts = InVT.getVectorNumElements();
2243 if (InVTNumElts == WidenNumElts) {
2244 if (N->getNumOperands() == 1)
2245 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2246 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
2250 if (TLI.isTypeLegal(InWidenVT)) {
2251 // Because the result and the input are different vector types, widening
2252 // the result could create a legal type but widening the input might make
2253 // it an illegal type that might lead to repeatedly splitting the input
2254 // and then widening it. To avoid this, we widen the input only if
2255 // it results in a legal type.
2256 if (WidenNumElts % InVTNumElts == 0) {
2257 // Widen the input and call convert on the widened input vector.
2258 unsigned NumConcat = WidenNumElts/InVTNumElts;
2259 SmallVector<SDValue, 16> Ops(NumConcat);
2261 SDValue UndefVal = DAG.getUNDEF(InVT);
2262 for (unsigned i = 1; i != NumConcat; ++i)
2264 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2265 if (N->getNumOperands() == 1)
2266 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2267 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
2270 if (InVTNumElts % WidenNumElts == 0) {
2271 SDValue InVal = DAG.getNode(
2272 ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2273 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2274 // Extract the input and convert the shorten input vector.
2275 if (N->getNumOperands() == 1)
2276 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2277 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
2281 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2282 SmallVector<SDValue, 16> Ops(WidenNumElts);
2283 EVT EltVT = WidenVT.getVectorElementType();
2284 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2286 for (i=0; i < MinElts; ++i) {
2287 SDValue Val = DAG.getNode(
2288 ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2289 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2290 if (N->getNumOperands() == 1)
2291 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2293 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
2296 SDValue UndefVal = DAG.getUNDEF(EltVT);
2297 for (; i < WidenNumElts; ++i)
2300 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2303 SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
2304 // If this is an FCOPYSIGN with same input types, we can treat it as a
2305 // normal (can trap) binary op.
2306 if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
2307 return WidenVecRes_BinaryCanTrap(N);
2309 // If the types are different, fall back to unrolling.
2310 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2311 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2314 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2315 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2316 SDValue InOp = GetWidenedVector(N->getOperand(0));
2317 SDValue ShOp = N->getOperand(1);
2318 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2321 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2322 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2323 SDValue InOp = GetWidenedVector(N->getOperand(0));
2324 SDValue ShOp = N->getOperand(1);
2326 EVT ShVT = ShOp.getValueType();
2327 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2328 ShOp = GetWidenedVector(ShOp);
2329 ShVT = ShOp.getValueType();
2331 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2332 ShVT.getVectorElementType(),
2333 WidenVT.getVectorNumElements());
2334 if (ShVT != ShWidenVT)
2335 ShOp = ModifyToType(ShOp, ShWidenVT);
2337 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2340 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2341 // Unary op widening.
2342 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2343 SDValue InOp = GetWidenedVector(N->getOperand(0));
2344 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2347 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2348 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2349 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2350 cast<VTSDNode>(N->getOperand(1))->getVT()
2351 .getVectorElementType(),
2352 WidenVT.getVectorNumElements());
2353 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2354 return DAG.getNode(N->getOpcode(), SDLoc(N),
2355 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2358 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2359 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2360 return GetWidenedVector(WidenVec);
2363 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2364 SDValue InOp = N->getOperand(0);
2365 EVT InVT = InOp.getValueType();
2366 EVT VT = N->getValueType(0);
2367 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2370 switch (getTypeAction(InVT)) {
2371 case TargetLowering::TypeLegal:
2373 case TargetLowering::TypePromoteInteger:
2374 // If the incoming type is a vector that is being promoted, then
2375 // we know that the elements are arranged differently and that we
2376 // must perform the conversion using a stack slot.
2377 if (InVT.isVector())
2380 // If the InOp is promoted to the same size, convert it. Otherwise,
2381 // fall out of the switch and widen the promoted input.
2382 InOp = GetPromotedInteger(InOp);
2383 InVT = InOp.getValueType();
2384 if (WidenVT.bitsEq(InVT))
2385 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2387 case TargetLowering::TypeSoftenFloat:
2388 case TargetLowering::TypePromoteFloat:
2389 case TargetLowering::TypeExpandInteger:
2390 case TargetLowering::TypeExpandFloat:
2391 case TargetLowering::TypeScalarizeVector:
2392 case TargetLowering::TypeSplitVector:
2394 case TargetLowering::TypeWidenVector:
2395 // If the InOp is widened to the same size, convert it. Otherwise, fall
2396 // out of the switch and widen the widened input.
2397 InOp = GetWidenedVector(InOp);
2398 InVT = InOp.getValueType();
2399 if (WidenVT.bitsEq(InVT))
2400 // The input widens to the same size. Convert to the widen value.
2401 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2405 unsigned WidenSize = WidenVT.getSizeInBits();
2406 unsigned InSize = InVT.getSizeInBits();
2407 // x86mmx is not an acceptable vector element type, so don't try.
2408 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2409 // Determine new input vector type. The new input vector type will use
2410 // the same element type (if its a vector) or use the input type as a
2411 // vector. It is the same size as the type to widen to.
2413 unsigned NewNumElts = WidenSize / InSize;
2414 if (InVT.isVector()) {
2415 EVT InEltVT = InVT.getVectorElementType();
2416 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2417 WidenSize / InEltVT.getSizeInBits());
2419 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2422 if (TLI.isTypeLegal(NewInVT)) {
2423 // Because the result and the input are different vector types, widening
2424 // the result could create a legal type but widening the input might make
2425 // it an illegal type that might lead to repeatedly splitting the input
2426 // and then widening it. To avoid this, we widen the input only if
2427 // it results in a legal type.
2428 SmallVector<SDValue, 16> Ops(NewNumElts);
2429 SDValue UndefVal = DAG.getUNDEF(InVT);
2431 for (unsigned i = 1; i < NewNumElts; ++i)
2435 if (InVT.isVector())
2436 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2438 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2439 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2443 return CreateStackStoreLoad(InOp, WidenVT);
2446 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2448 // Build a vector with undefined for the new nodes.
2449 EVT VT = N->getValueType(0);
2451 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2452 // type. The UNDEFs need to have the same type as the existing operands.
2453 EVT EltVT = N->getOperand(0).getValueType();
2454 unsigned NumElts = VT.getVectorNumElements();
2456 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2457 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2459 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2460 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2461 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2463 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2466 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2467 EVT InVT = N->getOperand(0).getValueType();
2468 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2470 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2471 unsigned NumInElts = InVT.getVectorNumElements();
2472 unsigned NumOperands = N->getNumOperands();
2474 bool InputWidened = false; // Indicates we need to widen the input.
2475 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2476 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2477 // Add undef vectors to widen to correct length.
2478 unsigned NumConcat = WidenVT.getVectorNumElements() /
2479 InVT.getVectorNumElements();
2480 SDValue UndefVal = DAG.getUNDEF(InVT);
2481 SmallVector<SDValue, 16> Ops(NumConcat);
2482 for (unsigned i=0; i < NumOperands; ++i)
2483 Ops[i] = N->getOperand(i);
2484 for (unsigned i = NumOperands; i != NumConcat; ++i)
2486 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2489 InputWidened = true;
2490 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2491 // The inputs and the result are widen to the same value.
2493 for (i=1; i < NumOperands; ++i)
2494 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
2497 if (i == NumOperands)
2498 // Everything but the first operand is an UNDEF so just return the
2499 // widened first operand.
2500 return GetWidenedVector(N->getOperand(0));
2502 if (NumOperands == 2) {
2503 // Replace concat of two operands with a shuffle.
2504 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2505 for (unsigned i = 0; i < NumInElts; ++i) {
2507 MaskOps[i + NumInElts] = i + WidenNumElts;
2509 return DAG.getVectorShuffle(WidenVT, dl,
2510 GetWidenedVector(N->getOperand(0)),
2511 GetWidenedVector(N->getOperand(1)),
2517 // Fall back to use extracts and build vector.
2518 EVT EltVT = WidenVT.getVectorElementType();
2519 SmallVector<SDValue, 16> Ops(WidenNumElts);
2521 for (unsigned i=0; i < NumOperands; ++i) {
2522 SDValue InOp = N->getOperand(i);
2524 InOp = GetWidenedVector(InOp);
2525 for (unsigned j=0; j < NumInElts; ++j)
2526 Ops[Idx++] = DAG.getNode(
2527 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2528 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2530 SDValue UndefVal = DAG.getUNDEF(EltVT);
2531 for (; Idx < WidenNumElts; ++Idx)
2532 Ops[Idx] = UndefVal;
2533 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2536 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2538 SDValue InOp = N->getOperand(0);
2539 SDValue RndOp = N->getOperand(3);
2540 SDValue SatOp = N->getOperand(4);
2542 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2543 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2545 EVT InVT = InOp.getValueType();
2546 EVT InEltVT = InVT.getVectorElementType();
2547 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2549 SDValue DTyOp = DAG.getValueType(WidenVT);
2550 SDValue STyOp = DAG.getValueType(InWidenVT);
2551 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2553 unsigned InVTNumElts = InVT.getVectorNumElements();
2554 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2555 InOp = GetWidenedVector(InOp);
2556 InVT = InOp.getValueType();
2557 InVTNumElts = InVT.getVectorNumElements();
2558 if (InVTNumElts == WidenNumElts)
2559 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2563 if (TLI.isTypeLegal(InWidenVT)) {
2564 // Because the result and the input are different vector types, widening
2565 // the result could create a legal type but widening the input might make
2566 // it an illegal type that might lead to repeatedly splitting the input
2567 // and then widening it. To avoid this, we widen the input only if
2568 // it results in a legal type.
2569 if (WidenNumElts % InVTNumElts == 0) {
2570 // Widen the input and call convert on the widened input vector.
2571 unsigned NumConcat = WidenNumElts/InVTNumElts;
2572 SmallVector<SDValue, 16> Ops(NumConcat);
2574 SDValue UndefVal = DAG.getUNDEF(InVT);
2575 for (unsigned i = 1; i != NumConcat; ++i)
2578 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2579 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2583 if (InVTNumElts % WidenNumElts == 0) {
2584 // Extract the input and convert the shorten input vector.
2586 ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2587 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2588 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2593 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2594 SmallVector<SDValue, 16> Ops(WidenNumElts);
2595 EVT EltVT = WidenVT.getVectorElementType();
2596 DTyOp = DAG.getValueType(EltVT);
2597 STyOp = DAG.getValueType(InEltVT);
2599 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2601 for (i=0; i < MinElts; ++i) {
2602 SDValue ExtVal = DAG.getNode(
2603 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2604 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2605 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2609 SDValue UndefVal = DAG.getUNDEF(EltVT);
2610 for (; i < WidenNumElts; ++i)
2613 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2616 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2617 EVT VT = N->getValueType(0);
2618 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2619 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2620 SDValue InOp = N->getOperand(0);
2621 SDValue Idx = N->getOperand(1);
2624 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2625 InOp = GetWidenedVector(InOp);
2627 EVT InVT = InOp.getValueType();
2629 // Check if we can just return the input vector after widening.
2630 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2631 if (IdxVal == 0 && InVT == WidenVT)
2634 // Check if we can extract from the vector.
2635 unsigned InNumElts = InVT.getVectorNumElements();
2636 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2637 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2639 // We could try widening the input to the right length but for now, extract
2640 // the original elements, fill the rest with undefs and build a vector.
2641 SmallVector<SDValue, 16> Ops(WidenNumElts);
2642 EVT EltVT = VT.getVectorElementType();
2643 unsigned NumElts = VT.getVectorNumElements();
2645 for (i=0; i < NumElts; ++i)
2647 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2648 DAG.getConstant(IdxVal + i, dl,
2649 TLI.getVectorIdxTy(DAG.getDataLayout())));
2651 SDValue UndefVal = DAG.getUNDEF(EltVT);
2652 for (; i < WidenNumElts; ++i)
2654 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2657 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2658 SDValue InOp = GetWidenedVector(N->getOperand(0));
2659 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2660 InOp.getValueType(), InOp,
2661 N->getOperand(1), N->getOperand(2));
2664 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2665 LoadSDNode *LD = cast<LoadSDNode>(N);
2666 ISD::LoadExtType ExtType = LD->getExtensionType();
2669 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2670 if (ExtType != ISD::NON_EXTLOAD)
2671 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2673 Result = GenWidenVectorLoads(LdChain, LD);
2675 // If we generate a single load, we can use that for the chain. Otherwise,
2676 // build a factor node to remember the multiple loads are independent and
2679 if (LdChain.size() == 1)
2680 NewChain = LdChain[0];
2682 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2684 // Modified the chain - switch anything that used the old chain to use
2686 ReplaceValueWith(SDValue(N, 1), NewChain);
2691 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2693 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2694 SDValue Mask = N->getMask();
2695 EVT MaskVT = Mask.getValueType();
2696 SDValue Src0 = GetWidenedVector(N->getSrc0());
2697 ISD::LoadExtType ExtType = N->getExtensionType();
2700 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2701 Mask = GetWidenedVector(Mask);
2703 EVT BoolVT = getSetCCResultType(WidenVT);
2705 // We can't use ModifyToType() because we should fill the mask with
2707 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2708 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2710 unsigned NumConcat = WidenNumElts / MaskNumElts;
2711 SmallVector<SDValue, 16> Ops(NumConcat);
2712 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
2714 for (unsigned i = 1; i != NumConcat; ++i)
2717 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2720 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2721 Mask, Src0, N->getMemoryVT(),
2722 N->getMemOperand(), ExtType);
2723 // Legalized the chain result - switch anything that used the old chain to
2725 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2729 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2730 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2731 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2732 WidenVT, N->getOperand(0));
2735 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2736 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2737 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2739 SDValue Cond1 = N->getOperand(0);
2740 EVT CondVT = Cond1.getValueType();
2741 if (CondVT.isVector()) {
2742 EVT CondEltVT = CondVT.getVectorElementType();
2743 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2744 CondEltVT, WidenNumElts);
2745 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2746 Cond1 = GetWidenedVector(Cond1);
2748 // If we have to split the condition there is no point in widening the
2749 // select. This would result in an cycle of widening the select ->
2750 // widening the condition operand -> splitting the condition operand ->
2751 // splitting the select -> widening the select. Instead split this select
2752 // further and widen the resulting type.
2753 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2754 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2755 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2759 if (Cond1.getValueType() != CondWidenVT)
2760 Cond1 = ModifyToType(Cond1, CondWidenVT);
2763 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2764 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2765 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2766 return DAG.getNode(N->getOpcode(), SDLoc(N),
2767 WidenVT, Cond1, InOp1, InOp2);
2770 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2771 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2772 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2773 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2774 InOp1.getValueType(), N->getOperand(0),
2775 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2778 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2779 assert(N->getValueType(0).isVector() ==
2780 N->getOperand(0).getValueType().isVector() &&
2781 "Scalar/Vector type mismatch");
2782 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2784 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2785 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2786 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2787 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2788 InOp1, InOp2, N->getOperand(2));
2791 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2792 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2793 return DAG.getUNDEF(WidenVT);
2796 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2797 EVT VT = N->getValueType(0);
2800 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2801 unsigned NumElts = VT.getVectorNumElements();
2802 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2804 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2805 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2807 // Adjust mask based on new input vector length.
2808 SmallVector<int, 16> NewMask;
2809 for (unsigned i = 0; i != NumElts; ++i) {
2810 int Idx = N->getMaskElt(i);
2811 if (Idx < (int)NumElts)
2812 NewMask.push_back(Idx);
2814 NewMask.push_back(Idx - NumElts + WidenNumElts);
2816 for (unsigned i = NumElts; i != WidenNumElts; ++i)
2817 NewMask.push_back(-1);
2818 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2821 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2822 assert(N->getValueType(0).isVector() &&
2823 N->getOperand(0).getValueType().isVector() &&
2824 "Operands must be vectors");
2825 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2826 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2828 SDValue InOp1 = N->getOperand(0);
2829 EVT InVT = InOp1.getValueType();
2830 assert(InVT.isVector() && "can not widen non-vector type");
2831 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2832 InVT.getVectorElementType(), WidenNumElts);
2834 // The input and output types often differ here, and it could be that while
2835 // we'd prefer to widen the result type, the input operands have been split.
2836 // In this case, we also need to split the result of this node as well.
2837 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
2838 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
2839 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
2843 InOp1 = GetWidenedVector(InOp1);
2844 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2846 // Assume that the input and output will be widen appropriately. If not,
2847 // we will have to unroll it at some point.
2848 assert(InOp1.getValueType() == WidenInVT &&
2849 InOp2.getValueType() == WidenInVT &&
2850 "Input not widened to expected type!");
2852 return DAG.getNode(ISD::SETCC, SDLoc(N),
2853 WidenVT, InOp1, InOp2, N->getOperand(2));
2857 //===----------------------------------------------------------------------===//
2858 // Widen Vector Operand
2859 //===----------------------------------------------------------------------===//
2860 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
2861 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
2864 SDValue Res = SDValue();
2866 // See if the target wants to custom widen this node.
2867 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2870 switch (N->getOpcode()) {
2873 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
2877 llvm_unreachable("Do not know how to widen this operator's operand!");
2879 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2880 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2881 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2882 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2883 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2884 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
2885 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2886 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
2888 case ISD::ANY_EXTEND:
2889 case ISD::SIGN_EXTEND:
2890 case ISD::ZERO_EXTEND:
2891 Res = WidenVecOp_EXTEND(N);
2894 case ISD::FP_EXTEND:
2895 case ISD::FP_TO_SINT:
2896 case ISD::FP_TO_UINT:
2897 case ISD::SINT_TO_FP:
2898 case ISD::UINT_TO_FP:
2900 Res = WidenVecOp_Convert(N);
2904 // If Res is null, the sub-method took care of registering the result.
2905 if (!Res.getNode()) return false;
2907 // If the result is N, the sub-method updated N in place. Tell the legalizer
2909 if (Res.getNode() == N)
2913 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2914 "Invalid operand expansion");
2916 ReplaceValueWith(SDValue(N, 0), Res);
2920 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
2922 EVT VT = N->getValueType(0);
2924 SDValue InOp = N->getOperand(0);
2925 // If some legalization strategy other than widening is used on the operand,
2926 // we can't safely assume that just extending the low lanes is the correct
2928 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
2929 return WidenVecOp_Convert(N);
2930 InOp = GetWidenedVector(InOp);
2931 assert(VT.getVectorNumElements() <
2932 InOp.getValueType().getVectorNumElements() &&
2933 "Input wasn't widened!");
2935 // We may need to further widen the operand until it has the same total
2936 // vector size as the result.
2937 EVT InVT = InOp.getValueType();
2938 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
2939 EVT InEltVT = InVT.getVectorElementType();
2940 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
2941 EVT FixedVT = (MVT::SimpleValueType)i;
2942 EVT FixedEltVT = FixedVT.getVectorElementType();
2943 if (TLI.isTypeLegal(FixedVT) &&
2944 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
2945 FixedEltVT == InEltVT) {
2946 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
2947 "Not enough elements in the fixed type for the operand!");
2948 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
2949 "We can't have the same type as we started with!");
2950 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
2952 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
2953 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2956 ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
2957 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2961 InVT = InOp.getValueType();
2962 if (InVT.getSizeInBits() != VT.getSizeInBits())
2963 // We couldn't find a legal vector type that was a widening of the input
2964 // and could be extended in-register to the result type, so we have to
2966 return WidenVecOp_Convert(N);
2969 // Use special DAG nodes to represent the operation of extending the
2971 switch (N->getOpcode()) {
2973 llvm_unreachable("Extend legalization on on extend operation!");
2974 case ISD::ANY_EXTEND:
2975 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
2976 case ISD::SIGN_EXTEND:
2977 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
2978 case ISD::ZERO_EXTEND:
2979 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
2983 SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
2984 // The result (and first input) is legal, but the second input is illegal.
2985 // We can't do much to fix that, so just unroll and let the extracts off of
2986 // the second input be widened as needed later.
2987 return DAG.UnrollVectorOp(N);
2990 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2991 // Since the result is legal and the input is illegal, it is unlikely
2992 // that we can fix the input to a legal type so unroll the convert
2993 // into some scalar code and create a nasty build vector.
2994 EVT VT = N->getValueType(0);
2995 EVT EltVT = VT.getVectorElementType();
2997 unsigned NumElts = VT.getVectorNumElements();
2998 SDValue InOp = N->getOperand(0);
2999 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3000 InOp = GetWidenedVector(InOp);
3001 EVT InVT = InOp.getValueType();
3002 EVT InEltVT = InVT.getVectorElementType();
3004 unsigned Opcode = N->getOpcode();
3005 SmallVector<SDValue, 16> Ops(NumElts);
3006 for (unsigned i=0; i < NumElts; ++i)
3007 Ops[i] = DAG.getNode(
3010 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
3011 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3013 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3016 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
3017 EVT VT = N->getValueType(0);
3018 SDValue InOp = GetWidenedVector(N->getOperand(0));
3019 EVT InWidenVT = InOp.getValueType();
3022 // Check if we can convert between two legal vector types and extract.
3023 unsigned InWidenSize = InWidenVT.getSizeInBits();
3024 unsigned Size = VT.getSizeInBits();
3025 // x86mmx is not an acceptable vector element type, so don't try.
3026 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
3027 unsigned NewNumElts = InWidenSize / Size;
3028 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
3029 if (TLI.isTypeLegal(NewVT)) {
3030 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
3032 ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
3033 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3037 return CreateStackStoreLoad(InOp, VT);
3040 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
3041 // If the input vector is not legal, it is likely that we will not find a
3042 // legal vector of the same size. Replace the concatenate vector with a
3043 // nasty build vector.
3044 EVT VT = N->getValueType(0);
3045 EVT EltVT = VT.getVectorElementType();
3047 unsigned NumElts = VT.getVectorNumElements();
3048 SmallVector<SDValue, 16> Ops(NumElts);
3050 EVT InVT = N->getOperand(0).getValueType();
3051 unsigned NumInElts = InVT.getVectorNumElements();
3054 unsigned NumOperands = N->getNumOperands();
3055 for (unsigned i=0; i < NumOperands; ++i) {
3056 SDValue InOp = N->getOperand(i);
3057 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3058 InOp = GetWidenedVector(InOp);
3059 for (unsigned j=0; j < NumInElts; ++j)
3060 Ops[Idx++] = DAG.getNode(
3061 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3062 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3064 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3067 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
3068 SDValue InOp = GetWidenedVector(N->getOperand(0));
3069 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
3070 N->getValueType(0), InOp, N->getOperand(1));
3073 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3074 SDValue InOp = GetWidenedVector(N->getOperand(0));
3075 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
3076 N->getValueType(0), InOp, N->getOperand(1));
3079 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
3080 // We have to widen the value but we want only to store the original
3082 StoreSDNode *ST = cast<StoreSDNode>(N);
3084 SmallVector<SDValue, 16> StChain;
3085 if (ST->isTruncatingStore())
3086 GenWidenVectorTruncStores(StChain, ST);
3088 GenWidenVectorStores(StChain, ST);
3090 if (StChain.size() == 1)
3093 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3096 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3097 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3098 SDValue Mask = MST->getMask();
3099 EVT MaskVT = Mask.getValueType();
3100 SDValue StVal = MST->getValue();
3102 SDValue WideVal = GetWidenedVector(StVal);
3105 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
3106 Mask = GetWidenedVector(Mask);
3108 // The mask should be widened as well
3109 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
3110 // We can't use ModifyToType() because we should fill the mask with
3112 unsigned WidenNumElts = BoolVT.getVectorNumElements();
3113 unsigned MaskNumElts = MaskVT.getVectorNumElements();
3115 unsigned NumConcat = WidenNumElts / MaskNumElts;
3116 SmallVector<SDValue, 16> Ops(NumConcat);
3117 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
3119 for (unsigned i = 1; i != NumConcat; ++i)
3122 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
3124 assert(Mask.getValueType().getVectorNumElements() ==
3125 WideVal.getValueType().getVectorNumElements() &&
3126 "Mask and data vectors should have the same number of elements");
3127 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
3128 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3132 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3133 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3134 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3137 // WARNING: In this code we widen the compare instruction with garbage.
3138 // This garbage may contain denormal floats which may be slow. Is this a real
3139 // concern ? Should we zero the unused lanes if this is a float compare ?
3141 // Get a new SETCC node to compare the newly widened operands.
3142 // Only some of the compared elements are legal.
3143 EVT SVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
3144 InOp0.getValueType());
3145 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3146 SVT, InOp0, InOp1, N->getOperand(2));
3148 // Extract the needed results from the result vector.
3149 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3150 SVT.getVectorElementType(),
3151 N->getValueType(0).getVectorNumElements());
3152 SDValue CC = DAG.getNode(
3153 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
3154 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3156 return PromoteTargetBoolean(CC, N->getValueType(0));
3160 //===----------------------------------------------------------------------===//
3161 // Vector Widening Utilities
3162 //===----------------------------------------------------------------------===//
3164 // Utility function to find the type to chop up a widen vector for load/store
3165 // TLI: Target lowering used to determine legal types.
3166 // Width: Width left need to load/store.
3167 // WidenVT: The widen vector type to load to/store from
3168 // Align: If 0, don't allow use of a wider type
3169 // WidenEx: If Align is not 0, the amount additional we can load/store from.
3171 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
3172 unsigned Width, EVT WidenVT,
3173 unsigned Align = 0, unsigned WidenEx = 0) {
3174 EVT WidenEltVT = WidenVT.getVectorElementType();
3175 unsigned WidenWidth = WidenVT.getSizeInBits();
3176 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
3177 unsigned AlignInBits = Align*8;
3179 // If we have one element to load/store, return it.
3180 EVT RetVT = WidenEltVT;
3181 if (Width == WidenEltWidth)
3184 // See if there is larger legal integer than the element type to load/store
3186 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
3187 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
3188 EVT MemVT((MVT::SimpleValueType) VT);
3189 unsigned MemVTWidth = MemVT.getSizeInBits();
3190 if (MemVT.getSizeInBits() <= WidenEltWidth)
3192 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
3193 if ((Action == TargetLowering::TypeLegal ||
3194 Action == TargetLowering::TypePromoteInteger) &&
3195 (WidenWidth % MemVTWidth) == 0 &&
3196 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3197 (MemVTWidth <= Width ||
3198 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3204 // See if there is a larger vector type to load/store that has the same vector
3205 // element type and is evenly divisible with the WidenVT.
3206 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
3207 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
3208 EVT MemVT = (MVT::SimpleValueType) VT;
3209 unsigned MemVTWidth = MemVT.getSizeInBits();
3210 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
3211 (WidenWidth % MemVTWidth) == 0 &&
3212 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3213 (MemVTWidth <= Width ||
3214 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3215 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3223 // Builds a vector type from scalar loads
3224 // VecTy: Resulting Vector type
3225 // LDOps: Load operators to build a vector type
3226 // [Start,End) the list of loads to use.
3227 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
3228 SmallVectorImpl<SDValue> &LdOps,
3229 unsigned Start, unsigned End) {
3230 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3231 SDLoc dl(LdOps[Start]);
3232 EVT LdTy = LdOps[Start].getValueType();
3233 unsigned Width = VecTy.getSizeInBits();
3234 unsigned NumElts = Width / LdTy.getSizeInBits();
3235 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
3238 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
3240 for (unsigned i = Start + 1; i != End; ++i) {
3241 EVT NewLdTy = LdOps[i].getValueType();
3242 if (NewLdTy != LdTy) {
3243 NumElts = Width / NewLdTy.getSizeInBits();
3244 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
3245 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
3246 // Readjust position and vector position based on new load type
3247 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
3250 VecOp = DAG.getNode(
3251 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
3252 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3254 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
3257 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
3259 // The strategy assumes that we can efficiently load powers of two widths.
3260 // The routines chops the vector into the largest vector loads with the same
3261 // element type or scalar loads and then recombines it to the widen vector
3263 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3264 unsigned WidenWidth = WidenVT.getSizeInBits();
3265 EVT LdVT = LD->getMemoryVT();
3267 assert(LdVT.isVector() && WidenVT.isVector());
3268 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
3271 SDValue Chain = LD->getChain();
3272 SDValue BasePtr = LD->getBasePtr();
3273 unsigned Align = LD->getAlignment();
3274 bool isVolatile = LD->isVolatile();
3275 bool isNonTemporal = LD->isNonTemporal();
3276 bool isInvariant = LD->isInvariant();
3277 AAMDNodes AAInfo = LD->getAAInfo();
3279 int LdWidth = LdVT.getSizeInBits();
3280 int WidthDiff = WidenWidth - LdWidth; // Difference
3281 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
3283 // Find the vector type that can load from.
3284 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3285 int NewVTWidth = NewVT.getSizeInBits();
3286 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3287 isVolatile, isNonTemporal, isInvariant, Align,
3289 LdChain.push_back(LdOp.getValue(1));
3291 // Check if we can load the element with one instruction
3292 if (LdWidth <= NewVTWidth) {
3293 if (!NewVT.isVector()) {
3294 unsigned NumElts = WidenWidth / NewVTWidth;
3295 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3296 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3297 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3299 if (NewVT == WidenVT)
3302 assert(WidenWidth % NewVTWidth == 0);
3303 unsigned NumConcat = WidenWidth / NewVTWidth;
3304 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3305 SDValue UndefVal = DAG.getUNDEF(NewVT);
3306 ConcatOps[0] = LdOp;
3307 for (unsigned i = 1; i != NumConcat; ++i)
3308 ConcatOps[i] = UndefVal;
3309 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3312 // Load vector by using multiple loads from largest vector to scalar
3313 SmallVector<SDValue, 16> LdOps;
3314 LdOps.push_back(LdOp);
3316 LdWidth -= NewVTWidth;
3317 unsigned Offset = 0;
3319 while (LdWidth > 0) {
3320 unsigned Increment = NewVTWidth / 8;
3321 Offset += Increment;
3322 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3323 DAG.getConstant(Increment, dl, BasePtr.getValueType()));
3326 if (LdWidth < NewVTWidth) {
3327 // Our current type we are using is too large, find a better size
3328 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3329 NewVTWidth = NewVT.getSizeInBits();
3330 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3331 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3332 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3334 LdChain.push_back(L.getValue(1));
3335 if (L->getValueType(0).isVector()) {
3336 SmallVector<SDValue, 16> Loads;
3338 unsigned size = L->getValueSizeInBits(0);
3339 while (size < LdOp->getValueSizeInBits(0)) {
3340 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3341 size += L->getValueSizeInBits(0);
3343 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3346 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3347 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3348 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3350 LdChain.push_back(L.getValue(1));
3356 LdWidth -= NewVTWidth;
3359 // Build the vector from the loads operations
3360 unsigned End = LdOps.size();
3361 if (!LdOps[0].getValueType().isVector())
3362 // All the loads are scalar loads.
3363 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3365 // If the load contains vectors, build the vector using concat vector.
3366 // All of the vectors used to loads are power of 2 and the scalars load
3367 // can be combined to make a power of 2 vector.
3368 SmallVector<SDValue, 16> ConcatOps(End);
3371 EVT LdTy = LdOps[i].getValueType();
3372 // First combine the scalar loads to a vector
3373 if (!LdTy.isVector()) {
3374 for (--i; i >= 0; --i) {
3375 LdTy = LdOps[i].getValueType();
3376 if (LdTy.isVector())
3379 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
3381 ConcatOps[--Idx] = LdOps[i];
3382 for (--i; i >= 0; --i) {
3383 EVT NewLdTy = LdOps[i].getValueType();
3384 if (NewLdTy != LdTy) {
3385 // Create a larger vector
3386 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3387 makeArrayRef(&ConcatOps[Idx], End - Idx));
3391 ConcatOps[--Idx] = LdOps[i];
3394 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
3395 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3396 makeArrayRef(&ConcatOps[Idx], End - Idx));
3398 // We need to fill the rest with undefs to build the vector
3399 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3400 SmallVector<SDValue, 16> WidenOps(NumOps);
3401 SDValue UndefVal = DAG.getUNDEF(LdTy);
3404 for (; i != End-Idx; ++i)
3405 WidenOps[i] = ConcatOps[Idx+i];
3406 for (; i != NumOps; ++i)
3407 WidenOps[i] = UndefVal;
3409 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3413 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3415 ISD::LoadExtType ExtType) {
3416 // For extension loads, it may not be more efficient to chop up the vector
3417 // and then extended it. Instead, we unroll the load and build a new vector.
3418 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3419 EVT LdVT = LD->getMemoryVT();
3421 assert(LdVT.isVector() && WidenVT.isVector());
3424 SDValue Chain = LD->getChain();
3425 SDValue BasePtr = LD->getBasePtr();
3426 unsigned Align = LD->getAlignment();
3427 bool isVolatile = LD->isVolatile();
3428 bool isNonTemporal = LD->isNonTemporal();
3429 bool isInvariant = LD->isInvariant();
3430 AAMDNodes AAInfo = LD->getAAInfo();
3432 EVT EltVT = WidenVT.getVectorElementType();
3433 EVT LdEltVT = LdVT.getVectorElementType();
3434 unsigned NumElts = LdVT.getVectorNumElements();
3436 // Load each element and widen
3437 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3438 SmallVector<SDValue, 16> Ops(WidenNumElts);
3439 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3440 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
3441 LD->getPointerInfo(),
3442 LdEltVT, isVolatile, isNonTemporal, isInvariant,
3444 LdChain.push_back(Ops[0].getValue(1));
3445 unsigned i = 0, Offset = Increment;
3446 for (i=1; i < NumElts; ++i, Offset += Increment) {
3447 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3449 DAG.getConstant(Offset, dl,
3450 BasePtr.getValueType()));
3451 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3452 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3453 isVolatile, isNonTemporal, isInvariant, Align,
3455 LdChain.push_back(Ops[i].getValue(1));
3458 // Fill the rest with undefs
3459 SDValue UndefVal = DAG.getUNDEF(EltVT);
3460 for (; i != WidenNumElts; ++i)
3463 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3467 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3469 // The strategy assumes that we can efficiently store powers of two widths.
3470 // The routines chops the vector into the largest vector stores with the same
3471 // element type or scalar stores.
3472 SDValue Chain = ST->getChain();
3473 SDValue BasePtr = ST->getBasePtr();
3474 unsigned Align = ST->getAlignment();
3475 bool isVolatile = ST->isVolatile();
3476 bool isNonTemporal = ST->isNonTemporal();
3477 AAMDNodes AAInfo = ST->getAAInfo();
3478 SDValue ValOp = GetWidenedVector(ST->getValue());
3481 EVT StVT = ST->getMemoryVT();
3482 unsigned StWidth = StVT.getSizeInBits();
3483 EVT ValVT = ValOp.getValueType();
3484 unsigned ValWidth = ValVT.getSizeInBits();
3485 EVT ValEltVT = ValVT.getVectorElementType();
3486 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3487 assert(StVT.getVectorElementType() == ValEltVT);
3489 int Idx = 0; // current index to store
3490 unsigned Offset = 0; // offset from base to store
3491 while (StWidth != 0) {
3492 // Find the largest vector type we can store with
3493 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3494 unsigned NewVTWidth = NewVT.getSizeInBits();
3495 unsigned Increment = NewVTWidth / 8;
3496 if (NewVT.isVector()) {
3497 unsigned NumVTElts = NewVT.getVectorNumElements();
3499 SDValue EOp = DAG.getNode(
3500 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3501 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3502 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3503 ST->getPointerInfo().getWithOffset(Offset),
3504 isVolatile, isNonTemporal,
3505 MinAlign(Align, Offset), AAInfo));
3506 StWidth -= NewVTWidth;
3507 Offset += Increment;
3509 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3510 DAG.getConstant(Increment, dl,
3511 BasePtr.getValueType()));
3512 } while (StWidth != 0 && StWidth >= NewVTWidth);
3514 // Cast the vector to the scalar type we can store
3515 unsigned NumElts = ValWidth / NewVTWidth;
3516 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3517 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3518 // Readjust index position based on new vector type
3519 Idx = Idx * ValEltWidth / NewVTWidth;
3521 SDValue EOp = DAG.getNode(
3522 ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3523 DAG.getConstant(Idx++, dl,
3524 TLI.getVectorIdxTy(DAG.getDataLayout())));
3525 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3526 ST->getPointerInfo().getWithOffset(Offset),
3527 isVolatile, isNonTemporal,
3528 MinAlign(Align, Offset), AAInfo));
3529 StWidth -= NewVTWidth;
3530 Offset += Increment;
3531 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3532 DAG.getConstant(Increment, dl,
3533 BasePtr.getValueType()));
3534 } while (StWidth != 0 && StWidth >= NewVTWidth);
3535 // Restore index back to be relative to the original widen element type
3536 Idx = Idx * NewVTWidth / ValEltWidth;
3542 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3544 // For extension loads, it may not be more efficient to truncate the vector
3545 // and then store it. Instead, we extract each element and then store it.
3546 SDValue Chain = ST->getChain();
3547 SDValue BasePtr = ST->getBasePtr();
3548 unsigned Align = ST->getAlignment();
3549 bool isVolatile = ST->isVolatile();
3550 bool isNonTemporal = ST->isNonTemporal();
3551 AAMDNodes AAInfo = ST->getAAInfo();
3552 SDValue ValOp = GetWidenedVector(ST->getValue());
3555 EVT StVT = ST->getMemoryVT();
3556 EVT ValVT = ValOp.getValueType();
3558 // It must be true that we the widen vector type is bigger than where
3559 // we need to store.
3560 assert(StVT.isVector() && ValOp.getValueType().isVector());
3561 assert(StVT.bitsLT(ValOp.getValueType()));
3563 // For truncating stores, we can not play the tricks of chopping legal
3564 // vector types and bit cast it to the right type. Instead, we unroll
3566 EVT StEltVT = StVT.getVectorElementType();
3567 EVT ValEltVT = ValVT.getVectorElementType();
3568 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3569 unsigned NumElts = StVT.getVectorNumElements();
3570 SDValue EOp = DAG.getNode(
3571 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3572 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3573 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3574 ST->getPointerInfo(), StEltVT,
3575 isVolatile, isNonTemporal, Align,
3577 unsigned Offset = Increment;
3578 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3579 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3581 DAG.getConstant(Offset, dl,
3582 BasePtr.getValueType()));
3583 SDValue EOp = DAG.getNode(
3584 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3585 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3586 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
3587 ST->getPointerInfo().getWithOffset(Offset),
3588 StEltVT, isVolatile, isNonTemporal,
3589 MinAlign(Align, Offset), AAInfo));
3593 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3594 /// input vector must have the same element type as NVT.
3595 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
3596 // Note that InOp might have been widened so it might already have
3597 // the right width or it might need be narrowed.
3598 EVT InVT = InOp.getValueType();
3599 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3600 "input and widen element type must match");
3603 // Check if InOp already has the right width.
3607 unsigned InNumElts = InVT.getVectorNumElements();
3608 unsigned WidenNumElts = NVT.getVectorNumElements();
3609 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3610 unsigned NumConcat = WidenNumElts / InNumElts;
3611 SmallVector<SDValue, 16> Ops(NumConcat);
3612 SDValue UndefVal = DAG.getUNDEF(InVT);
3614 for (unsigned i = 1; i != NumConcat; ++i)
3617 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3620 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3622 ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3623 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3625 // Fall back to extract and build.
3626 SmallVector<SDValue, 16> Ops(WidenNumElts);
3627 EVT EltVT = NVT.getVectorElementType();
3628 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3630 for (Idx = 0; Idx < MinNumElts; ++Idx)
3631 Ops[Idx] = DAG.getNode(
3632 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3633 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3635 SDValue UndefVal = DAG.getUNDEF(EltVT);
3636 for ( ; Idx < WidenNumElts; ++Idx)
3637 Ops[Idx] = UndefVal;
3638 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);