1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in multiple vectors of a smaller type. For example,
19 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/Target/TargetData.h"
27 //===----------------------------------------------------------------------===//
28 // Result Vector Scalarization: <1 x ty> -> ty.
29 //===----------------------------------------------------------------------===//
31 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
32 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
34 SDValue R = SDValue();
36 switch (N->getOpcode()) {
39 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
40 N->dump(&DAG); cerr << "\n";
42 assert(0 && "Do not know how to scalarize the result of this operator!");
45 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
46 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
47 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
48 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
49 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
50 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
51 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
52 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
53 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
54 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
55 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
56 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
57 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
76 case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break;
93 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
97 case ISD::SRL: R = ScalarizeVecRes_ShiftOp(N); break;
100 // If R is null, the sub-method took care of registering the result.
102 SetScalarizedVector(SDValue(N, ResNo), R);
105 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
106 SDValue LHS = GetScalarizedVector(N->getOperand(0));
107 SDValue RHS = GetScalarizedVector(N->getOperand(1));
108 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
111 SDValue DAGTypeLegalizer::ScalarizeVecRes_ShiftOp(SDNode *N) {
112 SDValue LHS = GetScalarizedVector(N->getOperand(0));
113 SDValue ShiftAmt = GetScalarizedVector(N->getOperand(1));
114 if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType()))
115 ShiftAmt = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt);
116 else if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType()))
117 ShiftAmt = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
119 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, ShiftAmt);
122 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
123 MVT NewVT = N->getValueType(0).getVectorElementType();
124 return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
127 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
128 MVT NewVT = N->getValueType(0).getVectorElementType();
129 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
130 return DAG.getConvertRndSat(NewVT, Op0, DAG.getValueType(NewVT),
131 DAG.getValueType(Op0.getValueType()),
134 cast<CvtRndSatSDNode>(N)->getCvtCode());
137 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
138 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
139 N->getValueType(0).getVectorElementType(),
140 N->getOperand(0), N->getOperand(1));
143 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
144 SDValue Op = GetScalarizedVector(N->getOperand(0));
145 return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
148 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
149 // The value to insert may have a wider type than the vector element type,
150 // so be sure to truncate it to the element type if necessary.
151 SDValue Op = N->getOperand(1);
152 MVT EltVT = N->getValueType(0).getVectorElementType();
153 if (Op.getValueType() != EltVT)
154 // FIXME: Can this happen for floating point types?
155 Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
159 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
160 assert(N->isUnindexed() && "Indexed vector load?");
162 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getExtensionType(),
163 N->getValueType(0).getVectorElementType(),
164 N->getChain(), N->getBasePtr(),
165 DAG.getNode(ISD::UNDEF,
166 N->getBasePtr().getValueType()),
167 N->getSrcValue(), N->getSrcValueOffset(),
168 N->getMemoryVT().getVectorElementType(),
169 N->isVolatile(), N->getAlignment());
171 // Legalized the chain result - switch anything that used the old chain to
173 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
177 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
178 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
179 MVT DestVT = N->getValueType(0).getVectorElementType();
180 SDValue Op = GetScalarizedVector(N->getOperand(0));
181 return DAG.getNode(N->getOpcode(), DestVT, Op);
184 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
185 return N->getOperand(0);
188 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
189 SDValue LHS = GetScalarizedVector(N->getOperand(1));
190 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
191 GetScalarizedVector(N->getOperand(2)));
194 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
195 SDValue LHS = GetScalarizedVector(N->getOperand(2));
196 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(),
197 N->getOperand(0), N->getOperand(1),
198 LHS, GetScalarizedVector(N->getOperand(3)),
202 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
203 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
206 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
207 // Figure out if the scalar is the LHS or RHS and return it.
208 SDValue Arg = N->getOperand(2).getOperand(0);
209 if (Arg.getOpcode() == ISD::UNDEF)
210 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
211 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
212 return GetScalarizedVector(N->getOperand(Op));
215 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
216 SDValue LHS = GetScalarizedVector(N->getOperand(0));
217 SDValue RHS = GetScalarizedVector(N->getOperand(1));
218 MVT NVT = N->getValueType(0).getVectorElementType();
219 MVT SVT = TLI.getSetCCResultType(LHS);
221 // Turn it into a scalar SETCC.
222 SDValue Res = DAG.getNode(ISD::SETCC, SVT, LHS, RHS, N->getOperand(2));
224 // VSETCC always returns a sign-extended value, while SETCC may not. The
225 // SETCC result type may not match the vector element type. Correct these.
226 if (NVT.bitsLE(SVT)) {
227 // The SETCC result type is bigger than the vector element type.
228 // Ensure the SETCC result is sign-extended.
229 if (TLI.getBooleanContents() !=
230 TargetLowering::ZeroOrNegativeOneBooleanContent)
231 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, SVT, Res,
232 DAG.getValueType(MVT::i1));
233 // Truncate to the final type.
234 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
236 // The SETCC result type is smaller than the vector element type.
237 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
238 if (TLI.getBooleanContents() !=
239 TargetLowering::ZeroOrNegativeOneBooleanContent)
240 Res = DAG.getNode(ISD::TRUNCATE, MVT::i1, Res);
241 // Sign extend to the final type.
242 return DAG.getNode(ISD::SIGN_EXTEND, NVT, Res);
247 //===----------------------------------------------------------------------===//
248 // Operand Vector Scalarization <1 x ty> -> ty.
249 //===----------------------------------------------------------------------===//
251 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
252 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
254 SDValue Res = SDValue();
256 if (Res.getNode() == 0) {
257 switch (N->getOpcode()) {
260 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
261 N->dump(&DAG); cerr << "\n";
263 assert(0 && "Do not know how to scalarize this operator's operand!");
266 case ISD::BIT_CONVERT:
267 Res = ScalarizeVecOp_BIT_CONVERT(N); break;
269 case ISD::CONCAT_VECTORS:
270 Res = ScalarizeVecOp_CONCAT_VECTORS(N); break;
272 case ISD::EXTRACT_VECTOR_ELT:
273 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
276 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
280 // If the result is null, the sub-method took care of registering results etc.
281 if (!Res.getNode()) return false;
283 // If the result is N, the sub-method updated N in place. Tell the legalizer
285 if (Res.getNode() == N)
288 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
289 "Invalid operand expansion");
291 ReplaceValueWith(SDValue(N, 0), Res);
295 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
296 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
297 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
298 SDValue Elt = GetScalarizedVector(N->getOperand(0));
299 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
302 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
303 /// use a BUILD_VECTOR instead.
304 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
305 SmallVector<SDValue, 8> Ops(N->getNumOperands());
306 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
307 Ops[i] = GetScalarizedVector(N->getOperand(i));
308 return DAG.getNode(ISD::BUILD_VECTOR, N->getValueType(0),
309 &Ops[0], Ops.size());
312 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
313 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
315 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
316 return GetScalarizedVector(N->getOperand(0));
319 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
320 /// scalarized, it must be <1 x ty>. Just store the element.
321 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
322 assert(N->isUnindexed() && "Indexed store of one-element vector?");
323 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
325 if (N->isTruncatingStore())
326 return DAG.getTruncStore(N->getChain(),
327 GetScalarizedVector(N->getOperand(1)),
329 N->getSrcValue(), N->getSrcValueOffset(),
330 N->getMemoryVT().getVectorElementType(),
331 N->isVolatile(), N->getAlignment());
333 return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
334 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
335 N->isVolatile(), N->getAlignment());
339 //===----------------------------------------------------------------------===//
340 // Result Vector Splitting
341 //===----------------------------------------------------------------------===//
343 /// SplitVectorResult - This method is called when the specified result of the
344 /// specified node is found to need vector splitting. At this point, the node
345 /// may also have invalid operands or may have other results that need
346 /// legalization, we just know that (at least) one result needs vector
348 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
349 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
352 switch (N->getOpcode()) {
355 cerr << "SplitVectorResult #" << ResNo << ": ";
356 N->dump(&DAG); cerr << "\n";
358 assert(0 && "Do not know how to split the result of this operator!");
361 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
362 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
363 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
364 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
366 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
367 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
368 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
369 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
370 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
371 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
372 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
373 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
374 case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
375 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
376 case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
390 case ISD::FNEARBYINT:
391 case ISD::FP_TO_SINT:
392 case ISD::FP_TO_UINT:
393 case ISD::SINT_TO_FP:
395 case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break;
415 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
418 // If Lo/Hi is null, the sub-method took care of registering results etc.
420 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
423 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
425 SDValue LHSLo, LHSHi;
426 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
427 SDValue RHSLo, RHSHi;
428 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
430 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
431 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
434 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
436 // We know the result is a vector. The input may be either a vector or a
439 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
441 SDValue InOp = N->getOperand(0);
442 MVT InVT = InOp.getValueType();
444 // Handle some special cases efficiently.
445 switch (getTypeAction(InVT)) {
447 assert(false && "Unknown type action!");
451 case ScalarizeVector:
455 // A scalar to vector conversion, where the scalar needs expansion.
456 // If the vector is being split in two then we can just convert the
459 GetExpandedOp(InOp, Lo, Hi);
460 if (TLI.isBigEndian())
462 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
463 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
468 // If the input is a vector that needs to be split, convert each split
469 // piece of the input now.
470 GetSplitVector(InOp, Lo, Hi);
471 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
472 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
476 // In the general case, convert the input to an integer and split it by hand.
477 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
478 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
479 if (TLI.isBigEndian())
480 std::swap(LoIntVT, HiIntVT);
482 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
484 if (TLI.isBigEndian())
486 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
487 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
490 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
493 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
494 unsigned LoNumElts = LoVT.getVectorNumElements();
495 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
496 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
498 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
499 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
502 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
504 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
505 unsigned NumSubvectors = N->getNumOperands() / 2;
506 if (NumSubvectors == 1) {
507 Lo = N->getOperand(0);
508 Hi = N->getOperand(1);
513 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
515 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
516 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
518 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
519 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
522 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
525 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
527 GetSplitVector(N->getOperand(0), VLo, VHi);
528 SDValue DTyOpLo = DAG.getValueType(LoVT);
529 SDValue DTyOpHi = DAG.getValueType(HiVT);
530 SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
531 SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
533 SDValue RndOp = N->getOperand(3);
534 SDValue SatOp = N->getOperand(4);
535 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
537 Lo = DAG.getConvertRndSat(LoVT, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, CvtCode);
538 Hi = DAG.getConvertRndSat(HiVT, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, CvtCode);
541 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
543 SDValue Vec = N->getOperand(0);
544 SDValue Idx = N->getOperand(1);
545 MVT IdxVT = Idx.getValueType();
548 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
549 // The indices are not guaranteed to be a multiple of the new vector
550 // size unless the original vector type was split in two.
551 assert(LoVT == HiVT && "Non power-of-two vectors not supported!");
553 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, LoVT, Vec, Idx);
554 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
555 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
556 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, HiVT, Vec, Idx);
559 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
561 GetSplitVector(N->getOperand(0), Lo, Hi);
562 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
563 Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
566 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
568 SDValue Vec = N->getOperand(0);
569 SDValue Elt = N->getOperand(1);
570 SDValue Idx = N->getOperand(2);
571 GetSplitVector(Vec, Lo, Hi);
573 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
574 unsigned IdxVal = CIdx->getZExtValue();
575 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
576 if (IdxVal < LoNumElts)
577 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx);
579 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt,
580 DAG.getIntPtrConstant(IdxVal - LoNumElts));
584 // Spill the vector to the stack.
585 MVT VecVT = Vec.getValueType();
586 MVT EltVT = VecVT.getVectorElementType();
587 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
588 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
590 // Store the new element. This may be larger than the vector element type,
591 // so use a truncating store.
592 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
594 TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT());
595 Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
597 // Load the Lo part from the stack slot.
598 Lo = DAG.getLoad(Lo.getValueType(), Store, StackPtr, NULL, 0);
600 // Increment the pointer to the other part.
601 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
602 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
603 DAG.getIntPtrConstant(IncrementSize));
605 // Load the Hi part from the stack slot.
606 Hi = DAG.getLoad(Hi.getValueType(), Store, StackPtr, NULL, 0, false,
607 MinAlign(Alignment, IncrementSize));
610 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
613 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
614 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, LoVT, N->getOperand(0));
615 Hi = DAG.getNode(ISD::UNDEF, HiVT);
618 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
620 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
622 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
624 ISD::LoadExtType ExtType = LD->getExtensionType();
625 SDValue Ch = LD->getChain();
626 SDValue Ptr = LD->getBasePtr();
627 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
628 const Value *SV = LD->getSrcValue();
629 int SVOffset = LD->getSrcValueOffset();
630 MVT MemoryVT = LD->getMemoryVT();
631 unsigned Alignment = LD->getAlignment();
632 bool isVolatile = LD->isVolatile();
634 MVT LoMemVT, HiMemVT;
635 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
637 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, Ch, Ptr, Offset,
638 SV, SVOffset, LoMemVT, isVolatile, Alignment);
640 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
641 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
642 DAG.getIntPtrConstant(IncrementSize));
643 SVOffset += IncrementSize;
644 Alignment = MinAlign(Alignment, IncrementSize);
645 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, Ch, Ptr, Offset,
646 SV, SVOffset, HiMemVT, isVolatile, Alignment);
648 // Build a factor node to remember that this load is independent of the
650 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
653 // Legalized the chain result - switch anything that used the old chain to
655 ReplaceValueWith(SDValue(LD, 1), Ch);
658 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
660 // Get the dest types - they may not match the input types, e.g. int_to_fp.
662 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
665 MVT InVT = N->getOperand(0).getValueType();
666 switch (getTypeAction(InVT)) {
667 default: assert(0 && "Unexpected type action!");
669 assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
670 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
671 LoVT.getVectorNumElements());
672 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
673 DAG.getIntPtrConstant(0));
674 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
675 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
679 GetSplitVector(N->getOperand(0), Lo, Hi);
683 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
684 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
687 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
689 // The low and high parts of the original input give four input vectors.
691 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
692 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
693 MVT NewVT = Inputs[0].getValueType();
694 unsigned NewElts = NewVT.getVectorNumElements();
695 assert(NewVT == Inputs[1].getValueType() &&
696 "Non power-of-two vectors not supported!");
698 // If Lo or Hi uses elements from at most two of the four input vectors, then
699 // express it as a vector shuffle of those two inputs. Otherwise extract the
700 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
701 SDValue Mask = N->getOperand(2);
702 MVT IdxVT = Mask.getValueType().getVectorElementType();
703 SmallVector<SDValue, 16> Ops;
704 Ops.reserve(NewElts);
705 for (unsigned High = 0; High < 2; ++High) {
706 SDValue &Output = High ? Hi : Lo;
708 // Build a shuffle mask for the output, discovering on the fly which
709 // input vectors to use as shuffle operands (recorded in InputUsed).
710 // If building a suitable shuffle vector proves too hard, then bail
711 // out with useBuildVector set.
712 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
713 unsigned FirstMaskIdx = High * NewElts;
714 bool useBuildVector = false;
715 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
716 SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
718 // The mask element. This indexes into the input.
719 unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
720 -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
722 // The input vector this mask element indexes into.
723 unsigned Input = Idx / NewElts;
725 if (Input >= array_lengthof(Inputs)) {
726 // The mask element does not index into any input vector.
727 Ops.push_back(DAG.getNode(ISD::UNDEF, IdxVT));
731 // Turn the index into an offset from the start of the input vector.
732 Idx -= Input * NewElts;
734 // Find or create a shuffle vector operand to hold this input.
736 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
737 if (InputUsed[OpNo] == Input) {
738 // This input vector is already an operand.
740 } else if (InputUsed[OpNo] == -1U) {
741 // Create a new operand for this input vector.
742 InputUsed[OpNo] = Input;
747 if (OpNo >= array_lengthof(InputUsed)) {
748 // More than two input vectors used! Give up on trying to create a
749 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
750 useBuildVector = true;
754 // Add the mask index for the new shuffle vector.
755 Ops.push_back(DAG.getConstant(Idx + OpNo * NewElts, IdxVT));
758 if (useBuildVector) {
759 MVT EltVT = NewVT.getVectorElementType();
762 // Extract the input elements by hand.
763 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
764 SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
766 // The mask element. This indexes into the input.
767 unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
768 -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
770 // The input vector this mask element indexes into.
771 unsigned Input = Idx / NewElts;
773 if (Input >= array_lengthof(Inputs)) {
774 // The mask element is "undef" or indexes off the end of the input.
775 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
779 // Turn the index into an offset from the start of the input vector.
780 Idx -= Input * NewElts;
782 // Extract the vector element by hand.
783 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT,
784 Inputs[Input], DAG.getIntPtrConstant(Idx)));
787 // Construct the Lo/Hi output using a BUILD_VECTOR.
788 Output = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &Ops[0], Ops.size());
789 } else if (InputUsed[0] == -1U) {
790 // No input vectors were used! The result is undefined.
791 Output = DAG.getNode(ISD::UNDEF, NewVT);
793 // At least one input vector was used. Create a new shuffle vector.
794 SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR,
795 MVT::getVectorVT(IdxVT, Ops.size()),
796 &Ops[0], Ops.size());
797 SDValue Op0 = Inputs[InputUsed[0]];
798 // If only one input was used, use an undefined vector for the other.
799 SDValue Op1 = InputUsed[1] == -1U ?
800 DAG.getNode(ISD::UNDEF, NewVT) : Inputs[InputUsed[1]];
801 Output = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, Op0, Op1, NewMask);
808 void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
811 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
813 SDValue LL, LH, RL, RH;
814 GetSplitVector(N->getOperand(0), LL, LH);
815 GetSplitVector(N->getOperand(1), RL, RH);
817 Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2));
818 Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2));
822 //===----------------------------------------------------------------------===//
823 // Operand Vector Splitting
824 //===----------------------------------------------------------------------===//
826 /// SplitVectorOperand - This method is called when the specified operand of the
827 /// specified node is found to need vector splitting. At this point, all of the
828 /// result types of the node are known to be legal, but other operands of the
829 /// node may need legalization as well as the specified one.
830 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
831 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
832 SDValue Res = SDValue();
834 if (Res.getNode() == 0) {
835 switch (N->getOpcode()) {
838 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
839 N->dump(&DAG); cerr << "\n";
841 assert(0 && "Do not know how to split this operator's operand!");
844 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
845 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
846 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
847 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N),
849 case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break;
854 case ISD::FP_TO_SINT:
855 case ISD::FP_TO_UINT:
856 case ISD::SINT_TO_FP:
858 case ISD::UINT_TO_FP: Res = SplitVecOp_UnaryOp(N); break;
862 // If the result is null, the sub-method took care of registering results etc.
863 if (!Res.getNode()) return false;
865 // If the result is N, the sub-method updated N in place. Tell the legalizer
867 if (Res.getNode() == N)
870 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
871 "Invalid operand expansion");
873 ReplaceValueWith(SDValue(N, 0), Res);
877 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
878 // The result has a legal vector type, but the input needs splitting.
879 MVT ResVT = N->getValueType(0);
881 GetSplitVector(N->getOperand(0), Lo, Hi);
882 assert(Lo.getValueType() == Hi.getValueType() &&
883 "Returns legal non-power-of-two vector type?");
884 MVT InVT = Lo.getValueType();
886 MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
887 InVT.getVectorNumElements());
889 Lo = DAG.getNode(N->getOpcode(), OutVT, Lo);
890 Hi = DAG.getNode(N->getOpcode(), OutVT, Hi);
892 return DAG.getNode(ISD::CONCAT_VECTORS, ResVT, Lo, Hi);
895 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
896 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
897 // end up being split all the way down to individual components. Convert the
898 // split pieces into integers and reassemble.
900 GetSplitVector(N->getOperand(0), Lo, Hi);
901 Lo = BitConvertToInteger(Lo);
902 Hi = BitConvertToInteger(Hi);
904 if (TLI.isBigEndian())
907 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
908 JoinIntegers(Lo, Hi));
911 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
912 // We know that the extracted result type is legal. For now, assume the index
914 MVT SubVT = N->getValueType(0);
915 SDValue Idx = N->getOperand(1);
917 GetSplitVector(N->getOperand(0), Lo, Hi);
919 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
920 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
922 if (IdxVal < LoElts) {
923 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
924 "Extracted subvector crosses vector split!");
925 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
927 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
928 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
932 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
933 SDValue Vec = N->getOperand(0);
934 SDValue Idx = N->getOperand(1);
935 MVT VecVT = Vec.getValueType();
937 if (isa<ConstantSDNode>(Idx)) {
938 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
939 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
942 GetSplitVector(Vec, Lo, Hi);
944 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
947 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
949 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
950 DAG.getConstant(IdxVal - LoElts,
951 Idx.getValueType()));
954 // Store the vector to the stack.
955 MVT EltVT = VecVT.getVectorElementType();
956 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
957 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
959 // Load back the required element.
960 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
961 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
964 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
965 assert(N->isUnindexed() && "Indexed store of vector?");
966 assert(OpNo == 1 && "Can only split the stored value");
968 bool isTruncating = N->isTruncatingStore();
969 SDValue Ch = N->getChain();
970 SDValue Ptr = N->getBasePtr();
971 int SVOffset = N->getSrcValueOffset();
972 MVT MemoryVT = N->getMemoryVT();
973 unsigned Alignment = N->getAlignment();
974 bool isVol = N->isVolatile();
976 GetSplitVector(N->getOperand(1), Lo, Hi);
978 MVT LoMemVT, HiMemVT;
979 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
981 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
984 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
985 LoMemVT, isVol, Alignment);
987 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
990 // Increment the pointer to the other half.
991 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
992 DAG.getIntPtrConstant(IncrementSize));
995 Hi = DAG.getTruncStore(Ch, Hi, Ptr,
996 N->getSrcValue(), SVOffset+IncrementSize,
998 isVol, MinAlign(Alignment, IncrementSize));
1000 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
1001 isVol, MinAlign(Alignment, IncrementSize));
1003 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1006 SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
1007 assert(OpNo == 2 && "Shuffle source type differs from result type?");
1008 SDValue Mask = N->getOperand(2);
1009 unsigned MaskLength = Mask.getValueType().getVectorNumElements();
1010 unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
1011 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
1013 // Look for a legal vector type to place the mask values in.
1014 // Note that there may not be *any* legal vector-of-integer
1015 // type for which the element type is legal!
1016 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
1017 EltVT <= MVT::LAST_INTEGER_VALUETYPE;
1018 // Integer values types are consecutively numbered. Exploit this.
1019 EltVT = MVT::SimpleValueType(EltVT + 1)) {
1021 // Is the element type big enough to hold the values?
1022 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
1026 // Is the vector type legal?
1027 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
1028 if (!isTypeLegal(VecVT))
1032 // If the element type is not legal, find a larger legal type to use for
1033 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
1034 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
1035 // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
1036 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
1037 // Integer values types are consecutively numbered. Exploit this.
1038 OpVT = MVT::SimpleValueType(OpVT + 1)) {
1039 if (!isTypeLegal(OpVT))
1042 // Success! Rebuild the vector using the legal types.
1043 SmallVector<SDValue, 16> Ops(MaskLength);
1044 for (unsigned i = 0; i < MaskLength; ++i) {
1045 SDValue Arg = Mask.getOperand(i);
1046 if (Arg.getOpcode() == ISD::UNDEF) {
1047 Ops[i] = DAG.getNode(ISD::UNDEF, OpVT);
1049 uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1050 Ops[i] = DAG.getConstant(Idx, OpVT);
1053 return DAG.UpdateNodeOperands(SDValue(N,0),
1054 N->getOperand(0), N->getOperand(1),
1055 DAG.getNode(ISD::BUILD_VECTOR,
1056 VecVT, &Ops[0], Ops.size()));
1059 // Continuing is pointless - failure is certain.
1062 assert(false && "Failed to find an appropriate mask type!");
1063 return SDValue(N, 0);