1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
30 //===----------------------------------------------------------------------===//
31 // Result Vector Scalarization: <1 x ty> -> ty.
32 //===----------------------------------------------------------------------===//
34 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
38 SDValue R = SDValue();
40 switch (N->getOpcode()) {
43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
47 llvm_unreachable("Do not know how to scalarize the result of this operator!");
49 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
50 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
51 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
52 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
53 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
54 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
55 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
56 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
57 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
58 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
59 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
60 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
61 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
62 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
63 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
64 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
84 case ISD::SIGN_EXTEND:
85 case ISD::ZERO_EXTEND:
87 R = ScalarizeVecRes_UnaryOp(N);
109 R = ScalarizeVecRes_BinOp(N);
113 // If R is null, the sub-method took care of registering the result.
115 SetScalarizedVector(SDValue(N, ResNo), R);
118 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
119 SDValue LHS = GetScalarizedVector(N->getOperand(0));
120 SDValue RHS = GetScalarizedVector(N->getOperand(1));
121 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
122 LHS.getValueType(), LHS, RHS);
125 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
126 EVT NewVT = N->getValueType(0).getVectorElementType();
127 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
128 NewVT, N->getOperand(0));
131 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
132 EVT NewVT = N->getValueType(0).getVectorElementType();
133 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
134 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
135 Op0, DAG.getValueType(NewVT),
136 DAG.getValueType(Op0.getValueType()),
139 cast<CvtRndSatSDNode>(N)->getCvtCode());
142 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
143 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
144 N->getValueType(0).getVectorElementType(),
145 N->getOperand(0), N->getOperand(1));
148 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
149 SDValue Op = GetScalarizedVector(N->getOperand(0));
150 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
151 Op.getValueType(), Op, N->getOperand(1));
154 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
155 // The value to insert may have a wider type than the vector element type,
156 // so be sure to truncate it to the element type if necessary.
157 SDValue Op = N->getOperand(1);
158 EVT EltVT = N->getValueType(0).getVectorElementType();
159 if (Op.getValueType() != EltVT)
160 // FIXME: Can this happen for floating point types?
161 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
166 assert(N->isUnindexed() && "Indexed vector load?");
168 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
169 N->getExtensionType(),
170 N->getValueType(0).getVectorElementType(),
172 N->getChain(), N->getBasePtr(),
173 DAG.getUNDEF(N->getBasePtr().getValueType()),
175 N->getMemoryVT().getVectorElementType(),
176 N->isVolatile(), N->isNonTemporal(),
177 N->getOriginalAlignment());
179 // Legalized the chain result - switch anything that used the old chain to
181 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
185 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
186 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
187 EVT DestVT = N->getValueType(0).getVectorElementType();
188 SDValue Op = GetScalarizedVector(N->getOperand(0));
189 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
192 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
193 EVT EltVT = N->getValueType(0).getVectorElementType();
194 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
195 SDValue LHS = GetScalarizedVector(N->getOperand(0));
196 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT,
197 LHS, DAG.getValueType(ExtVT));
200 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
201 // If the operand is wider than the vector element type then it is implicitly
202 // truncated. Make that explicit here.
203 EVT EltVT = N->getValueType(0).getVectorElementType();
204 SDValue InOp = N->getOperand(0);
205 if (InOp.getValueType() != EltVT)
206 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
210 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
211 SDValue LHS = GetScalarizedVector(N->getOperand(1));
212 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
213 LHS.getValueType(), N->getOperand(0), LHS,
214 GetScalarizedVector(N->getOperand(2)));
217 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
218 SDValue LHS = GetScalarizedVector(N->getOperand(2));
219 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
220 N->getOperand(0), N->getOperand(1),
221 LHS, GetScalarizedVector(N->getOperand(3)),
225 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
226 SDValue LHS = GetScalarizedVector(N->getOperand(0));
227 SDValue RHS = GetScalarizedVector(N->getOperand(1));
228 DebugLoc DL = N->getDebugLoc();
230 // Turn it into a scalar SETCC.
231 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
234 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
235 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
238 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
239 // Figure out if the scalar is the LHS or RHS and return it.
240 SDValue Arg = N->getOperand(2).getOperand(0);
241 if (Arg.getOpcode() == ISD::UNDEF)
242 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
243 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
244 return GetScalarizedVector(N->getOperand(Op));
247 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
248 SDValue LHS = GetScalarizedVector(N->getOperand(0));
249 SDValue RHS = GetScalarizedVector(N->getOperand(1));
250 EVT NVT = N->getValueType(0).getVectorElementType();
251 EVT SVT = TLI.getSetCCResultType(LHS.getValueType());
252 DebugLoc DL = N->getDebugLoc();
254 // Turn it into a scalar SETCC.
255 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2));
257 // VSETCC always returns a sign-extended value, while SETCC may not. The
258 // SETCC result type may not match the vector element type. Correct these.
259 if (NVT.bitsLE(SVT)) {
260 // The SETCC result type is bigger than the vector element type.
261 // Ensure the SETCC result is sign-extended.
262 if (TLI.getBooleanContents() !=
263 TargetLowering::ZeroOrNegativeOneBooleanContent)
264 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
265 DAG.getValueType(MVT::i1));
266 // Truncate to the final type.
267 return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
270 // The SETCC result type is smaller than the vector element type.
271 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
272 if (TLI.getBooleanContents() !=
273 TargetLowering::ZeroOrNegativeOneBooleanContent)
274 Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
275 // Sign extend to the final type.
276 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
280 //===----------------------------------------------------------------------===//
281 // Operand Vector Scalarization <1 x ty> -> ty.
282 //===----------------------------------------------------------------------===//
284 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
285 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
288 SDValue Res = SDValue();
290 if (Res.getNode() == 0) {
291 switch (N->getOpcode()) {
294 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
298 llvm_unreachable("Do not know how to scalarize this operator's operand!");
300 Res = ScalarizeVecOp_BITCAST(N);
302 case ISD::CONCAT_VECTORS:
303 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
305 case ISD::EXTRACT_VECTOR_ELT:
306 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
309 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
314 // If the result is null, the sub-method took care of registering results etc.
315 if (!Res.getNode()) return false;
317 // If the result is N, the sub-method updated N in place. Tell the legalizer
319 if (Res.getNode() == N)
322 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
323 "Invalid operand expansion");
325 ReplaceValueWith(SDValue(N, 0), Res);
329 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
330 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
331 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
332 SDValue Elt = GetScalarizedVector(N->getOperand(0));
333 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
334 N->getValueType(0), Elt);
337 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
338 /// use a BUILD_VECTOR instead.
339 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
340 SmallVector<SDValue, 8> Ops(N->getNumOperands());
341 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
342 Ops[i] = GetScalarizedVector(N->getOperand(i));
343 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
344 &Ops[0], Ops.size());
347 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
348 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
350 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
351 SDValue Res = GetScalarizedVector(N->getOperand(0));
352 if (Res.getValueType() != N->getValueType(0))
353 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
358 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
359 /// scalarized, it must be <1 x ty>. Just store the element.
360 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
361 assert(N->isUnindexed() && "Indexed store of one-element vector?");
362 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
363 DebugLoc dl = N->getDebugLoc();
365 if (N->isTruncatingStore())
366 return DAG.getTruncStore(N->getChain(), dl,
367 GetScalarizedVector(N->getOperand(1)),
368 N->getBasePtr(), N->getPointerInfo(),
369 N->getMemoryVT().getVectorElementType(),
370 N->isVolatile(), N->isNonTemporal(),
373 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
374 N->getBasePtr(), N->getPointerInfo(),
375 N->isVolatile(), N->isNonTemporal(),
376 N->getOriginalAlignment());
380 //===----------------------------------------------------------------------===//
381 // Result Vector Splitting
382 //===----------------------------------------------------------------------===//
384 /// SplitVectorResult - This method is called when the specified result of the
385 /// specified node is found to need vector splitting. At this point, the node
386 /// may also have invalid operands or may have other results that need
387 /// legalization, we just know that (at least) one result needs vector
389 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
390 DEBUG(dbgs() << "Split node result: ";
395 switch (N->getOpcode()) {
398 dbgs() << "SplitVectorResult #" << ResNo << ": ";
402 llvm_unreachable("Do not know how to split the result of this operator!");
404 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
405 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
406 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
407 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
409 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
410 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
411 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
412 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
413 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
414 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
415 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
416 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
417 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
418 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
420 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
424 SplitVecRes_SETCC(N, Lo, Hi);
426 case ISD::VECTOR_SHUFFLE:
427 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
442 case ISD::FNEARBYINT:
444 case ISD::FP_TO_SINT:
445 case ISD::FP_TO_UINT:
446 case ISD::SINT_TO_FP:
447 case ISD::UINT_TO_FP:
449 case ISD::SIGN_EXTEND:
450 case ISD::ZERO_EXTEND:
451 case ISD::ANY_EXTEND:
457 SplitVecRes_UnaryOp(N, Lo, Hi);
479 SplitVecRes_BinOp(N, Lo, Hi);
483 // If Lo/Hi is null, the sub-method took care of registering results etc.
485 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
488 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
490 SDValue LHSLo, LHSHi;
491 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
492 SDValue RHSLo, RHSHi;
493 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
494 DebugLoc dl = N->getDebugLoc();
496 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
497 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
500 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
502 // We know the result is a vector. The input may be either a vector or a
505 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
506 DebugLoc dl = N->getDebugLoc();
508 SDValue InOp = N->getOperand(0);
509 EVT InVT = InOp.getValueType();
511 // Handle some special cases efficiently.
512 switch (getTypeAction(InVT)) {
514 assert(false && "Unknown type action!");
518 case ScalarizeVector:
522 // A scalar to vector conversion, where the scalar needs expansion.
523 // If the vector is being split in two then we can just convert the
526 GetExpandedOp(InOp, Lo, Hi);
527 if (TLI.isBigEndian())
529 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
530 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
535 // If the input is a vector that needs to be split, convert each split
536 // piece of the input now.
537 GetSplitVector(InOp, Lo, Hi);
538 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
539 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
543 // In the general case, convert the input to an integer and split it by hand.
544 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
545 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
546 if (TLI.isBigEndian())
547 std::swap(LoIntVT, HiIntVT);
549 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
551 if (TLI.isBigEndian())
553 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
554 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
557 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
560 DebugLoc dl = N->getDebugLoc();
561 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
562 unsigned LoNumElts = LoVT.getVectorNumElements();
563 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
564 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
566 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
567 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
570 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
572 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
573 DebugLoc dl = N->getDebugLoc();
574 unsigned NumSubvectors = N->getNumOperands() / 2;
575 if (NumSubvectors == 1) {
576 Lo = N->getOperand(0);
577 Hi = N->getOperand(1);
582 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
584 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
585 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
587 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
588 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
591 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
594 DebugLoc dl = N->getDebugLoc();
595 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
597 SDValue DTyOpLo = DAG.getValueType(LoVT);
598 SDValue DTyOpHi = DAG.getValueType(HiVT);
600 SDValue RndOp = N->getOperand(3);
601 SDValue SatOp = N->getOperand(4);
602 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
606 EVT InVT = N->getOperand(0).getValueType();
607 switch (getTypeAction(InVT)) {
608 default: llvm_unreachable("Unexpected type action!");
610 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
611 LoVT.getVectorNumElements());
612 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
613 DAG.getIntPtrConstant(0));
614 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
615 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
619 GetSplitVector(N->getOperand(0), VLo, VHi);
622 // If the result needs to be split and the input needs to be widened,
623 // the two types must have different lengths. Use the widened result
624 // and extract from it to do the split.
625 SDValue InOp = GetWidenedVector(N->getOperand(0));
626 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
627 LoVT.getVectorNumElements());
628 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
629 DAG.getIntPtrConstant(0));
630 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
631 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
636 SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
637 SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
639 Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
641 Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp,
645 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
647 SDValue Vec = N->getOperand(0);
648 SDValue Idx = N->getOperand(1);
649 DebugLoc dl = N->getDebugLoc();
652 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
654 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
655 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
656 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
657 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements()));
660 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
662 DebugLoc dl = N->getDebugLoc();
663 GetSplitVector(N->getOperand(0), Lo, Hi);
664 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
665 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
668 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
670 SDValue LHSLo, LHSHi;
671 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
672 DebugLoc dl = N->getDebugLoc();
675 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT);
677 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
678 DAG.getValueType(LoVT));
679 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
680 DAG.getValueType(HiVT));
683 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
685 SDValue Vec = N->getOperand(0);
686 SDValue Elt = N->getOperand(1);
687 SDValue Idx = N->getOperand(2);
688 DebugLoc dl = N->getDebugLoc();
689 GetSplitVector(Vec, Lo, Hi);
691 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
692 unsigned IdxVal = CIdx->getZExtValue();
693 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
694 if (IdxVal < LoNumElts)
695 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
696 Lo.getValueType(), Lo, Elt, Idx);
698 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
699 DAG.getIntPtrConstant(IdxVal - LoNumElts));
703 // Spill the vector to the stack.
704 EVT VecVT = Vec.getValueType();
705 EVT EltVT = VecVT.getVectorElementType();
706 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
707 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
708 MachinePointerInfo(), false, false, 0);
710 // Store the new element. This may be larger than the vector element type,
711 // so use a truncating store.
712 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
713 const Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
715 TLI.getTargetData()->getPrefTypeAlignment(VecType);
716 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
719 // Load the Lo part from the stack slot.
720 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
723 // Increment the pointer to the other part.
724 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
725 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
726 DAG.getIntPtrConstant(IncrementSize));
728 // Load the Hi part from the stack slot.
729 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
730 false, false, MinAlign(Alignment, IncrementSize));
733 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
736 DebugLoc dl = N->getDebugLoc();
737 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
738 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
739 Hi = DAG.getUNDEF(HiVT);
742 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
744 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
746 DebugLoc dl = LD->getDebugLoc();
747 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
749 ISD::LoadExtType ExtType = LD->getExtensionType();
750 SDValue Ch = LD->getChain();
751 SDValue Ptr = LD->getBasePtr();
752 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
753 EVT MemoryVT = LD->getMemoryVT();
754 unsigned Alignment = LD->getOriginalAlignment();
755 bool isVolatile = LD->isVolatile();
756 bool isNonTemporal = LD->isNonTemporal();
758 EVT LoMemVT, HiMemVT;
759 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
761 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
762 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
765 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
766 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
767 DAG.getIntPtrConstant(IncrementSize));
768 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
769 LD->getPointerInfo().getWithOffset(IncrementSize),
770 HiMemVT, isVolatile, isNonTemporal, Alignment);
772 // Build a factor node to remember that this load is independent of the
774 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
777 // Legalized the chain result - switch anything that used the old chain to
779 ReplaceValueWith(SDValue(LD, 1), Ch);
782 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
784 DebugLoc DL = N->getDebugLoc();
785 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
788 EVT InVT = N->getOperand(0).getValueType();
789 SDValue LL, LH, RL, RH;
790 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
791 LoVT.getVectorNumElements());
792 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
793 DAG.getIntPtrConstant(0));
794 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
795 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
797 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
798 DAG.getIntPtrConstant(0));
799 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
800 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
802 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
803 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
806 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
808 // Get the dest types - they may not match the input types, e.g. int_to_fp.
810 DebugLoc dl = N->getDebugLoc();
811 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
814 EVT InVT = N->getOperand(0).getValueType();
815 switch (getTypeAction(InVT)) {
816 default: llvm_unreachable("Unexpected type action!");
818 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
819 LoVT.getVectorNumElements());
820 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
821 DAG.getIntPtrConstant(0));
822 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
823 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
827 GetSplitVector(N->getOperand(0), Lo, Hi);
830 // If the result needs to be split and the input needs to be widened,
831 // the two types must have different lengths. Use the widened result
832 // and extract from it to do the split.
833 SDValue InOp = GetWidenedVector(N->getOperand(0));
834 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
835 LoVT.getVectorNumElements());
836 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
837 DAG.getIntPtrConstant(0));
838 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
839 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
844 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
845 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
848 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
849 SDValue &Lo, SDValue &Hi) {
850 // The low and high parts of the original input give four input vectors.
852 DebugLoc dl = N->getDebugLoc();
853 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
854 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
855 EVT NewVT = Inputs[0].getValueType();
856 unsigned NewElts = NewVT.getVectorNumElements();
858 // If Lo or Hi uses elements from at most two of the four input vectors, then
859 // express it as a vector shuffle of those two inputs. Otherwise extract the
860 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
861 SmallVector<int, 16> Ops;
862 for (unsigned High = 0; High < 2; ++High) {
863 SDValue &Output = High ? Hi : Lo;
865 // Build a shuffle mask for the output, discovering on the fly which
866 // input vectors to use as shuffle operands (recorded in InputUsed).
867 // If building a suitable shuffle vector proves too hard, then bail
868 // out with useBuildVector set.
869 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
870 unsigned FirstMaskIdx = High * NewElts;
871 bool useBuildVector = false;
872 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
873 // The mask element. This indexes into the input.
874 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
876 // The input vector this mask element indexes into.
877 unsigned Input = (unsigned)Idx / NewElts;
879 if (Input >= array_lengthof(Inputs)) {
880 // The mask element does not index into any input vector.
885 // Turn the index into an offset from the start of the input vector.
886 Idx -= Input * NewElts;
888 // Find or create a shuffle vector operand to hold this input.
890 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
891 if (InputUsed[OpNo] == Input) {
892 // This input vector is already an operand.
894 } else if (InputUsed[OpNo] == -1U) {
895 // Create a new operand for this input vector.
896 InputUsed[OpNo] = Input;
901 if (OpNo >= array_lengthof(InputUsed)) {
902 // More than two input vectors used! Give up on trying to create a
903 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
904 useBuildVector = true;
908 // Add the mask index for the new shuffle vector.
909 Ops.push_back(Idx + OpNo * NewElts);
912 if (useBuildVector) {
913 EVT EltVT = NewVT.getVectorElementType();
914 SmallVector<SDValue, 16> SVOps;
916 // Extract the input elements by hand.
917 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
918 // The mask element. This indexes into the input.
919 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
921 // The input vector this mask element indexes into.
922 unsigned Input = (unsigned)Idx / NewElts;
924 if (Input >= array_lengthof(Inputs)) {
925 // The mask element is "undef" or indexes off the end of the input.
926 SVOps.push_back(DAG.getUNDEF(EltVT));
930 // Turn the index into an offset from the start of the input vector.
931 Idx -= Input * NewElts;
933 // Extract the vector element by hand.
934 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
935 Inputs[Input], DAG.getIntPtrConstant(Idx)));
938 // Construct the Lo/Hi output using a BUILD_VECTOR.
939 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
940 } else if (InputUsed[0] == -1U) {
941 // No input vectors were used! The result is undefined.
942 Output = DAG.getUNDEF(NewVT);
944 SDValue Op0 = Inputs[InputUsed[0]];
945 // If only one input was used, use an undefined vector for the other.
946 SDValue Op1 = InputUsed[1] == -1U ?
947 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
948 // At least one input vector was used. Create a new shuffle vector.
949 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
957 //===----------------------------------------------------------------------===//
958 // Operand Vector Splitting
959 //===----------------------------------------------------------------------===//
961 /// SplitVectorOperand - This method is called when the specified operand of the
962 /// specified node is found to need vector splitting. At this point, all of the
963 /// result types of the node are known to be legal, but other operands of the
964 /// node may need legalization as well as the specified one.
965 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
966 DEBUG(dbgs() << "Split node operand: ";
969 SDValue Res = SDValue();
971 if (Res.getNode() == 0) {
972 switch (N->getOpcode()) {
975 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
979 llvm_unreachable("Do not know how to split this operator's operand!");
981 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
982 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
983 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
984 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
985 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
987 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
993 case ISD::FP_TO_SINT:
994 case ISD::FP_TO_UINT:
995 case ISD::SINT_TO_FP:
996 case ISD::UINT_TO_FP:
1000 case ISD::SIGN_EXTEND:
1001 case ISD::ZERO_EXTEND:
1002 case ISD::ANY_EXTEND:
1003 Res = SplitVecOp_UnaryOp(N);
1008 // If the result is null, the sub-method took care of registering results etc.
1009 if (!Res.getNode()) return false;
1011 // If the result is N, the sub-method updated N in place. Tell the legalizer
1013 if (Res.getNode() == N)
1016 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1017 "Invalid operand expansion");
1019 ReplaceValueWith(SDValue(N, 0), Res);
1023 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1024 // The result has a legal vector type, but the input needs splitting.
1025 EVT ResVT = N->getValueType(0);
1027 DebugLoc dl = N->getDebugLoc();
1028 GetSplitVector(N->getOperand(0), Lo, Hi);
1029 EVT InVT = Lo.getValueType();
1031 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1032 InVT.getVectorNumElements());
1034 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1035 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1037 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1040 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1041 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1042 // end up being split all the way down to individual components. Convert the
1043 // split pieces into integers and reassemble.
1045 GetSplitVector(N->getOperand(0), Lo, Hi);
1046 Lo = BitConvertToInteger(Lo);
1047 Hi = BitConvertToInteger(Hi);
1049 if (TLI.isBigEndian())
1052 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
1053 JoinIntegers(Lo, Hi));
1056 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1057 // We know that the extracted result type is legal.
1058 EVT SubVT = N->getValueType(0);
1059 SDValue Idx = N->getOperand(1);
1060 DebugLoc dl = N->getDebugLoc();
1062 GetSplitVector(N->getOperand(0), Lo, Hi);
1064 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1065 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1067 if (IdxVal < LoElts) {
1068 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1069 "Extracted subvector crosses vector split!");
1070 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1072 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1073 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1077 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1078 SDValue Vec = N->getOperand(0);
1079 SDValue Idx = N->getOperand(1);
1080 EVT VecVT = Vec.getValueType();
1082 if (isa<ConstantSDNode>(Idx)) {
1083 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1084 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1087 GetSplitVector(Vec, Lo, Hi);
1089 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1091 if (IdxVal < LoElts)
1092 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1093 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1094 DAG.getConstant(IdxVal - LoElts,
1095 Idx.getValueType())), 0);
1098 // Store the vector to the stack.
1099 EVT EltVT = VecVT.getVectorElementType();
1100 DebugLoc dl = N->getDebugLoc();
1101 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1102 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1103 MachinePointerInfo(), false, false, 0);
1105 // Load back the required element.
1106 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1107 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1108 MachinePointerInfo(), EltVT, false, false, 0);
1111 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1112 assert(N->isUnindexed() && "Indexed store of vector?");
1113 assert(OpNo == 1 && "Can only split the stored value");
1114 DebugLoc DL = N->getDebugLoc();
1116 bool isTruncating = N->isTruncatingStore();
1117 SDValue Ch = N->getChain();
1118 SDValue Ptr = N->getBasePtr();
1119 EVT MemoryVT = N->getMemoryVT();
1120 unsigned Alignment = N->getOriginalAlignment();
1121 bool isVol = N->isVolatile();
1122 bool isNT = N->isNonTemporal();
1124 GetSplitVector(N->getOperand(1), Lo, Hi);
1126 EVT LoMemVT, HiMemVT;
1127 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1129 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1132 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1133 LoMemVT, isVol, isNT, Alignment);
1135 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1136 isVol, isNT, Alignment);
1138 // Increment the pointer to the other half.
1139 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1140 DAG.getIntPtrConstant(IncrementSize));
1143 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1144 N->getPointerInfo().getWithOffset(IncrementSize),
1145 HiMemVT, isVol, isNT, Alignment);
1147 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1148 N->getPointerInfo().getWithOffset(IncrementSize),
1149 isVol, isNT, Alignment);
1151 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1154 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1155 DebugLoc DL = N->getDebugLoc();
1157 // The input operands all must have the same type, and we know the result the
1158 // result type is valid. Convert this to a buildvector which extracts all the
1160 // TODO: If the input elements are power-two vectors, we could convert this to
1161 // a new CONCAT_VECTORS node with elements that are half-wide.
1162 SmallVector<SDValue, 32> Elts;
1163 EVT EltVT = N->getValueType(0).getVectorElementType();
1164 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1165 SDValue Op = N->getOperand(op);
1166 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1168 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1169 Op, DAG.getIntPtrConstant(i)));
1174 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
1175 &Elts[0], Elts.size());
1178 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1179 // The result has a legal vector type, but the input needs splitting.
1180 EVT ResVT = N->getValueType(0);
1182 DebugLoc DL = N->getDebugLoc();
1183 GetSplitVector(N->getOperand(0), Lo, Hi);
1184 EVT InVT = Lo.getValueType();
1186 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1187 InVT.getVectorNumElements());
1189 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1190 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1192 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1197 //===----------------------------------------------------------------------===//
1198 // Result Vector Widening
1199 //===----------------------------------------------------------------------===//
1201 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1202 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1206 // See if the target wants to custom widen this node.
1207 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1210 SDValue Res = SDValue();
1211 switch (N->getOpcode()) {
1214 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1218 llvm_unreachable("Do not know how to widen the result of this operator!");
1220 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1221 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1222 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1223 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1224 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1225 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1226 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1227 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1228 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1229 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1230 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1231 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1232 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1233 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1234 case ISD::VECTOR_SHUFFLE:
1235 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1238 Res = WidenVecRes_VSETCC(N);
1245 case ISD::FCOPYSIGN:
1261 Res = WidenVecRes_Binary(N);
1265 Res = WidenVecRes_POWI(N);
1271 Res = WidenVecRes_Shift(N);
1275 case ISD::FP_TO_SINT:
1276 case ISD::FP_TO_UINT:
1277 case ISD::SINT_TO_FP:
1278 case ISD::UINT_TO_FP:
1280 case ISD::SIGN_EXTEND:
1281 case ISD::ZERO_EXTEND:
1282 case ISD::ANY_EXTEND:
1283 Res = WidenVecRes_Convert(N);
1299 Res = WidenVecRes_Unary(N);
1303 // If Res is null, the sub-method took care of registering the result.
1305 SetWidenedVector(SDValue(N, ResNo), Res);
1308 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1309 // Binary op widening.
1310 unsigned Opcode = N->getOpcode();
1311 DebugLoc dl = N->getDebugLoc();
1312 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1313 EVT WidenEltVT = WidenVT.getVectorElementType();
1315 unsigned NumElts = VT.getVectorNumElements();
1316 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1317 NumElts = NumElts / 2;
1318 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1321 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1322 // Operation doesn't trap so just widen as normal.
1323 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1324 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1325 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1328 // No legal vector version so unroll the vector operation and then widen.
1330 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1332 // Since the operation can trap, apply operation on the original vector.
1334 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1335 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1336 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1338 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1339 unsigned ConcatEnd = 0; // Current ConcatOps index.
1340 int Idx = 0; // Current Idx into input vectors.
1342 // NumElts := greatest legal vector size (at most WidenVT)
1343 // while (orig. vector has unhandled elements) {
1344 // take munches of size NumElts from the beginning and add to ConcatOps
1345 // NumElts := next smaller supported vector size or 1
1347 while (CurNumElts != 0) {
1348 while (CurNumElts >= NumElts) {
1349 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1350 DAG.getIntPtrConstant(Idx));
1351 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1352 DAG.getIntPtrConstant(Idx));
1353 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1355 CurNumElts -= NumElts;
1358 NumElts = NumElts / 2;
1359 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1360 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1363 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1364 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1365 InOp1, DAG.getIntPtrConstant(Idx));
1366 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1367 InOp2, DAG.getIntPtrConstant(Idx));
1368 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1375 // Check to see if we have a single operation with the widen type.
1376 if (ConcatEnd == 1) {
1377 VT = ConcatOps[0].getValueType();
1379 return ConcatOps[0];
1382 // while (Some element of ConcatOps is not of type MaxVT) {
1383 // From the end of ConcatOps, collect elements of the same type and put
1384 // them into an op of the next larger supported type
1386 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1387 Idx = ConcatEnd - 1;
1388 VT = ConcatOps[Idx--].getValueType();
1389 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1392 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1396 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1397 } while (!TLI.isTypeLegal(NextVT));
1399 if (!VT.isVector()) {
1400 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1401 SDValue VecOp = DAG.getUNDEF(NextVT);
1402 unsigned NumToInsert = ConcatEnd - Idx - 1;
1403 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1404 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1405 ConcatOps[OpIdx], DAG.getIntPtrConstant(i));
1407 ConcatOps[Idx+1] = VecOp;
1408 ConcatEnd = Idx + 2;
1410 // Vector type, create a CONCAT_VECTORS of type NextVT
1411 SDValue undefVec = DAG.getUNDEF(VT);
1412 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1413 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1414 unsigned RealVals = ConcatEnd - Idx - 1;
1415 unsigned SubConcatEnd = 0;
1416 unsigned SubConcatIdx = Idx + 1;
1417 while (SubConcatEnd < RealVals)
1418 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1419 while (SubConcatEnd < OpsToConcat)
1420 SubConcatOps[SubConcatEnd++] = undefVec;
1421 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1422 NextVT, &SubConcatOps[0],
1424 ConcatEnd = SubConcatIdx + 1;
1428 // Check to see if we have a single operation with the widen type.
1429 if (ConcatEnd == 1) {
1430 VT = ConcatOps[0].getValueType();
1432 return ConcatOps[0];
1435 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1436 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1437 if (NumOps != ConcatEnd ) {
1438 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1439 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1440 ConcatOps[j] = UndefVal;
1442 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps);
1445 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1446 SDValue InOp = N->getOperand(0);
1447 DebugLoc DL = N->getDebugLoc();
1449 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1450 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1452 EVT InVT = InOp.getValueType();
1453 EVT InEltVT = InVT.getVectorElementType();
1454 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1456 unsigned Opcode = N->getOpcode();
1457 unsigned InVTNumElts = InVT.getVectorNumElements();
1459 if (getTypeAction(InVT) == WidenVector) {
1460 InOp = GetWidenedVector(N->getOperand(0));
1461 InVT = InOp.getValueType();
1462 InVTNumElts = InVT.getVectorNumElements();
1463 if (InVTNumElts == WidenNumElts) {
1464 if (N->getNumOperands() == 1)
1465 return DAG.getNode(Opcode, DL, WidenVT, InOp);
1466 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
1470 if (TLI.isTypeLegal(InWidenVT)) {
1471 // Because the result and the input are different vector types, widening
1472 // the result could create a legal type but widening the input might make
1473 // it an illegal type that might lead to repeatedly splitting the input
1474 // and then widening it. To avoid this, we widen the input only if
1475 // it results in a legal type.
1476 if (WidenNumElts % InVTNumElts == 0) {
1477 // Widen the input and call convert on the widened input vector.
1478 unsigned NumConcat = WidenNumElts/InVTNumElts;
1479 SmallVector<SDValue, 16> Ops(NumConcat);
1481 SDValue UndefVal = DAG.getUNDEF(InVT);
1482 for (unsigned i = 1; i != NumConcat; ++i)
1484 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT,
1485 &Ops[0], NumConcat);
1486 if (N->getNumOperands() == 1)
1487 return DAG.getNode(Opcode, DL, WidenVT, InVec);
1488 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
1491 if (InVTNumElts % WidenNumElts == 0) {
1492 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
1493 InOp, DAG.getIntPtrConstant(0));
1494 // Extract the input and convert the shorten input vector.
1495 if (N->getNumOperands() == 1)
1496 return DAG.getNode(Opcode, DL, WidenVT, InVal);
1497 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
1501 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1502 SmallVector<SDValue, 16> Ops(WidenNumElts);
1503 EVT EltVT = WidenVT.getVectorElementType();
1504 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1506 for (i=0; i < MinElts; ++i) {
1507 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
1508 DAG.getIntPtrConstant(i));
1509 if (N->getNumOperands() == 1)
1510 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
1512 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
1515 SDValue UndefVal = DAG.getUNDEF(EltVT);
1516 for (; i < WidenNumElts; ++i)
1519 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts);
1522 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
1523 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1524 SDValue InOp = GetWidenedVector(N->getOperand(0));
1525 SDValue ShOp = N->getOperand(1);
1526 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1529 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1530 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1531 SDValue InOp = GetWidenedVector(N->getOperand(0));
1532 SDValue ShOp = N->getOperand(1);
1534 EVT ShVT = ShOp.getValueType();
1535 if (getTypeAction(ShVT) == WidenVector) {
1536 ShOp = GetWidenedVector(ShOp);
1537 ShVT = ShOp.getValueType();
1539 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
1540 ShVT.getVectorElementType(),
1541 WidenVT.getVectorNumElements());
1542 if (ShVT != ShWidenVT)
1543 ShOp = ModifyToType(ShOp, ShWidenVT);
1545 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1548 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1549 // Unary op widening.
1550 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1551 SDValue InOp = GetWidenedVector(N->getOperand(0));
1552 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1555 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
1556 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1557 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
1558 cast<VTSDNode>(N->getOperand(1))->getVT()
1559 .getVectorElementType(),
1560 WidenVT.getVectorNumElements());
1561 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
1562 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
1563 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
1566 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
1567 SDValue InOp = N->getOperand(0);
1568 EVT InVT = InOp.getValueType();
1569 EVT VT = N->getValueType(0);
1570 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1571 DebugLoc dl = N->getDebugLoc();
1573 switch (getTypeAction(InVT)) {
1575 assert(false && "Unknown type action!");
1579 case PromoteInteger:
1580 // If the InOp is promoted to the same size, convert it. Otherwise,
1581 // fall out of the switch and widen the promoted input.
1582 InOp = GetPromotedInteger(InOp);
1583 InVT = InOp.getValueType();
1584 if (WidenVT.bitsEq(InVT))
1585 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1590 case ScalarizeVector:
1594 // If the InOp is widened to the same size, convert it. Otherwise, fall
1595 // out of the switch and widen the widened input.
1596 InOp = GetWidenedVector(InOp);
1597 InVT = InOp.getValueType();
1598 if (WidenVT.bitsEq(InVT))
1599 // The input widens to the same size. Convert to the widen value.
1600 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1604 unsigned WidenSize = WidenVT.getSizeInBits();
1605 unsigned InSize = InVT.getSizeInBits();
1606 // x86mmx is not an acceptable vector element type, so don't try.
1607 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
1608 // Determine new input vector type. The new input vector type will use
1609 // the same element type (if its a vector) or use the input type as a
1610 // vector. It is the same size as the type to widen to.
1612 unsigned NewNumElts = WidenSize / InSize;
1613 if (InVT.isVector()) {
1614 EVT InEltVT = InVT.getVectorElementType();
1615 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
1616 WidenSize / InEltVT.getSizeInBits());
1618 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
1621 if (TLI.isTypeLegal(NewInVT)) {
1622 // Because the result and the input are different vector types, widening
1623 // the result could create a legal type but widening the input might make
1624 // it an illegal type that might lead to repeatedly splitting the input
1625 // and then widening it. To avoid this, we widen the input only if
1626 // it results in a legal type.
1627 SmallVector<SDValue, 16> Ops(NewNumElts);
1628 SDValue UndefVal = DAG.getUNDEF(InVT);
1630 for (unsigned i = 1; i < NewNumElts; ++i)
1634 if (InVT.isVector())
1635 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1636 NewInVT, &Ops[0], NewNumElts);
1638 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1639 NewInVT, &Ops[0], NewNumElts);
1640 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
1644 return CreateStackStoreLoad(InOp, WidenVT);
1647 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1648 DebugLoc dl = N->getDebugLoc();
1649 // Build a vector with undefined for the new nodes.
1650 EVT VT = N->getValueType(0);
1651 EVT EltVT = VT.getVectorElementType();
1652 unsigned NumElts = VT.getVectorNumElements();
1654 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1655 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1657 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1658 NewOps.reserve(WidenNumElts);
1659 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1660 NewOps.push_back(DAG.getUNDEF(EltVT));
1662 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1665 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1666 EVT InVT = N->getOperand(0).getValueType();
1667 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1668 DebugLoc dl = N->getDebugLoc();
1669 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1670 unsigned NumOperands = N->getNumOperands();
1672 bool InputWidened = false; // Indicates we need to widen the input.
1673 if (getTypeAction(InVT) != WidenVector) {
1674 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1675 // Add undef vectors to widen to correct length.
1676 unsigned NumConcat = WidenVT.getVectorNumElements() /
1677 InVT.getVectorNumElements();
1678 SDValue UndefVal = DAG.getUNDEF(InVT);
1679 SmallVector<SDValue, 16> Ops(NumConcat);
1680 for (unsigned i=0; i < NumOperands; ++i)
1681 Ops[i] = N->getOperand(i);
1682 for (unsigned i = NumOperands; i != NumConcat; ++i)
1684 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1687 InputWidened = true;
1688 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
1689 // The inputs and the result are widen to the same value.
1691 for (i=1; i < NumOperands; ++i)
1692 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1695 if (i > NumOperands)
1696 // Everything but the first operand is an UNDEF so just return the
1697 // widened first operand.
1698 return GetWidenedVector(N->getOperand(0));
1700 if (NumOperands == 2) {
1701 // Replace concat of two operands with a shuffle.
1702 SmallVector<int, 16> MaskOps(WidenNumElts);
1703 for (unsigned i=0; i < WidenNumElts/2; ++i) {
1705 MaskOps[i+WidenNumElts/2] = i+WidenNumElts;
1707 return DAG.getVectorShuffle(WidenVT, dl,
1708 GetWidenedVector(N->getOperand(0)),
1709 GetWidenedVector(N->getOperand(1)),
1715 // Fall back to use extracts and build vector.
1716 EVT EltVT = WidenVT.getVectorElementType();
1717 unsigned NumInElts = InVT.getVectorNumElements();
1718 SmallVector<SDValue, 16> Ops(WidenNumElts);
1720 for (unsigned i=0; i < NumOperands; ++i) {
1721 SDValue InOp = N->getOperand(i);
1723 InOp = GetWidenedVector(InOp);
1724 for (unsigned j=0; j < NumInElts; ++j)
1725 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1726 DAG.getIntPtrConstant(j));
1728 SDValue UndefVal = DAG.getUNDEF(EltVT);
1729 for (; Idx < WidenNumElts; ++Idx)
1730 Ops[Idx] = UndefVal;
1731 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1734 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1735 DebugLoc dl = N->getDebugLoc();
1736 SDValue InOp = N->getOperand(0);
1737 SDValue RndOp = N->getOperand(3);
1738 SDValue SatOp = N->getOperand(4);
1740 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1741 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1743 EVT InVT = InOp.getValueType();
1744 EVT InEltVT = InVT.getVectorElementType();
1745 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1747 SDValue DTyOp = DAG.getValueType(WidenVT);
1748 SDValue STyOp = DAG.getValueType(InWidenVT);
1749 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1751 unsigned InVTNumElts = InVT.getVectorNumElements();
1752 if (getTypeAction(InVT) == WidenVector) {
1753 InOp = GetWidenedVector(InOp);
1754 InVT = InOp.getValueType();
1755 InVTNumElts = InVT.getVectorNumElements();
1756 if (InVTNumElts == WidenNumElts)
1757 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1761 if (TLI.isTypeLegal(InWidenVT)) {
1762 // Because the result and the input are different vector types, widening
1763 // the result could create a legal type but widening the input might make
1764 // it an illegal type that might lead to repeatedly splitting the input
1765 // and then widening it. To avoid this, we widen the input only if
1766 // it results in a legal type.
1767 if (WidenNumElts % InVTNumElts == 0) {
1768 // Widen the input and call convert on the widened input vector.
1769 unsigned NumConcat = WidenNumElts/InVTNumElts;
1770 SmallVector<SDValue, 16> Ops(NumConcat);
1772 SDValue UndefVal = DAG.getUNDEF(InVT);
1773 for (unsigned i = 1; i != NumConcat; ++i)
1776 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1777 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1781 if (InVTNumElts % WidenNumElts == 0) {
1782 // Extract the input and convert the shorten input vector.
1783 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1784 DAG.getIntPtrConstant(0));
1785 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1790 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1791 SmallVector<SDValue, 16> Ops(WidenNumElts);
1792 EVT EltVT = WidenVT.getVectorElementType();
1793 DTyOp = DAG.getValueType(EltVT);
1794 STyOp = DAG.getValueType(InEltVT);
1796 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1798 for (i=0; i < MinElts; ++i) {
1799 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1800 DAG.getIntPtrConstant(i));
1801 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1805 SDValue UndefVal = DAG.getUNDEF(EltVT);
1806 for (; i < WidenNumElts; ++i)
1809 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1812 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1813 EVT VT = N->getValueType(0);
1814 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1815 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1816 SDValue InOp = N->getOperand(0);
1817 SDValue Idx = N->getOperand(1);
1818 DebugLoc dl = N->getDebugLoc();
1820 if (getTypeAction(InOp.getValueType()) == WidenVector)
1821 InOp = GetWidenedVector(InOp);
1823 EVT InVT = InOp.getValueType();
1825 // Check if we can just return the input vector after widening.
1826 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1827 if (IdxVal == 0 && InVT == WidenVT)
1830 // Check if we can extract from the vector.
1831 unsigned InNumElts = InVT.getVectorNumElements();
1832 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1833 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1835 // We could try widening the input to the right length but for now, extract
1836 // the original elements, fill the rest with undefs and build a vector.
1837 SmallVector<SDValue, 16> Ops(WidenNumElts);
1838 EVT EltVT = VT.getVectorElementType();
1839 unsigned NumElts = VT.getVectorNumElements();
1841 for (i=0; i < NumElts; ++i)
1842 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1843 DAG.getIntPtrConstant(IdxVal+i));
1845 SDValue UndefVal = DAG.getUNDEF(EltVT);
1846 for (; i < WidenNumElts; ++i)
1848 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1851 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1852 SDValue InOp = GetWidenedVector(N->getOperand(0));
1853 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1854 InOp.getValueType(), InOp,
1855 N->getOperand(1), N->getOperand(2));
1858 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1859 LoadSDNode *LD = cast<LoadSDNode>(N);
1860 ISD::LoadExtType ExtType = LD->getExtensionType();
1863 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1864 if (ExtType != ISD::NON_EXTLOAD)
1865 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
1867 Result = GenWidenVectorLoads(LdChain, LD);
1869 // If we generate a single load, we can use that for the chain. Otherwise,
1870 // build a factor node to remember the multiple loads are independent and
1873 if (LdChain.size() == 1)
1874 NewChain = LdChain[0];
1876 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other,
1877 &LdChain[0], LdChain.size());
1879 // Modified the chain - switch anything that used the old chain to use
1881 ReplaceValueWith(SDValue(N, 1), NewChain);
1886 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1887 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1888 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1889 WidenVT, N->getOperand(0));
1892 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1893 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1894 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1896 SDValue Cond1 = N->getOperand(0);
1897 EVT CondVT = Cond1.getValueType();
1898 if (CondVT.isVector()) {
1899 EVT CondEltVT = CondVT.getVectorElementType();
1900 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
1901 CondEltVT, WidenNumElts);
1902 if (getTypeAction(CondVT) == WidenVector)
1903 Cond1 = GetWidenedVector(Cond1);
1905 if (Cond1.getValueType() != CondWidenVT)
1906 Cond1 = ModifyToType(Cond1, CondWidenVT);
1909 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1910 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1911 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1912 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
1913 WidenVT, Cond1, InOp1, InOp2);
1916 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1917 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1918 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1919 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1920 InOp1.getValueType(), N->getOperand(0),
1921 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1924 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
1925 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1926 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1927 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1928 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
1929 InOp1, InOp2, N->getOperand(2));
1932 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1933 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1934 return DAG.getUNDEF(WidenVT);
1937 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
1938 EVT VT = N->getValueType(0);
1939 DebugLoc dl = N->getDebugLoc();
1941 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1942 unsigned NumElts = VT.getVectorNumElements();
1943 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1945 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1946 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1948 // Adjust mask based on new input vector length.
1949 SmallVector<int, 16> NewMask;
1950 for (unsigned i = 0; i != NumElts; ++i) {
1951 int Idx = N->getMaskElt(i);
1952 if (Idx < (int)NumElts)
1953 NewMask.push_back(Idx);
1955 NewMask.push_back(Idx - NumElts + WidenNumElts);
1957 for (unsigned i = NumElts; i != WidenNumElts; ++i)
1958 NewMask.push_back(-1);
1959 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
1962 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1963 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1964 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1966 SDValue InOp1 = N->getOperand(0);
1967 EVT InVT = InOp1.getValueType();
1968 assert(InVT.isVector() && "can not widen non vector type");
1969 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
1970 InVT.getVectorElementType(), WidenNumElts);
1971 InOp1 = GetWidenedVector(InOp1);
1972 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1974 // Assume that the input and output will be widen appropriately. If not,
1975 // we will have to unroll it at some point.
1976 assert(InOp1.getValueType() == WidenInVT &&
1977 InOp2.getValueType() == WidenInVT &&
1978 "Input not widened to expected type!");
1979 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(),
1980 WidenVT, InOp1, InOp2, N->getOperand(2));
1984 //===----------------------------------------------------------------------===//
1985 // Widen Vector Operand
1986 //===----------------------------------------------------------------------===//
1987 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
1988 DEBUG(dbgs() << "Widen node operand " << ResNo << ": ";
1991 SDValue Res = SDValue();
1993 switch (N->getOpcode()) {
1996 dbgs() << "WidenVectorOperand op #" << ResNo << ": ";
2000 llvm_unreachable("Do not know how to widen this operator's operand!");
2002 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2003 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2004 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2005 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2006 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2009 case ISD::FP_EXTEND:
2010 case ISD::FP_TO_SINT:
2011 case ISD::FP_TO_UINT:
2012 case ISD::SINT_TO_FP:
2013 case ISD::UINT_TO_FP:
2015 case ISD::SIGN_EXTEND:
2016 case ISD::ZERO_EXTEND:
2017 case ISD::ANY_EXTEND:
2018 Res = WidenVecOp_Convert(N);
2022 // If Res is null, the sub-method took care of registering the result.
2023 if (!Res.getNode()) return false;
2025 // If the result is N, the sub-method updated N in place. Tell the legalizer
2027 if (Res.getNode() == N)
2031 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2032 "Invalid operand expansion");
2034 ReplaceValueWith(SDValue(N, 0), Res);
2038 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2039 // Since the result is legal and the input is illegal, it is unlikely
2040 // that we can fix the input to a legal type so unroll the convert
2041 // into some scalar code and create a nasty build vector.
2042 EVT VT = N->getValueType(0);
2043 EVT EltVT = VT.getVectorElementType();
2044 DebugLoc dl = N->getDebugLoc();
2045 unsigned NumElts = VT.getVectorNumElements();
2046 SDValue InOp = N->getOperand(0);
2047 if (getTypeAction(InOp.getValueType()) == WidenVector)
2048 InOp = GetWidenedVector(InOp);
2049 EVT InVT = InOp.getValueType();
2050 EVT InEltVT = InVT.getVectorElementType();
2052 unsigned Opcode = N->getOpcode();
2053 SmallVector<SDValue, 16> Ops(NumElts);
2054 for (unsigned i=0; i < NumElts; ++i)
2055 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2056 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2057 DAG.getIntPtrConstant(i)));
2059 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2062 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2063 EVT VT = N->getValueType(0);
2064 SDValue InOp = GetWidenedVector(N->getOperand(0));
2065 EVT InWidenVT = InOp.getValueType();
2066 DebugLoc dl = N->getDebugLoc();
2068 // Check if we can convert between two legal vector types and extract.
2069 unsigned InWidenSize = InWidenVT.getSizeInBits();
2070 unsigned Size = VT.getSizeInBits();
2071 // x86mmx is not an acceptable vector element type, so don't try.
2072 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2073 unsigned NewNumElts = InWidenSize / Size;
2074 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2075 if (TLI.isTypeLegal(NewVT)) {
2076 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2077 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2078 DAG.getIntPtrConstant(0));
2082 return CreateStackStoreLoad(InOp, VT);
2085 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2086 // If the input vector is not legal, it is likely that we will not find a
2087 // legal vector of the same size. Replace the concatenate vector with a
2088 // nasty build vector.
2089 EVT VT = N->getValueType(0);
2090 EVT EltVT = VT.getVectorElementType();
2091 DebugLoc dl = N->getDebugLoc();
2092 unsigned NumElts = VT.getVectorNumElements();
2093 SmallVector<SDValue, 16> Ops(NumElts);
2095 EVT InVT = N->getOperand(0).getValueType();
2096 unsigned NumInElts = InVT.getVectorNumElements();
2099 unsigned NumOperands = N->getNumOperands();
2100 for (unsigned i=0; i < NumOperands; ++i) {
2101 SDValue InOp = N->getOperand(i);
2102 if (getTypeAction(InOp.getValueType()) == WidenVector)
2103 InOp = GetWidenedVector(InOp);
2104 for (unsigned j=0; j < NumInElts; ++j)
2105 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2106 DAG.getIntPtrConstant(j));
2108 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2111 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2112 SDValue InOp = GetWidenedVector(N->getOperand(0));
2113 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
2114 N->getValueType(0), InOp, N->getOperand(1));
2117 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2118 SDValue InOp = GetWidenedVector(N->getOperand(0));
2119 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
2120 N->getValueType(0), InOp, N->getOperand(1));
2123 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2124 // We have to widen the value but we want only to store the original
2126 StoreSDNode *ST = cast<StoreSDNode>(N);
2128 SmallVector<SDValue, 16> StChain;
2129 if (ST->isTruncatingStore())
2130 GenWidenVectorTruncStores(StChain, ST);
2132 GenWidenVectorStores(StChain, ST);
2134 if (StChain.size() == 1)
2137 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(),
2138 MVT::Other,&StChain[0],StChain.size());
2141 //===----------------------------------------------------------------------===//
2142 // Vector Widening Utilities
2143 //===----------------------------------------------------------------------===//
2145 // Utility function to find the type to chop up a widen vector for load/store
2146 // TLI: Target lowering used to determine legal types.
2147 // Width: Width left need to load/store.
2148 // WidenVT: The widen vector type to load to/store from
2149 // Align: If 0, don't allow use of a wider type
2150 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2152 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2153 unsigned Width, EVT WidenVT,
2154 unsigned Align = 0, unsigned WidenEx = 0) {
2155 EVT WidenEltVT = WidenVT.getVectorElementType();
2156 unsigned WidenWidth = WidenVT.getSizeInBits();
2157 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2158 unsigned AlignInBits = Align*8;
2160 // If we have one element to load/store, return it.
2161 EVT RetVT = WidenEltVT;
2162 if (Width == WidenEltWidth)
2165 // See if there is larger legal integer than the element type to load/store
2167 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2168 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2169 EVT MemVT((MVT::SimpleValueType) VT);
2170 unsigned MemVTWidth = MemVT.getSizeInBits();
2171 if (MemVT.getSizeInBits() <= WidenEltWidth)
2173 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2174 (MemVTWidth <= Width ||
2175 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2181 // See if there is a larger vector type to load/store that has the same vector
2182 // element type and is evenly divisible with the WidenVT.
2183 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2184 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2185 EVT MemVT = (MVT::SimpleValueType) VT;
2186 unsigned MemVTWidth = MemVT.getSizeInBits();
2187 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2188 (WidenWidth % MemVTWidth) == 0 &&
2189 (MemVTWidth <= Width ||
2190 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2191 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2199 // Builds a vector type from scalar loads
2200 // VecTy: Resulting Vector type
2201 // LDOps: Load operators to build a vector type
2202 // [Start,End) the list of loads to use.
2203 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2204 SmallVector<SDValue, 16>& LdOps,
2205 unsigned Start, unsigned End) {
2206 DebugLoc dl = LdOps[Start].getDebugLoc();
2207 EVT LdTy = LdOps[Start].getValueType();
2208 unsigned Width = VecTy.getSizeInBits();
2209 unsigned NumElts = Width / LdTy.getSizeInBits();
2210 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2213 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2215 for (unsigned i = Start + 1; i != End; ++i) {
2216 EVT NewLdTy = LdOps[i].getValueType();
2217 if (NewLdTy != LdTy) {
2218 NumElts = Width / NewLdTy.getSizeInBits();
2219 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2220 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2221 // Readjust position and vector position based on new load type
2222 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2225 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2226 DAG.getIntPtrConstant(Idx++));
2228 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2231 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,
2233 // The strategy assumes that we can efficiently load powers of two widths.
2234 // The routines chops the vector into the largest vector loads with the same
2235 // element type or scalar loads and then recombines it to the widen vector
2237 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2238 unsigned WidenWidth = WidenVT.getSizeInBits();
2239 EVT LdVT = LD->getMemoryVT();
2240 DebugLoc dl = LD->getDebugLoc();
2241 assert(LdVT.isVector() && WidenVT.isVector());
2242 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2245 SDValue Chain = LD->getChain();
2246 SDValue BasePtr = LD->getBasePtr();
2247 unsigned Align = LD->getAlignment();
2248 bool isVolatile = LD->isVolatile();
2249 bool isNonTemporal = LD->isNonTemporal();
2251 int LdWidth = LdVT.getSizeInBits();
2252 int WidthDiff = WidenWidth - LdWidth; // Difference
2253 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
2255 // Find the vector type that can load from.
2256 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2257 int NewVTWidth = NewVT.getSizeInBits();
2258 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
2259 isVolatile, isNonTemporal, Align);
2260 LdChain.push_back(LdOp.getValue(1));
2262 // Check if we can load the element with one instruction
2263 if (LdWidth <= NewVTWidth) {
2264 if (!NewVT.isVector()) {
2265 unsigned NumElts = WidenWidth / NewVTWidth;
2266 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2267 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2268 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2270 if (NewVT == WidenVT)
2273 assert(WidenWidth % NewVTWidth == 0);
2274 unsigned NumConcat = WidenWidth / NewVTWidth;
2275 SmallVector<SDValue, 16> ConcatOps(NumConcat);
2276 SDValue UndefVal = DAG.getUNDEF(NewVT);
2277 ConcatOps[0] = LdOp;
2278 for (unsigned i = 1; i != NumConcat; ++i)
2279 ConcatOps[i] = UndefVal;
2280 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
2284 // Load vector by using multiple loads from largest vector to scalar
2285 SmallVector<SDValue, 16> LdOps;
2286 LdOps.push_back(LdOp);
2288 LdWidth -= NewVTWidth;
2289 unsigned Offset = 0;
2291 while (LdWidth > 0) {
2292 unsigned Increment = NewVTWidth / 8;
2293 Offset += Increment;
2294 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2295 DAG.getIntPtrConstant(Increment));
2297 if (LdWidth < NewVTWidth) {
2298 // Our current type we are using is too large, find a better size
2299 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2300 NewVTWidth = NewVT.getSizeInBits();
2303 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2304 LD->getPointerInfo().getWithOffset(Offset),
2306 isNonTemporal, MinAlign(Align, Increment));
2307 LdChain.push_back(LdOp.getValue(1));
2308 LdOps.push_back(LdOp);
2310 LdWidth -= NewVTWidth;
2313 // Build the vector from the loads operations
2314 unsigned End = LdOps.size();
2315 if (!LdOps[0].getValueType().isVector())
2316 // All the loads are scalar loads.
2317 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
2319 // If the load contains vectors, build the vector using concat vector.
2320 // All of the vectors used to loads are power of 2 and the scalars load
2321 // can be combined to make a power of 2 vector.
2322 SmallVector<SDValue, 16> ConcatOps(End);
2325 EVT LdTy = LdOps[i].getValueType();
2326 // First combine the scalar loads to a vector
2327 if (!LdTy.isVector()) {
2328 for (--i; i >= 0; --i) {
2329 LdTy = LdOps[i].getValueType();
2330 if (LdTy.isVector())
2333 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
2335 ConcatOps[--Idx] = LdOps[i];
2336 for (--i; i >= 0; --i) {
2337 EVT NewLdTy = LdOps[i].getValueType();
2338 if (NewLdTy != LdTy) {
2339 // Create a larger vector
2340 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2341 &ConcatOps[Idx], End - Idx);
2345 ConcatOps[--Idx] = LdOps[i];
2348 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
2349 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2350 &ConcatOps[Idx], End - Idx);
2352 // We need to fill the rest with undefs to build the vector
2353 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
2354 SmallVector<SDValue, 16> WidenOps(NumOps);
2355 SDValue UndefVal = DAG.getUNDEF(LdTy);
2358 for (; i != End-Idx; ++i)
2359 WidenOps[i] = ConcatOps[Idx+i];
2360 for (; i != NumOps; ++i)
2361 WidenOps[i] = UndefVal;
2363 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
2367 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,
2369 ISD::LoadExtType ExtType) {
2370 // For extension loads, it may not be more efficient to chop up the vector
2371 // and then extended it. Instead, we unroll the load and build a new vector.
2372 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2373 EVT LdVT = LD->getMemoryVT();
2374 DebugLoc dl = LD->getDebugLoc();
2375 assert(LdVT.isVector() && WidenVT.isVector());
2378 SDValue Chain = LD->getChain();
2379 SDValue BasePtr = LD->getBasePtr();
2380 unsigned Align = LD->getAlignment();
2381 bool isVolatile = LD->isVolatile();
2382 bool isNonTemporal = LD->isNonTemporal();
2384 EVT EltVT = WidenVT.getVectorElementType();
2385 EVT LdEltVT = LdVT.getVectorElementType();
2386 unsigned NumElts = LdVT.getVectorNumElements();
2388 // Load each element and widen
2389 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2390 SmallVector<SDValue, 16> Ops(WidenNumElts);
2391 unsigned Increment = LdEltVT.getSizeInBits() / 8;
2392 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
2393 LD->getPointerInfo(),
2394 LdEltVT, isVolatile, isNonTemporal, Align);
2395 LdChain.push_back(Ops[0].getValue(1));
2396 unsigned i = 0, Offset = Increment;
2397 for (i=1; i < NumElts; ++i, Offset += Increment) {
2398 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2399 BasePtr, DAG.getIntPtrConstant(Offset));
2400 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
2401 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
2402 isVolatile, isNonTemporal, Align);
2403 LdChain.push_back(Ops[i].getValue(1));
2406 // Fill the rest with undefs
2407 SDValue UndefVal = DAG.getUNDEF(EltVT);
2408 for (; i != WidenNumElts; ++i)
2411 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
2415 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2417 // The strategy assumes that we can efficiently store powers of two widths.
2418 // The routines chops the vector into the largest vector stores with the same
2419 // element type or scalar stores.
2420 SDValue Chain = ST->getChain();
2421 SDValue BasePtr = ST->getBasePtr();
2422 unsigned Align = ST->getAlignment();
2423 bool isVolatile = ST->isVolatile();
2424 bool isNonTemporal = ST->isNonTemporal();
2425 SDValue ValOp = GetWidenedVector(ST->getValue());
2426 DebugLoc dl = ST->getDebugLoc();
2428 EVT StVT = ST->getMemoryVT();
2429 unsigned StWidth = StVT.getSizeInBits();
2430 EVT ValVT = ValOp.getValueType();
2431 unsigned ValWidth = ValVT.getSizeInBits();
2432 EVT ValEltVT = ValVT.getVectorElementType();
2433 unsigned ValEltWidth = ValEltVT.getSizeInBits();
2434 assert(StVT.getVectorElementType() == ValEltVT);
2436 int Idx = 0; // current index to store
2437 unsigned Offset = 0; // offset from base to store
2438 while (StWidth != 0) {
2439 // Find the largest vector type we can store with
2440 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
2441 unsigned NewVTWidth = NewVT.getSizeInBits();
2442 unsigned Increment = NewVTWidth / 8;
2443 if (NewVT.isVector()) {
2444 unsigned NumVTElts = NewVT.getVectorNumElements();
2446 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2447 DAG.getIntPtrConstant(Idx));
2448 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2449 ST->getPointerInfo().getWithOffset(Offset),
2450 isVolatile, isNonTemporal,
2451 MinAlign(Align, Offset)));
2452 StWidth -= NewVTWidth;
2453 Offset += Increment;
2455 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2456 DAG.getIntPtrConstant(Increment));
2457 } while (StWidth != 0 && StWidth >= NewVTWidth);
2459 // Cast the vector to the scalar type we can store
2460 unsigned NumElts = ValWidth / NewVTWidth;
2461 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2462 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
2463 // Readjust index position based on new vector type
2464 Idx = Idx * ValEltWidth / NewVTWidth;
2466 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2467 DAG.getIntPtrConstant(Idx++));
2468 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2469 ST->getPointerInfo().getWithOffset(Offset),
2470 isVolatile, isNonTemporal,
2471 MinAlign(Align, Offset)));
2472 StWidth -= NewVTWidth;
2473 Offset += Increment;
2474 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2475 DAG.getIntPtrConstant(Increment));
2476 } while (StWidth != 0 && StWidth >= NewVTWidth);
2477 // Restore index back to be relative to the original widen element type
2478 Idx = Idx * NewVTWidth / ValEltWidth;
2484 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,
2486 // For extension loads, it may not be more efficient to truncate the vector
2487 // and then store it. Instead, we extract each element and then store it.
2488 SDValue Chain = ST->getChain();
2489 SDValue BasePtr = ST->getBasePtr();
2490 unsigned Align = ST->getAlignment();
2491 bool isVolatile = ST->isVolatile();
2492 bool isNonTemporal = ST->isNonTemporal();
2493 SDValue ValOp = GetWidenedVector(ST->getValue());
2494 DebugLoc dl = ST->getDebugLoc();
2496 EVT StVT = ST->getMemoryVT();
2497 EVT ValVT = ValOp.getValueType();
2499 // It must be true that we the widen vector type is bigger than where
2500 // we need to store.
2501 assert(StVT.isVector() && ValOp.getValueType().isVector());
2502 assert(StVT.bitsLT(ValOp.getValueType()));
2504 // For truncating stores, we can not play the tricks of chopping legal
2505 // vector types and bit cast it to the right type. Instead, we unroll
2507 EVT StEltVT = StVT.getVectorElementType();
2508 EVT ValEltVT = ValVT.getVectorElementType();
2509 unsigned Increment = ValEltVT.getSizeInBits() / 8;
2510 unsigned NumElts = StVT.getVectorNumElements();
2511 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2512 DAG.getIntPtrConstant(0));
2513 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
2514 ST->getPointerInfo(), StEltVT,
2515 isVolatile, isNonTemporal, Align));
2516 unsigned Offset = Increment;
2517 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
2518 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2519 BasePtr, DAG.getIntPtrConstant(Offset));
2520 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2521 DAG.getIntPtrConstant(0));
2522 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
2523 ST->getPointerInfo().getWithOffset(Offset),
2524 StEltVT, isVolatile, isNonTemporal,
2525 MinAlign(Align, Offset)));
2529 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2530 /// input vector must have the same element type as NVT.
2531 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
2532 // Note that InOp might have been widened so it might already have
2533 // the right width or it might need be narrowed.
2534 EVT InVT = InOp.getValueType();
2535 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2536 "input and widen element type must match");
2537 DebugLoc dl = InOp.getDebugLoc();
2539 // Check if InOp already has the right width.
2543 unsigned InNumElts = InVT.getVectorNumElements();
2544 unsigned WidenNumElts = NVT.getVectorNumElements();
2545 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2546 unsigned NumConcat = WidenNumElts / InNumElts;
2547 SmallVector<SDValue, 16> Ops(NumConcat);
2548 SDValue UndefVal = DAG.getUNDEF(InVT);
2550 for (unsigned i = 1; i != NumConcat; ++i)
2553 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2556 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2557 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2558 DAG.getIntPtrConstant(0));
2560 // Fall back to extract and build.
2561 SmallVector<SDValue, 16> Ops(WidenNumElts);
2562 EVT EltVT = NVT.getVectorElementType();
2563 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2565 for (Idx = 0; Idx < MinNumElts; ++Idx)
2566 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2567 DAG.getIntPtrConstant(Idx));
2569 SDValue UndefVal = DAG.getUNDEF(EltVT);
2570 for ( ; Idx < WidenNumElts; ++Idx)
2571 Ops[Idx] = UndefVal;
2572 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);