1 //===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by James M. Laskey and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple two pass scheduler. The first pass attempts to push
11 // backward any lengthy instructions and critical paths. The second pass packs
12 // instructions into semi-optimal time slots.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "sched"
17 #include "llvm/Type.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
30 /// BuildSchedUnits - Build SUnits from the selection dag that we are input.
31 /// This SUnit graph is similar to the SelectionDAG, but represents flagged
32 /// together nodes with a single SUnit.
33 void ScheduleDAG::BuildSchedUnits() {
34 // Reserve entries in the vector for each of the SUnits we are creating. This
35 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
37 SUnits.reserve(std::distance(DAG.allnodes_begin(), DAG.allnodes_end()));
39 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
41 for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(),
42 E = DAG.allnodes_end(); NI != E; ++NI) {
43 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
46 // If this node has already been processed, stop now.
47 if (SUnitMap[NI]) continue;
49 SUnit *NodeSUnit = NewSUnit(NI);
51 // See if anything is flagged to this node, if so, add them to flagged
52 // nodes. Nodes can have at most one flag input and one flag output. Flags
53 // are required the be the last operand and result of a node.
55 // Scan up, adding flagged preds to FlaggedNodes.
57 if (N->getNumOperands() &&
58 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
60 N = N->getOperand(N->getNumOperands()-1).Val;
61 NodeSUnit->FlaggedNodes.push_back(N);
62 SUnitMap[N] = NodeSUnit;
63 } while (N->getNumOperands() &&
64 N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
65 std::reverse(NodeSUnit->FlaggedNodes.begin(),
66 NodeSUnit->FlaggedNodes.end());
69 // Scan down, adding this node and any flagged succs to FlaggedNodes if they
70 // have a user of the flag operand.
72 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
73 SDOperand FlagVal(N, N->getNumValues()-1);
75 // There are either zero or one users of the Flag result.
76 bool HasFlagUse = false;
77 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
79 if (FlagVal.isOperand(*UI)) {
81 NodeSUnit->FlaggedNodes.push_back(N);
82 SUnitMap[N] = NodeSUnit;
86 if (!HasFlagUse) break;
89 // Now all flagged nodes are in FlaggedNodes and N is the bottom-most node.
92 SUnitMap[N] = NodeSUnit;
94 // Compute the latency for the node. We use the sum of the latencies for
95 // all nodes flagged together into this SUnit.
96 if (InstrItins.isEmpty()) {
97 // No latency information.
98 NodeSUnit->Latency = 1;
100 NodeSUnit->Latency = 0;
101 if (N->isTargetOpcode()) {
102 unsigned SchedClass = TII->getSchedClass(N->getTargetOpcode());
103 InstrStage *S = InstrItins.begin(SchedClass);
104 InstrStage *E = InstrItins.end(SchedClass);
106 NodeSUnit->Latency += S->Cycles;
108 for (unsigned i = 0, e = NodeSUnit->FlaggedNodes.size(); i != e; ++i) {
109 SDNode *FNode = NodeSUnit->FlaggedNodes[i];
110 if (FNode->isTargetOpcode()) {
111 unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode());
112 InstrStage *S = InstrItins.begin(SchedClass);
113 InstrStage *E = InstrItins.end(SchedClass);
115 NodeSUnit->Latency += S->Cycles;
121 // Pass 2: add the preds, succs, etc.
122 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
123 SUnit *SU = &SUnits[su];
124 SDNode *MainNode = SU->Node;
126 if (MainNode->isTargetOpcode()) {
127 unsigned Opc = MainNode->getTargetOpcode();
128 for (unsigned i = 0, ee = TII->getNumOperands(Opc); i != ee; ++i) {
129 if (TII->getOperandConstraint(Opc, i, TOI::TIED_TO) != -1) {
130 SU->isTwoAddress = true;
134 if (TII->isCommutableInstr(Opc))
135 SU->isCommutable = true;
138 // Find all predecessors and successors of the group.
139 // Temporarily add N to make code simpler.
140 SU->FlaggedNodes.push_back(MainNode);
142 for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
143 SDNode *N = SU->FlaggedNodes[n];
145 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
146 SDNode *OpN = N->getOperand(i).Val;
147 if (isPassiveNode(OpN)) continue; // Not scheduled.
148 SUnit *OpSU = SUnitMap[OpN];
149 assert(OpSU && "Node has no SUnit!");
150 if (OpSU == SU) continue; // In the same group.
152 MVT::ValueType OpVT = N->getOperand(i).getValueType();
153 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
154 bool isChain = OpVT == MVT::Other;
156 if (SU->addPred(OpSU, isChain)) {
161 SU->NumChainPredsLeft++;
164 if (OpSU->addSucc(SU, isChain)) {
167 OpSU->NumSuccsLeft++;
169 OpSU->NumChainSuccsLeft++;
175 // Remove MainNode from FlaggedNodes again.
176 SU->FlaggedNodes.pop_back();
182 static void CalculateDepths(SUnit &SU, unsigned Depth) {
183 if (SU.Depth == 0 || Depth > SU.Depth) {
185 for (SUnit::succ_iterator I = SU.Succs.begin(), E = SU.Succs.end();
187 CalculateDepths(*I->first, Depth+1);
191 void ScheduleDAG::CalculateDepths() {
192 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
193 ::CalculateDepths(*Entry, 0U);
194 for (unsigned i = 0, e = SUnits.size(); i != e; ++i)
195 if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
196 ::CalculateDepths(SUnits[i], 0U);
200 static void CalculateHeights(SUnit &SU, unsigned Height) {
201 if (SU.Height == 0 || Height > SU.Height) {
203 for (SUnit::pred_iterator I = SU.Preds.begin(), E = SU.Preds.end();
205 CalculateHeights(*I->first, Height+1);
208 void ScheduleDAG::CalculateHeights() {
209 SUnit *Root = SUnitMap[DAG.getRoot().Val];
210 ::CalculateHeights(*Root, 0U);
213 /// CountResults - The results of target nodes have register or immediate
214 /// operands first, then an optional chain, and optional flag operands (which do
215 /// not go into the machine instrs.)
216 unsigned ScheduleDAG::CountResults(SDNode *Node) {
217 unsigned N = Node->getNumValues();
218 while (N && Node->getValueType(N - 1) == MVT::Flag)
220 if (N && Node->getValueType(N - 1) == MVT::Other)
221 --N; // Skip over chain result.
225 /// CountOperands The inputs to target nodes have any actual inputs first,
226 /// followed by an optional chain operand, then flag operands. Compute the
227 /// number of actual operands that will go into the machine instr.
228 unsigned ScheduleDAG::CountOperands(SDNode *Node) {
229 unsigned N = Node->getNumOperands();
230 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
232 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
233 --N; // Ignore chain if it exists.
237 static const TargetRegisterClass *getInstrOperandRegClass(
238 const MRegisterInfo *MRI,
239 const TargetInstrInfo *TII,
240 const TargetInstrDescriptor *II,
242 if (Op >= II->numOperands) {
243 assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
246 const TargetOperandInfo &toi = II->OpInfo[Op];
247 return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
248 ? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
251 static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI,
255 const TargetInstrInfo *TII,
256 const TargetInstrDescriptor &II) {
257 // Create the result registers for this node and add the result regs to
258 // the machine instruction.
260 RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
261 MI->addRegOperand(ResultReg, true);
262 for (unsigned i = 1; i != NumResults; ++i) {
263 const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
264 assert(RC && "Isn't a register operand!");
265 MI->addRegOperand(RegMap->createVirtualRegister(RC), true);
270 /// getVR - Return the virtual register corresponding to the specified result
271 /// of the specified node.
272 static unsigned getVR(SDOperand Op, DenseMap<SDNode*, unsigned> &VRBaseMap) {
273 DenseMap<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
274 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
275 return I->second + Op.ResNo;
279 /// AddOperand - Add the specified operand to the specified machine instr. II
280 /// specifies the instruction information for the node, and IIOpNum is the
281 /// operand number (in the II) that we are adding. IIOpNum and II are used for
283 void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
285 const TargetInstrDescriptor *II,
286 DenseMap<SDNode*, unsigned> &VRBaseMap) {
287 if (Op.isTargetOpcode()) {
288 // Note that this case is redundant with the final else block, but we
289 // include it because it is the most common and it makes the logic
291 assert(Op.getValueType() != MVT::Other &&
292 Op.getValueType() != MVT::Flag &&
293 "Chain and flag operands should occur at end of operand list!");
295 // Get/emit the operand.
296 unsigned VReg = getVR(Op, VRBaseMap);
297 MI->addRegOperand(VReg, false);
299 // Verify that it is right.
300 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
302 const TargetRegisterClass *RC =
303 getInstrOperandRegClass(MRI, TII, II, IIOpNum);
304 assert(RC && "Don't have operand info for this instruction!");
305 const TargetRegisterClass *VRC = RegMap->getRegClass(VReg);
307 cerr << "Register class of operand and regclass of use don't agree!\n";
309 cerr << "Operand = " << IIOpNum << "\n";
310 cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
311 cerr << "MI = "; MI->print(cerr);
312 cerr << "VReg = " << VReg << "\n";
313 cerr << "VReg RegClass size = " << VRC->getSize()
314 << ", align = " << VRC->getAlignment() << "\n";
315 cerr << "Expected RegClass size = " << RC->getSize()
316 << ", align = " << RC->getAlignment() << "\n";
318 cerr << "Fatal error, aborting.\n";
322 } else if (ConstantSDNode *C =
323 dyn_cast<ConstantSDNode>(Op)) {
324 MI->addImmOperand(C->getValue());
325 } else if (RegisterSDNode *R =
326 dyn_cast<RegisterSDNode>(Op)) {
327 MI->addRegOperand(R->getReg(), false);
328 } else if (GlobalAddressSDNode *TGA =
329 dyn_cast<GlobalAddressSDNode>(Op)) {
330 MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
331 } else if (BasicBlockSDNode *BB =
332 dyn_cast<BasicBlockSDNode>(Op)) {
333 MI->addMachineBasicBlockOperand(BB->getBasicBlock());
334 } else if (FrameIndexSDNode *FI =
335 dyn_cast<FrameIndexSDNode>(Op)) {
336 MI->addFrameIndexOperand(FI->getIndex());
337 } else if (JumpTableSDNode *JT =
338 dyn_cast<JumpTableSDNode>(Op)) {
339 MI->addJumpTableIndexOperand(JT->getIndex());
340 } else if (ConstantPoolSDNode *CP =
341 dyn_cast<ConstantPoolSDNode>(Op)) {
342 int Offset = CP->getOffset();
343 unsigned Align = CP->getAlignment();
344 const Type *Type = CP->getType();
345 // MachineConstantPool wants an explicit alignment.
347 Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
349 // Alignment of vector types. FIXME!
350 Align = TM.getTargetData()->getTypeSize(Type);
351 Align = Log2_64(Align);
356 if (CP->isMachineConstantPoolEntry())
357 Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
359 Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
360 MI->addConstantPoolIndexOperand(Idx, Offset);
361 } else if (ExternalSymbolSDNode *ES =
362 dyn_cast<ExternalSymbolSDNode>(Op)) {
363 MI->addExternalSymbolOperand(ES->getSymbol());
365 assert(Op.getValueType() != MVT::Other &&
366 Op.getValueType() != MVT::Flag &&
367 "Chain and flag operands should occur at end of operand list!");
368 unsigned VReg = getVR(Op, VRBaseMap);
369 MI->addRegOperand(VReg, false);
371 // Verify that it is right.
372 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
374 const TargetRegisterClass *RC =
375 getInstrOperandRegClass(MRI, TII, II, IIOpNum);
376 assert(RC && "Don't have operand info for this instruction!");
377 assert(RegMap->getRegClass(VReg) == RC &&
378 "Register class of operand and regclass of use don't agree!");
384 // Returns the Register Class of a physical register
385 static const TargetRegisterClass *getPhysicalRegisterRegClass(
386 const MRegisterInfo *MRI,
389 assert(MRegisterInfo::isPhysicalRegister(reg) &&
390 "reg must be a physical register");
391 // Pick the register class of the right type that contains this physreg.
392 for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
393 E = MRI->regclass_end(); I != E; ++I)
394 if ((*I)->hasType(VT) && (*I)->contains(reg))
396 assert(false && "Couldn't find the register class");
400 /// EmitNode - Generate machine code for an node and needed dependencies.
402 void ScheduleDAG::EmitNode(SDNode *Node,
403 DenseMap<SDNode*, unsigned> &VRBaseMap) {
404 unsigned VRBase = 0; // First virtual register for node
406 // If machine instruction
407 if (Node->isTargetOpcode()) {
408 unsigned Opc = Node->getTargetOpcode();
409 const TargetInstrDescriptor &II = TII->get(Opc);
411 unsigned NumResults = CountResults(Node);
412 unsigned NodeOperands = CountOperands(Node);
413 unsigned NumMIOperands = NodeOperands + NumResults;
415 assert((unsigned(II.numOperands) == NumMIOperands ||
416 (II.Flags & M_VARIABLE_OPS)) &&
417 "#operands for dag node doesn't match .td file!");
420 // Create the new machine instruction.
421 MachineInstr *MI = new MachineInstr(II);
423 // Add result register values for things that are defined by this
426 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
427 // the CopyToReg'd destination register instead of creating a new vreg.
428 if (NumResults == 1) {
429 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
432 if (Use->getOpcode() == ISD::CopyToReg &&
433 Use->getOperand(2).Val == Node) {
434 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
435 if (MRegisterInfo::isVirtualRegister(Reg)) {
437 MI->addRegOperand(Reg, true);
444 // Otherwise, create new virtual registers.
445 if (NumResults && VRBase == 0)
446 VRBase = CreateVirtualRegisters(MRI, MI, NumResults, RegMap, TII, II);
448 // Emit all of the actual operands of this instruction, adding them to the
449 // instruction as appropriate.
450 for (unsigned i = 0; i != NodeOperands; ++i)
451 AddOperand(MI, Node->getOperand(i), i+NumResults, &II, VRBaseMap);
453 // Commute node if it has been determined to be profitable.
454 if (CommuteSet.count(Node)) {
455 MachineInstr *NewMI = TII->commuteInstruction(MI);
457 DOUT << "Sched: COMMUTING FAILED!\n";
459 DOUT << "Sched: COMMUTED TO: " << *NewMI;
467 // Now that we have emitted all operands, emit this instruction itself.
468 if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
469 BB->insert(BB->end(), MI);
471 // Insert this instruction into the end of the basic block, potentially
472 // taking some custom action.
473 BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
476 switch (Node->getOpcode()) {
481 assert(0 && "This target-independent node should have been selected!");
482 case ISD::EntryToken: // fall thru
483 case ISD::TokenFactor:
486 case ISD::CopyToReg: {
488 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(2)))
491 InReg = getVR(Node->getOperand(2), VRBaseMap);
492 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
493 if (InReg != DestReg) {// Coalesced away the copy?
494 const TargetRegisterClass *TRC = 0;
495 // Get the target register class
496 if (MRegisterInfo::isVirtualRegister(InReg))
497 TRC = RegMap->getRegClass(InReg);
499 TRC = getPhysicalRegisterRegClass(MRI,
500 Node->getOperand(2).getValueType(),
502 MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC);
506 case ISD::CopyFromReg: {
507 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
508 if (MRegisterInfo::isVirtualRegister(SrcReg)) {
509 VRBase = SrcReg; // Just use the input register directly!
513 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
514 // the CopyToReg'd destination register instead of creating a new vreg.
515 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
518 if (Use->getOpcode() == ISD::CopyToReg &&
519 Use->getOperand(2).Val == Node) {
520 unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
521 if (MRegisterInfo::isVirtualRegister(DestReg)) {
528 // Figure out the register class to create for the destreg.
529 const TargetRegisterClass *TRC = 0;
531 TRC = RegMap->getRegClass(VRBase);
533 TRC = getPhysicalRegisterRegClass(MRI, Node->getValueType(0), SrcReg);
535 // Create the reg, emit the copy.
536 VRBase = RegMap->createVirtualRegister(TRC);
538 MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
541 case ISD::INLINEASM: {
542 unsigned NumOps = Node->getNumOperands();
543 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
544 --NumOps; // Ignore the flag operand.
546 // Create the inline asm machine instruction.
548 new MachineInstr(BB, TII->get(TargetInstrInfo::INLINEASM));
550 // Add the asm string as an external symbol operand.
552 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
553 MI->addExternalSymbolOperand(AsmStr);
555 // Add all of the operand registers to the instruction.
556 for (unsigned i = 2; i != NumOps;) {
557 unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
558 unsigned NumVals = Flags >> 3;
560 MI->addImmOperand(Flags);
561 ++i; // Skip the ID value.
564 default: assert(0 && "Bad flags!");
565 case 1: // Use of register.
566 for (; NumVals; --NumVals, ++i) {
567 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
568 MI->addRegOperand(Reg, false);
571 case 2: // Def of register.
572 for (; NumVals; --NumVals, ++i) {
573 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
574 MI->addRegOperand(Reg, true);
577 case 3: { // Immediate.
578 assert(NumVals == 1 && "Unknown immediate value!");
579 if (ConstantSDNode *CS=dyn_cast<ConstantSDNode>(Node->getOperand(i))){
580 MI->addImmOperand(CS->getValue());
582 GlobalAddressSDNode *GA =
583 cast<GlobalAddressSDNode>(Node->getOperand(i));
584 MI->addGlobalAddressOperand(GA->getGlobal(), GA->getOffset());
589 case 4: // Addressing mode.
590 // The addressing mode has been selected, just add all of the
591 // operands to the machine instruction.
592 for (; NumVals; --NumVals, ++i)
593 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
602 assert(!VRBaseMap.count(Node) && "Node emitted out of order - early");
603 VRBaseMap[Node] = VRBase;
606 void ScheduleDAG::EmitNoop() {
607 TII->insertNoop(*BB, BB->end());
610 /// EmitSchedule - Emit the machine code in scheduled order.
611 void ScheduleDAG::EmitSchedule() {
612 // If this is the first basic block in the function, and if it has live ins
613 // that need to be copied into vregs, emit the copies into the top of the
614 // block before emitting the code for the block.
615 MachineFunction &MF = DAG.getMachineFunction();
616 if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) {
617 for (MachineFunction::livein_iterator LI = MF.livein_begin(),
618 E = MF.livein_end(); LI != E; ++LI)
620 MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
621 LI->first, RegMap->getRegClass(LI->second));
625 // Finally, emit the code for all of the scheduled instructions.
626 DenseMap<SDNode*, unsigned> VRBaseMap;
627 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
628 if (SUnit *SU = Sequence[i]) {
629 for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++)
630 EmitNode(SU->FlaggedNodes[j], VRBaseMap);
631 EmitNode(SU->Node, VRBaseMap);
633 // Null SUnit* is a noop.
639 /// dump - dump the schedule.
640 void ScheduleDAG::dumpSchedule() const {
641 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
642 if (SUnit *SU = Sequence[i])
645 cerr << "**** NOOP ****\n";
650 /// Run - perform scheduling.
652 MachineBasicBlock *ScheduleDAG::Run() {
653 TII = TM.getInstrInfo();
654 MRI = TM.getRegisterInfo();
655 RegMap = BB->getParent()->getSSARegMap();
656 ConstPool = BB->getParent()->getConstantPool();
662 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
663 /// a group of nodes flagged together.
664 void SUnit::dump(const SelectionDAG *G) const {
665 cerr << "SU(" << NodeNum << "): ";
668 if (FlaggedNodes.size() != 0) {
669 for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
671 FlaggedNodes[i]->dump(G);
677 void SUnit::dumpAll(const SelectionDAG *G) const {
680 cerr << " # preds left : " << NumPredsLeft << "\n";
681 cerr << " # succs left : " << NumSuccsLeft << "\n";
682 cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
683 cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
684 cerr << " Latency : " << Latency << "\n";
685 cerr << " Depth : " << Depth << "\n";
686 cerr << " Height : " << Height << "\n";
688 if (Preds.size() != 0) {
689 cerr << " Predecessors:\n";
690 for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
696 cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";
699 if (Succs.size() != 0) {
700 cerr << " Successors:\n";
701 for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
707 cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";