1 //===-- ScheduleDAG.cpp - Implement a trivial DAG scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by James M. Laskey and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple two pass scheduler. The first pass attempts to push
11 // backward any lengthy instructions and critical paths. The second pass packs
12 // instructions into semi-optimal time slots.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "sched"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/SelectionDAGISel.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetInstrItineraries.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
32 // Style of scheduling to use.
33 enum ScheduleChoices {
36 simpleNoItinScheduling
40 cl::opt<ScheduleChoices> ScheduleStyle("sched",
41 cl::desc("Choose scheduling style"),
42 cl::init(noScheduling),
44 clEnumValN(noScheduling, "none",
45 "Trivial emission with no analysis"),
46 clEnumValN(simpleScheduling, "simple",
47 "Minimize critical path and maximize processor utilization"),
48 clEnumValN(simpleNoItinScheduling, "simple-noitin",
49 "Same as simple except using generic latency"),
55 ViewDAGs("view-sched-dags", cl::Hidden,
56 cl::desc("Pop up a window to show sched dags as they are processed"));
58 static const bool ViewDAGs = 0;
62 //===----------------------------------------------------------------------===//
64 /// BitsIterator - Provides iteration through individual bits in a bit vector.
69 T Bits; // Bits left to iterate through
73 BitsIterator(T Initial) : Bits(Initial) {}
75 /// Next - Returns the next bit set or zero if exhausted.
77 // Get the rightmost bit set
78 T Result = Bits & -Bits;
81 // Return single bit or zero
86 //===----------------------------------------------------------------------===//
89 //===----------------------------------------------------------------------===//
91 /// ResourceTally - Manages the use of resources over time intervals. Each
92 /// item (slot) in the tally vector represents the resources used at a given
93 /// moment. A bit set to 1 indicates that a resource is in use, otherwise
94 /// available. An assumption is made that the tally is large enough to schedule
95 /// all current instructions (asserts otherwise.)
100 std::vector<T> Tally; // Resources used per slot
101 typedef typename std::vector<T>::iterator Iter;
104 /// SlotsAvailable - Returns true if all units are available.
106 bool SlotsAvailable(Iter Begin, unsigned N, unsigned ResourceSet,
107 unsigned &Resource) {
108 assert(N && "Must check availability with N != 0");
109 // Determine end of interval
110 Iter End = Begin + N;
111 assert(End <= Tally.end() && "Tally is not large enough for schedule");
113 // Iterate thru each resource
114 BitsIterator<T> Resources(ResourceSet & ~*Begin);
115 while (unsigned Res = Resources.Next()) {
116 // Check if resource is available for next N slots
120 if (*Interval & Res) break;
121 } while (Interval != Begin);
123 // If available for N
124 if (Interval == Begin) {
136 /// RetrySlot - Finds a good candidate slot to retry search.
137 Iter RetrySlot(Iter Begin, unsigned N, unsigned ResourceSet) {
138 assert(N && "Must check availability with N != 0");
139 // Determine end of interval
140 Iter End = Begin + N;
141 assert(End <= Tally.end() && "Tally is not large enough for schedule");
143 while (Begin != End--) {
144 // Clear units in use
145 ResourceSet &= ~*End;
146 // If no units left then we should go no further
147 if (!ResourceSet) return End + 1;
149 // Made it all the way through
153 /// FindAndReserveStages - Return true if the stages can be completed. If
155 bool FindAndReserveStages(Iter Begin,
156 InstrStage *Stage, InstrStage *StageEnd) {
157 // If at last stage then we're done
158 if (Stage == StageEnd) return true;
159 // Get number of cycles for current stage
160 unsigned N = Stage->Cycles;
161 // Check to see if N slots are available, if not fail
163 if (!SlotsAvailable(Begin, N, Stage->Units, Resource)) return false;
164 // Check to see if remaining stages are available, if not fail
165 if (!FindAndReserveStages(Begin + N, Stage + 1, StageEnd)) return false;
167 Reserve(Begin, N, Resource);
172 /// Reserve - Mark busy (set) the specified N slots.
173 void Reserve(Iter Begin, unsigned N, unsigned Resource) {
174 // Determine end of interval
175 Iter End = Begin + N;
176 assert(End <= Tally.end() && "Tally is not large enough for schedule");
178 // Set resource bit in each slot
179 for (; Begin < End; Begin++)
183 /// FindSlots - Starting from Begin, locate consecutive slots where all stages
184 /// can be completed. Returns the address of first slot.
185 Iter FindSlots(Iter Begin, InstrStage *StageBegin, InstrStage *StageEnd) {
189 // Try all possible slots forward
191 // Try at cursor, if successful return position.
192 if (FindAndReserveStages(Cursor, StageBegin, StageEnd)) return Cursor;
193 // Locate a better position
194 Cursor = RetrySlot(Cursor + 1, StageBegin->Cycles, StageBegin->Units);
199 /// Initialize - Resize and zero the tally to the specified number of time
201 inline void Initialize(unsigned N) {
202 Tally.assign(N, 0); // Initialize tally to all zeros.
205 // FindAndReserve - Locate an ideal slot for the specified stages and mark
207 unsigned FindAndReserve(unsigned Slot, InstrStage *StageBegin,
208 InstrStage *StageEnd) {
210 Iter Begin = Tally.begin() + Slot;
212 Iter Where = FindSlots(Begin, StageBegin, StageEnd);
213 // Distance is slot number
214 unsigned Final = Where - Tally.begin();
219 //===----------------------------------------------------------------------===//
223 typedef NodeInfo *NodeInfoPtr;
224 typedef std::vector<NodeInfoPtr> NIVector;
225 typedef std::vector<NodeInfoPtr>::iterator NIIterator;
227 //===----------------------------------------------------------------------===//
229 /// Node group - This struct is used to manage flagged node groups.
233 NIVector Members; // Group member nodes
234 NodeInfo *Dominator; // Node with highest latency
235 unsigned Latency; // Total latency of the group
236 int Pending; // Number of visits pending before
241 NodeGroup() : Dominator(NULL), Pending(0) {}
244 inline void setDominator(NodeInfo *D) { Dominator = D; }
245 inline NodeInfo *getDominator() { return Dominator; }
246 inline void setLatency(unsigned L) { Latency = L; }
247 inline unsigned getLatency() { return Latency; }
248 inline int getPending() const { return Pending; }
249 inline void setPending(int P) { Pending = P; }
250 inline int addPending(int I) { return Pending += I; }
253 inline bool group_empty() { return Members.empty(); }
254 inline NIIterator group_begin() { return Members.begin(); }
255 inline NIIterator group_end() { return Members.end(); }
256 inline void group_push_back(const NodeInfoPtr &NI) { Members.push_back(NI); }
257 inline NIIterator group_insert(NIIterator Pos, const NodeInfoPtr &NI) {
258 return Members.insert(Pos, NI);
260 inline void group_insert(NIIterator Pos, NIIterator First, NIIterator Last) {
261 Members.insert(Pos, First, Last);
264 static void Add(NodeInfo *D, NodeInfo *U);
265 static unsigned CountInternalUses(NodeInfo *D, NodeInfo *U);
267 //===----------------------------------------------------------------------===//
270 //===----------------------------------------------------------------------===//
272 /// NodeInfo - This struct tracks information used to schedule the a node.
276 int Pending; // Number of visits pending before
279 SDNode *Node; // DAG node
280 InstrStage *StageBegin; // First stage in itinerary
281 InstrStage *StageEnd; // Last+1 stage in itinerary
282 unsigned Latency; // Total cycles to complete instruction
283 bool IsCall; // Is function call
284 unsigned Slot; // Node's time slot
285 NodeGroup *Group; // Grouping information
286 unsigned VRBase; // Virtual register base
288 unsigned Preorder; // Index before scheduling
292 NodeInfo(SDNode *N = NULL)
308 inline bool isInGroup() const {
309 assert(!Group || !Group->group_empty() && "Group with no members");
310 return Group != NULL;
312 inline bool isGroupDominator() const {
313 return isInGroup() && Group->getDominator() == this;
315 inline int getPending() const {
316 return Group ? Group->getPending() : Pending;
318 inline void setPending(int P) {
319 if (Group) Group->setPending(P);
322 inline int addPending(int I) {
323 if (Group) return Group->addPending(I);
324 else return Pending += I;
327 //===----------------------------------------------------------------------===//
330 //===----------------------------------------------------------------------===//
332 /// NodeGroupIterator - Iterates over all the nodes indicated by the node info.
333 /// If the node is in a group then iterate over the members of the group,
334 /// otherwise just the node info.
336 class NodeGroupIterator {
338 NodeInfo *NI; // Node info
339 NIIterator NGI; // Node group iterator
340 NIIterator NGE; // Node group iterator end
344 NodeGroupIterator(NodeInfo *N) : NI(N) {
345 // If the node is in a group then set up the group iterator. Otherwise
346 // the group iterators will trip first time out.
347 if (N->isInGroup()) {
349 NodeGroup *Group = NI->Group;
350 NGI = Group->group_begin();
351 NGE = Group->group_end();
352 // Prevent this node from being used (will be in members list
357 /// next - Return the next node info, otherwise NULL.
361 if (NGI != NGE) return *NGI++;
362 // Use node as the result (may be NULL)
363 NodeInfo *Result = NI;
366 // Return node or NULL
370 //===----------------------------------------------------------------------===//
373 //===----------------------------------------------------------------------===//
375 /// NodeGroupOpIterator - Iterates over all the operands of a node. If the node
376 /// is a member of a group, this iterates over all the operands of all the
377 /// members of the group.
379 class NodeGroupOpIterator {
381 NodeInfo *NI; // Node containing operands
382 NodeGroupIterator GI; // Node group iterator
383 SDNode::op_iterator OI; // Operand iterator
384 SDNode::op_iterator OE; // Operand iterator end
386 /// CheckNode - Test if node has more operands. If not get the next node
387 /// skipping over nodes that have no operands.
389 // Only if operands are exhausted first
391 // Get next node info
392 NodeInfo *NI = GI.next();
393 // Exit if nodes are exhausted
396 SDNode *Node = NI->Node;
397 // Set up the operand iterators
398 OI = Node->op_begin();
405 NodeGroupOpIterator(NodeInfo *N)
406 : NI(N), GI(N), OI(SDNode::op_iterator()), OE(SDNode::op_iterator()) {}
408 /// isEnd - Returns true when not more operands are available.
410 inline bool isEnd() { CheckNode(); return OI == OE; }
412 /// next - Returns the next available operand.
414 inline SDOperand next() {
415 assert(OI != OE && "Not checking for end of NodeGroupOpIterator correctly");
419 //===----------------------------------------------------------------------===//
422 //===----------------------------------------------------------------------===//
424 /// SimpleSched - Simple two pass scheduler.
428 MachineBasicBlock *BB; // Current basic block
429 SelectionDAG &DAG; // DAG of the current basic block
430 const TargetMachine &TM; // Target processor
431 const TargetInstrInfo &TII; // Target instruction information
432 const MRegisterInfo &MRI; // Target processor register information
433 SSARegMap *RegMap; // Virtual/real register map
434 MachineConstantPool *ConstPool; // Target constant pool
435 unsigned NodeCount; // Number of nodes in DAG
436 bool HasGroups; // True if there are any groups
437 NodeInfo *Info; // Info for nodes being scheduled
438 std::map<SDNode *, NodeInfo *> Map; // Map nodes to info
439 NIVector Ordering; // Emit ordering of nodes
440 ResourceTally<unsigned> Tally; // Resource usage tally
441 unsigned NSlots; // Total latency
442 static const unsigned NotFound = ~0U; // Search marker
447 SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
448 : BB(bb), DAG(D), TM(D.getTarget()), TII(*TM.getInstrInfo()),
449 MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()),
450 ConstPool(BB->getParent()->getConstantPool()),
451 NodeCount(0), HasGroups(false), Info(NULL), Map(), Tally(), NSlots(0) {
452 assert(&TII && "Target doesn't provide instr info?");
453 assert(&MRI && "Target doesn't provide register info?");
456 // Run - perform scheduling.
457 MachineBasicBlock *Run() {
463 /// getNI - Returns the node info for the specified node.
465 inline NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
467 /// getVR - Returns the virtual register number of the node.
469 inline unsigned getVR(SDOperand Op) {
470 NodeInfo *NI = getNI(Op.Val);
471 assert(NI->VRBase != 0 && "Node emitted out of order - late");
472 return NI->VRBase + Op.ResNo;
475 static bool isFlagDefiner(SDNode *A);
476 static bool isFlagUser(SDNode *A);
477 static bool isDefiner(NodeInfo *A, NodeInfo *B);
478 static bool isPassiveNode(SDNode *Node);
479 void IncludeNode(NodeInfo *NI);
482 void IdentifyGroups();
483 void GatherSchedulingInfo();
484 void FakeGroupDominators();
485 void PrepareNodeInfo();
486 bool isStrongDependency(NodeInfo *A, NodeInfo *B);
487 bool isWeakDependency(NodeInfo *A, NodeInfo *B);
488 void ScheduleBackward();
489 void ScheduleForward();
491 void EmitNode(NodeInfo *NI);
492 static unsigned CountResults(SDNode *Node);
493 static unsigned CountOperands(SDNode *Node);
494 unsigned CreateVirtualRegisters(MachineInstr *MI,
496 const TargetInstrDescriptor &II);
498 void printChanges(unsigned Index);
499 void printSI(std::ostream &O, NodeInfo *NI) const;
500 void print(std::ostream &O) const;
501 inline void dump(const char *tag) const { std::cerr << tag; dump(); }
506 //===----------------------------------------------------------------------===//
507 /// Special case itineraries.
510 CallLatency = 40, // To push calls back in time
512 RSInteger = 0xC0000000, // Two integer units
513 RSFloat = 0x30000000, // Two float units
514 RSLoadStore = 0x0C000000, // Two load store units
515 RSBranch = 0x02000000 // One branch unit
517 static InstrStage CallStage = { CallLatency, RSBranch };
518 static InstrStage LoadStage = { 5, RSLoadStore };
519 static InstrStage StoreStage = { 2, RSLoadStore };
520 static InstrStage IntStage = { 2, RSInteger };
521 static InstrStage FloatStage = { 3, RSFloat };
522 //===----------------------------------------------------------------------===//
525 //===----------------------------------------------------------------------===//
529 //===----------------------------------------------------------------------===//
532 //===----------------------------------------------------------------------===//
533 /// Add - Adds a definer and user pair to a node group.
535 void NodeGroup::Add(NodeInfo *D, NodeInfo *U) {
536 // Get current groups
537 NodeGroup *DGroup = D->Group;
538 NodeGroup *UGroup = U->Group;
539 // If both are members of groups
540 if (DGroup && UGroup) {
541 // There may have been another edge connecting
542 if (DGroup == UGroup) return;
543 // Add the pending users count
544 DGroup->addPending(UGroup->getPending());
545 // For each member of the users group
546 NodeGroupIterator UNGI(U);
547 while (NodeInfo *UNI = UNGI.next() ) {
550 // For each member of the definers group
551 NodeGroupIterator DNGI(D);
552 while (NodeInfo *DNI = DNGI.next() ) {
553 // Remove internal edges
554 DGroup->addPending(-CountInternalUses(DNI, UNI));
557 // Merge the two lists
558 DGroup->group_insert(DGroup->group_end(),
559 UGroup->group_begin(), UGroup->group_end());
561 // Make user member of definers group
563 // Add users uses to definers group pending
564 DGroup->addPending(U->Node->use_size());
565 // For each member of the definers group
566 NodeGroupIterator DNGI(D);
567 while (NodeInfo *DNI = DNGI.next() ) {
568 // Remove internal edges
569 DGroup->addPending(-CountInternalUses(DNI, U));
571 DGroup->group_push_back(U);
573 // Make definer member of users group
575 // Add definers uses to users group pending
576 UGroup->addPending(D->Node->use_size());
577 // For each member of the users group
578 NodeGroupIterator UNGI(U);
579 while (NodeInfo *UNI = UNGI.next() ) {
580 // Remove internal edges
581 UGroup->addPending(-CountInternalUses(D, UNI));
583 UGroup->group_insert(UGroup->group_begin(), D);
585 D->Group = U->Group = DGroup = new NodeGroup();
586 DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
587 CountInternalUses(D, U));
588 DGroup->group_push_back(D);
589 DGroup->group_push_back(U);
593 /// CountInternalUses - Returns the number of edges between the two nodes.
595 unsigned NodeGroup::CountInternalUses(NodeInfo *D, NodeInfo *U) {
597 for (unsigned M = U->Node->getNumOperands(); 0 < M--;) {
598 SDOperand Op = U->Node->getOperand(M);
599 if (Op.Val == D->Node) N++;
604 //===----------------------------------------------------------------------===//
607 //===----------------------------------------------------------------------===//
608 /// isFlagDefiner - Returns true if the node defines a flag result.
609 bool SimpleSched::isFlagDefiner(SDNode *A) {
610 unsigned N = A->getNumValues();
611 return N && A->getValueType(N - 1) == MVT::Flag;
614 /// isFlagUser - Returns true if the node uses a flag result.
616 bool SimpleSched::isFlagUser(SDNode *A) {
617 unsigned N = A->getNumOperands();
618 return N && A->getOperand(N - 1).getValueType() == MVT::Flag;
621 /// isDefiner - Return true if node A is a definer for B.
623 bool SimpleSched::isDefiner(NodeInfo *A, NodeInfo *B) {
624 // While there are A nodes
625 NodeGroupIterator NII(A);
626 while (NodeInfo *NI = NII.next()) {
628 SDNode *Node = NI->Node;
629 // While there operands in nodes of B
630 NodeGroupOpIterator NGOI(B);
631 while (!NGOI.isEnd()) {
632 SDOperand Op = NGOI.next();
633 // If node from A defines a node in B
634 if (Node == Op.Val) return true;
640 /// isPassiveNode - Return true if the node is a non-scheduled leaf.
642 bool SimpleSched::isPassiveNode(SDNode *Node) {
643 if (isa<ConstantSDNode>(Node)) return true;
644 if (isa<RegisterSDNode>(Node)) return true;
645 if (isa<GlobalAddressSDNode>(Node)) return true;
646 if (isa<BasicBlockSDNode>(Node)) return true;
647 if (isa<FrameIndexSDNode>(Node)) return true;
648 if (isa<ConstantPoolSDNode>(Node)) return true;
649 if (isa<ExternalSymbolSDNode>(Node)) return true;
653 /// IncludeNode - Add node to NodeInfo vector.
655 void SimpleSched::IncludeNode(NodeInfo *NI) {
657 SDNode *Node = NI->Node;
659 if (Node->getOpcode() == ISD::EntryToken) return;
660 // Check current count for node
661 int Count = NI->getPending();
662 // If the node is already in list
663 if (Count < 0) return;
664 // Decrement count to indicate a visit
666 // If count has gone to zero then add node to list
669 if (NI->isInGroup()) {
670 Ordering.push_back(NI->Group->getDominator());
672 Ordering.push_back(NI);
674 // indicate node has been added
677 // Mark as visited with new count
678 NI->setPending(Count);
681 /// VisitAll - Visit each node breadth-wise to produce an initial ordering.
682 /// Note that the ordering in the Nodes vector is reversed.
683 void SimpleSched::VisitAll() {
684 // Add first element to list
685 Ordering.push_back(getNI(DAG.getRoot().Val));
687 // Iterate through all nodes that have been added
688 for (unsigned i = 0; i < Ordering.size(); i++) { // note: size() varies
689 // Visit all operands
690 NodeGroupOpIterator NGI(Ordering[i]);
691 while (!NGI.isEnd()) {
693 SDOperand Op = NGI.next();
695 SDNode *Node = Op.Val;
696 // Ignore passive nodes
697 if (isPassiveNode(Node)) continue;
699 IncludeNode(getNI(Node));
703 // Add entry node last (IncludeNode filters entry nodes)
704 if (DAG.getEntryNode().Val != DAG.getRoot().Val)
705 Ordering.push_back(getNI(DAG.getEntryNode().Val));
707 // FIXME - Reverse the order
708 for (unsigned i = 0, N = Ordering.size(), Half = N >> 1; i < Half; i++) {
709 unsigned j = N - i - 1;
710 NodeInfo *tmp = Ordering[i];
711 Ordering[i] = Ordering[j];
716 /// IdentifyGroups - Put flagged nodes into groups.
718 void SimpleSched::IdentifyGroups() {
719 for (unsigned i = 0, N = NodeCount; i < N; i++) {
720 NodeInfo* NI = &Info[i];
721 SDNode *Node = NI->Node;
723 // For each operand (in reverse to only look at flags)
724 for (unsigned N = Node->getNumOperands(); 0 < N--;) {
726 SDOperand Op = Node->getOperand(N);
727 // No more flags to walk
728 if (Op.getValueType() != MVT::Flag) break;
730 NodeGroup::Add(getNI(Op.Val), NI);
731 // Let evryone else know
737 /// GatherSchedulingInfo - Get latency and resource information about each node.
739 void SimpleSched::GatherSchedulingInfo() {
740 // Get instruction itineraries for the target
741 const InstrItineraryData InstrItins = TM.getInstrItineraryData();
744 for (unsigned i = 0, N = NodeCount; i < N; i++) {
746 NodeInfo* NI = &Info[i];
747 SDNode *Node = NI->Node;
749 // If there are itineraries and it is a machine instruction
750 if (InstrItins.isEmpty() || ScheduleStyle == simpleNoItinScheduling) {
752 if (Node->isTargetOpcode()) {
753 // Get return type to guess which processing unit
754 MVT::ValueType VT = Node->getValueType(0);
755 // Get machine opcode
756 MachineOpCode TOpc = Node->getTargetOpcode();
757 NI->IsCall = TII.isCall(TOpc);
759 if (TII.isLoad(TOpc)) NI->StageBegin = &LoadStage;
760 else if (TII.isStore(TOpc)) NI->StageBegin = &StoreStage;
761 else if (MVT::isInteger(VT)) NI->StageBegin = &IntStage;
762 else if (MVT::isFloatingPoint(VT)) NI->StageBegin = &FloatStage;
763 if (NI->StageBegin) NI->StageEnd = NI->StageBegin + 1;
765 } else if (Node->isTargetOpcode()) {
766 // get machine opcode
767 MachineOpCode TOpc = Node->getTargetOpcode();
768 // Check to see if it is a call
769 NI->IsCall = TII.isCall(TOpc);
770 // Get itinerary stages for instruction
771 unsigned II = TII.getSchedClass(TOpc);
772 NI->StageBegin = InstrItins.begin(II);
773 NI->StageEnd = InstrItins.end(II);
776 // One slot for the instruction itself
779 // Add long latency for a call to push it back in time
780 if (NI->IsCall) NI->Latency += CallLatency;
782 // Sum up all the latencies
783 for (InstrStage *Stage = NI->StageBegin, *E = NI->StageEnd;
784 Stage != E; Stage++) {
785 NI->Latency += Stage->Cycles;
788 // Sum up all the latencies for max tally size
789 NSlots += NI->Latency;
792 // Unify metrics if in a group
794 for (unsigned i = 0, N = NodeCount; i < N; i++) {
795 NodeInfo* NI = &Info[i];
797 if (NI->isInGroup()) {
798 NodeGroup *Group = NI->Group;
800 if (!Group->getDominator()) {
801 NIIterator NGI = Group->group_begin(), NGE = Group->group_end();
802 NodeInfo *Dominator = *NGI;
803 unsigned Latency = 0;
805 for (NGI++; NGI != NGE; NGI++) {
806 NodeInfo* NGNI = *NGI;
807 Latency += NGNI->Latency;
808 if (Dominator->Latency < NGNI->Latency) Dominator = NGNI;
811 Dominator->Latency = Latency;
812 Group->setDominator(Dominator);
819 /// FakeGroupDominators - Set dominators for non-scheduling.
821 void SimpleSched::FakeGroupDominators() {
822 for (unsigned i = 0, N = NodeCount; i < N; i++) {
823 NodeInfo* NI = &Info[i];
825 if (NI->isInGroup()) {
826 NodeGroup *Group = NI->Group;
828 if (!Group->getDominator()) {
829 Group->setDominator(NI);
835 /// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
837 void SimpleSched::PrepareNodeInfo() {
838 // Allocate node information
839 Info = new NodeInfo[NodeCount];
842 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
843 E = DAG.allnodes_end(); I != E; ++I, ++i) {
844 // Fast reference to node schedule info
845 NodeInfo* NI = &Info[i];
850 // Set pending visit count
851 NI->setPending(I->use_size());
855 /// isStrongDependency - Return true if node A has results used by node B.
856 /// I.E., B must wait for latency of A.
857 bool SimpleSched::isStrongDependency(NodeInfo *A, NodeInfo *B) {
858 // If A defines for B then it's a strong dependency
859 return isDefiner(A, B);
862 /// isWeakDependency Return true if node A produces a result that will
863 /// conflict with operands of B. It is assumed that we have called
864 /// isStrongDependency prior.
865 bool SimpleSched::isWeakDependency(NodeInfo *A, NodeInfo *B) {
866 // TODO check for conflicting real registers and aliases
867 #if 0 // FIXME - Since we are in SSA form and not checking register aliasing
868 return A->Node->getOpcode() == ISD::EntryToken || isStrongDependency(B, A);
870 return A->Node->getOpcode() == ISD::EntryToken;
874 /// ScheduleBackward - Schedule instructions so that any long latency
875 /// instructions and the critical path get pushed back in time. Time is run in
876 /// reverse to allow code reuse of the Tally and eliminate the overhead of
877 /// biasing every slot indices against NSlots.
878 void SimpleSched::ScheduleBackward() {
879 // Size and clear the resource tally
880 Tally.Initialize(NSlots);
881 // Get number of nodes to schedule
882 unsigned N = Ordering.size();
884 // For each node being scheduled
885 for (unsigned i = N; 0 < i--;) {
886 NodeInfo *NI = Ordering[i];
888 unsigned Slot = NotFound;
890 // Compare against those previously scheduled nodes
893 // Get following instruction
894 NodeInfo *Other = Ordering[j];
896 // Check dependency against previously inserted nodes
897 if (isStrongDependency(NI, Other)) {
898 Slot = Other->Slot + Other->Latency;
900 } else if (isWeakDependency(NI, Other)) {
906 // If independent of others (or first entry)
907 if (Slot == NotFound) Slot = 0;
909 #if 0 // FIXME - measure later
910 // Find a slot where the needed resources are available
911 if (NI->StageBegin != NI->StageEnd)
912 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
918 // Insert sort based on slot
921 // Get following instruction
922 NodeInfo *Other = Ordering[j];
923 // Should we look further (remember slots are in reverse time)
924 if (Slot >= Other->Slot) break;
925 // Shuffle other into ordering
926 Ordering[j - 1] = Other;
928 // Insert node in proper slot
929 if (j != i + 1) Ordering[j - 1] = NI;
933 /// ScheduleForward - Schedule instructions to maximize packing.
935 void SimpleSched::ScheduleForward() {
936 // Size and clear the resource tally
937 Tally.Initialize(NSlots);
938 // Get number of nodes to schedule
939 unsigned N = Ordering.size();
941 // For each node being scheduled
942 for (unsigned i = 0; i < N; i++) {
943 NodeInfo *NI = Ordering[i];
945 unsigned Slot = NotFound;
947 // Compare against those previously scheduled nodes
950 // Get following instruction
951 NodeInfo *Other = Ordering[j];
953 // Check dependency against previously inserted nodes
954 if (isStrongDependency(Other, NI)) {
955 Slot = Other->Slot + Other->Latency;
957 } else if (Other->IsCall || isWeakDependency(Other, NI)) {
963 // If independent of others (or first entry)
964 if (Slot == NotFound) Slot = 0;
966 // Find a slot where the needed resources are available
967 if (NI->StageBegin != NI->StageEnd)
968 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
973 // Insert sort based on slot
976 // Get prior instruction
977 NodeInfo *Other = Ordering[j];
978 // Should we look further
979 if (Slot >= Other->Slot) break;
980 // Shuffle other into ordering
981 Ordering[j + 1] = Other;
983 // Insert node in proper slot
984 if (j != i) Ordering[j + 1] = NI;
988 /// EmitAll - Emit all nodes in schedule sorted order.
990 void SimpleSched::EmitAll() {
991 // For each node in the ordering
992 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
993 // Get the scheduling info
994 NodeInfo *NI = Ordering[i];
995 // Iterate through nodes
996 NodeGroupIterator NGI(Ordering[i]);
997 if (NI->isInGroup()) {
998 if (NI->isGroupDominator()) {
999 NodeGroupIterator NGI(Ordering[i]);
1000 while (NodeInfo *NI = NGI.next()) EmitNode(NI);
1008 /// CountResults - The results of target nodes have register or immediate
1009 /// operands first, then an optional chain, and optional flag operands (which do
1010 /// not go into the machine instrs.)
1011 unsigned SimpleSched::CountResults(SDNode *Node) {
1012 unsigned N = Node->getNumValues();
1013 while (N && Node->getValueType(N - 1) == MVT::Flag)
1015 if (N && Node->getValueType(N - 1) == MVT::Other)
1016 --N; // Skip over chain result.
1020 /// CountOperands The inputs to target nodes have any actual inputs first,
1021 /// followed by an optional chain operand, then flag operands. Compute the
1022 /// number of actual operands that will go into the machine instr.
1023 unsigned SimpleSched::CountOperands(SDNode *Node) {
1024 unsigned N = Node->getNumOperands();
1025 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
1027 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
1028 --N; // Ignore chain if it exists.
1032 /// CreateVirtualRegisters - Add result register values for things that are
1033 /// defined by this instruction.
1034 unsigned SimpleSched::CreateVirtualRegisters(MachineInstr *MI,
1035 unsigned NumResults,
1036 const TargetInstrDescriptor &II) {
1037 // Create the result registers for this node and add the result regs to
1038 // the machine instruction.
1039 const TargetOperandInfo *OpInfo = II.OpInfo;
1040 unsigned ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
1041 MI->addRegOperand(ResultReg, MachineOperand::Def);
1042 for (unsigned i = 1; i != NumResults; ++i) {
1043 assert(OpInfo[i].RegClass && "Isn't a register operand!");
1044 MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[i].RegClass),
1045 MachineOperand::Def);
1050 /// EmitNode - Generate machine code for an node and needed dependencies.
1052 void SimpleSched::EmitNode(NodeInfo *NI) {
1053 unsigned VRBase = 0; // First virtual register for node
1054 SDNode *Node = NI->Node;
1056 // If machine instruction
1057 if (Node->isTargetOpcode()) {
1058 unsigned Opc = Node->getTargetOpcode();
1059 const TargetInstrDescriptor &II = TII.get(Opc);
1061 unsigned NumResults = CountResults(Node);
1062 unsigned NodeOperands = CountOperands(Node);
1063 unsigned NumMIOperands = NodeOperands + NumResults;
1065 assert((unsigned(II.numOperands) == NumMIOperands || II.numOperands == -1)&&
1066 "#operands for dag node doesn't match .td file!");
1069 // Create the new machine instruction.
1070 MachineInstr *MI = new MachineInstr(Opc, NumMIOperands, true, true);
1072 // Add result register values for things that are defined by this
1075 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
1076 // the CopyToReg'd destination register instead of creating a new vreg.
1077 if (NumResults == 1) {
1078 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
1081 if (Use->getOpcode() == ISD::CopyToReg &&
1082 Use->getOperand(2).Val == Node) {
1083 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
1084 if (MRegisterInfo::isVirtualRegister(Reg)) {
1086 MI->addRegOperand(Reg, MachineOperand::Def);
1093 // Otherwise, create new virtual registers.
1094 if (NumResults && VRBase == 0)
1095 VRBase = CreateVirtualRegisters(MI, NumResults, II);
1097 // Emit all of the actual operands of this instruction, adding them to the
1098 // instruction as appropriate.
1099 for (unsigned i = 0; i != NodeOperands; ++i) {
1100 if (Node->getOperand(i).isTargetOpcode()) {
1101 // Note that this case is redundant with the final else block, but we
1102 // include it because it is the most common and it makes the logic
1104 assert(Node->getOperand(i).getValueType() != MVT::Other &&
1105 Node->getOperand(i).getValueType() != MVT::Flag &&
1106 "Chain and flag operands should occur at end of operand list!");
1108 // Get/emit the operand.
1109 unsigned VReg = getVR(Node->getOperand(i));
1110 MI->addRegOperand(VReg, MachineOperand::Use);
1112 // Verify that it is right.
1113 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
1114 assert(II.OpInfo[i+NumResults].RegClass &&
1115 "Don't have operand info for this instruction!");
1116 assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
1117 "Register class of operand and regclass of use don't agree!");
1118 } else if (ConstantSDNode *C =
1119 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1120 MI->addZeroExtImm64Operand(C->getValue());
1121 } else if (RegisterSDNode*R =
1122 dyn_cast<RegisterSDNode>(Node->getOperand(i))) {
1123 MI->addRegOperand(R->getReg(), MachineOperand::Use);
1124 } else if (GlobalAddressSDNode *TGA =
1125 dyn_cast<GlobalAddressSDNode>(Node->getOperand(i))) {
1126 MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
1127 } else if (BasicBlockSDNode *BB =
1128 dyn_cast<BasicBlockSDNode>(Node->getOperand(i))) {
1129 MI->addMachineBasicBlockOperand(BB->getBasicBlock());
1130 } else if (FrameIndexSDNode *FI =
1131 dyn_cast<FrameIndexSDNode>(Node->getOperand(i))) {
1132 MI->addFrameIndexOperand(FI->getIndex());
1133 } else if (ConstantPoolSDNode *CP =
1134 dyn_cast<ConstantPoolSDNode>(Node->getOperand(i))) {
1135 unsigned Idx = ConstPool->getConstantPoolIndex(CP->get());
1136 MI->addConstantPoolIndexOperand(Idx);
1137 } else if (ExternalSymbolSDNode *ES =
1138 dyn_cast<ExternalSymbolSDNode>(Node->getOperand(i))) {
1139 MI->addExternalSymbolOperand(ES->getSymbol(), false);
1141 assert(Node->getOperand(i).getValueType() != MVT::Other &&
1142 Node->getOperand(i).getValueType() != MVT::Flag &&
1143 "Chain and flag operands should occur at end of operand list!");
1144 unsigned VReg = getVR(Node->getOperand(i));
1145 MI->addRegOperand(VReg, MachineOperand::Use);
1147 // Verify that it is right.
1148 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
1149 assert(II.OpInfo[i+NumResults].RegClass &&
1150 "Don't have operand info for this instruction!");
1151 assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
1152 "Register class of operand and regclass of use don't agree!");
1156 // Now that we have emitted all operands, emit this instruction itself.
1157 if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
1158 BB->insert(BB->end(), MI);
1160 // Insert this instruction into the end of the basic block, potentially
1161 // taking some custom action.
1162 BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
1165 switch (Node->getOpcode()) {
1168 assert(0 && "This target-independent node should have been selected!");
1169 case ISD::EntryToken: // fall thru
1170 case ISD::TokenFactor:
1172 case ISD::CopyToReg: {
1173 unsigned InReg = getVR(Node->getOperand(2));
1174 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1175 if (InReg != DestReg) // Coallesced away the copy?
1176 MRI.copyRegToReg(*BB, BB->end(), DestReg, InReg,
1177 RegMap->getRegClass(InReg));
1180 case ISD::CopyFromReg: {
1181 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1182 if (MRegisterInfo::isVirtualRegister(SrcReg)) {
1183 VRBase = SrcReg; // Just use the input register directly!
1187 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
1188 // the CopyToReg'd destination register instead of creating a new vreg.
1189 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
1192 if (Use->getOpcode() == ISD::CopyToReg &&
1193 Use->getOperand(2).Val == Node) {
1194 unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
1195 if (MRegisterInfo::isVirtualRegister(DestReg)) {
1202 // Figure out the register class to create for the destreg.
1203 const TargetRegisterClass *TRC = 0;
1205 TRC = RegMap->getRegClass(VRBase);
1208 // Pick the register class of the right type that contains this physreg.
1209 for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
1210 E = MRI.regclass_end(); I != E; ++I)
1211 if ((*I)->hasType(Node->getValueType(0)) &&
1212 (*I)->contains(SrcReg)) {
1216 assert(TRC && "Couldn't find register class for reg copy!");
1218 // Create the reg, emit the copy.
1219 VRBase = RegMap->createVirtualRegister(TRC);
1221 MRI.copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
1227 assert(NI->VRBase == 0 && "Node emitted out of order - early");
1228 NI->VRBase = VRBase;
1231 /// Schedule - Order nodes according to selected style.
1233 void SimpleSched::Schedule() {
1235 NodeCount = std::distance(DAG.allnodes_begin(), DAG.allnodes_end());
1236 // Test to see if scheduling should occur
1237 bool ShouldSchedule = NodeCount > 3 && ScheduleStyle != noScheduling;
1238 // Set up minimum info for scheduling
1240 // Construct node groups for flagged nodes
1243 // Don't waste time if is only entry and return
1244 if (ShouldSchedule) {
1245 // Get latency and resource requirements
1246 GatherSchedulingInfo();
1247 } else if (HasGroups) {
1248 // Make sure all the groups have dominators
1249 FakeGroupDominators();
1252 // Breadth first walk of DAG
1256 static unsigned Count = 0;
1258 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
1259 NodeInfo *NI = Ordering[i];
1264 // Don't waste time if is only entry and return
1265 if (ShouldSchedule) {
1266 // Push back long instructions and critical path
1269 // Pack instructions to maximize resource utilization
1273 DEBUG(printChanges(Count));
1275 // Emit in scheduled order
1279 /// printChanges - Hilight changes in order caused by scheduling.
1281 void SimpleSched::printChanges(unsigned Index) {
1283 // Get the ordered node count
1284 unsigned N = Ordering.size();
1285 // Determine if any changes
1287 for (; i < N; i++) {
1288 NodeInfo *NI = Ordering[i];
1289 if (NI->Preorder != i) break;
1293 std::cerr << Index << ". New Ordering\n";
1295 for (i = 0; i < N; i++) {
1296 NodeInfo *NI = Ordering[i];
1297 std::cerr << " " << NI->Preorder << ". ";
1298 printSI(std::cerr, NI);
1300 if (NI->isGroupDominator()) {
1301 NodeGroup *Group = NI->Group;
1302 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
1305 printSI(std::cerr, *NII);
1311 std::cerr << Index << ". No Changes\n";
1316 /// printSI - Print schedule info.
1318 void SimpleSched::printSI(std::ostream &O, NodeInfo *NI) const {
1320 SDNode *Node = NI->Node;
1322 << std::hex << Node << std::dec
1323 << ", Lat=" << NI->Latency
1324 << ", Slot=" << NI->Slot
1325 << ", ARITY=(" << Node->getNumOperands() << ","
1326 << Node->getNumValues() << ")"
1327 << " " << Node->getOperationName(&DAG);
1328 if (isFlagDefiner(Node)) O << "<#";
1329 if (isFlagUser(Node)) O << ">#";
1333 /// print - Print ordering to specified output stream.
1335 void SimpleSched::print(std::ostream &O) const {
1337 using namespace std;
1339 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
1340 NodeInfo *NI = Ordering[i];
1343 if (NI->isGroupDominator()) {
1344 NodeGroup *Group = NI->Group;
1345 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
1356 /// dump - Print ordering to std::cerr.
1358 void SimpleSched::dump() const {
1361 //===----------------------------------------------------------------------===//
1364 //===----------------------------------------------------------------------===//
1365 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
1366 /// target node in the graph.
1367 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &SD) {
1368 if (ViewDAGs) SD.viewGraph();
1369 BB = SimpleSched(SD, BB).Run();