1 //===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple two pass scheduler. The first pass attempts to push
11 // backward any lengthy instructions and critical paths. The second pass packs
12 // instructions into semi-optimal time slots.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "pre-RA-sched"
17 #include "llvm/Type.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
33 STATISTIC(NumCommutes, "Number of instructions commuted");
37 SchedLiveInCopies("schedule-livein-copies",
38 cl::desc("Schedule copies of livein registers"),
42 ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
43 const TargetMachine &tm)
44 : DAG(dag), BB(bb), TM(tm), MRI(BB->getParent()->getRegInfo()) {
45 TII = TM.getInstrInfo();
46 MF = &DAG.getMachineFunction();
47 TRI = TM.getRegisterInfo();
48 TLI = &DAG.getTargetLoweringInfo();
49 ConstPool = BB->getParent()->getConstantPool();
52 /// CheckForPhysRegDependency - Check if the dependency between def and use of
53 /// a specified operand is a physical register dependency. If so, returns the
54 /// register and the cost of copying the register.
55 static void CheckForPhysRegDependency(SDNode *Def, SDNode *Use, unsigned Op,
56 const TargetRegisterInfo *TRI,
57 const TargetInstrInfo *TII,
58 unsigned &PhysReg, int &Cost) {
59 if (Op != 2 || Use->getOpcode() != ISD::CopyToReg)
62 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
63 if (TargetRegisterInfo::isVirtualRegister(Reg))
66 unsigned ResNo = Use->getOperand(2).ResNo;
67 if (Def->isTargetOpcode()) {
68 const TargetInstrDesc &II = TII->get(Def->getTargetOpcode());
69 if (ResNo >= II.getNumDefs() &&
70 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
72 const TargetRegisterClass *RC =
73 TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo));
74 Cost = RC->getCopyCost();
79 SUnit *ScheduleDAG::Clone(SUnit *Old) {
80 SUnit *SU = NewSUnit(Old->Node);
81 SU->OrigNode = Old->OrigNode;
82 SU->FlaggedNodes = Old->FlaggedNodes;
83 SU->Latency = Old->Latency;
84 SU->isTwoAddress = Old->isTwoAddress;
85 SU->isCommutable = Old->isCommutable;
86 SU->hasPhysRegDefs = Old->hasPhysRegDefs;
91 /// BuildSchedUnits - Build SUnits from the selection dag that we are input.
92 /// This SUnit graph is similar to the SelectionDAG, but represents flagged
93 /// together nodes with a single SUnit.
94 void ScheduleDAG::BuildSchedUnits() {
95 // Reserve entries in the vector for each of the SUnits we are creating. This
96 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
98 SUnits.reserve(DAG.allnodes_size());
100 // During scheduling, the NodeId field of SDNode is used to map SDNodes
101 // to their associated SUnits by holding SUnits table indices. A value
102 // of -1 means the SDNode does not yet have an associated SUnit.
103 for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(),
104 E = DAG.allnodes_end(); NI != E; ++NI)
107 for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(),
108 E = DAG.allnodes_end(); NI != E; ++NI) {
109 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
112 // If this node has already been processed, stop now.
113 if (NI->getNodeId() != -1) continue;
115 SUnit *NodeSUnit = NewSUnit(NI);
117 // See if anything is flagged to this node, if so, add them to flagged
118 // nodes. Nodes can have at most one flag input and one flag output. Flags
119 // are required the be the last operand and result of a node.
121 // Scan up, adding flagged preds to FlaggedNodes.
123 if (N->getNumOperands() &&
124 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
126 N = N->getOperand(N->getNumOperands()-1).Val;
127 NodeSUnit->FlaggedNodes.push_back(N);
128 assert(N->getNodeId() == -1 && "Node already inserted!");
129 N->setNodeId(NodeSUnit->NodeNum);
130 } while (N->getNumOperands() &&
131 N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
132 std::reverse(NodeSUnit->FlaggedNodes.begin(),
133 NodeSUnit->FlaggedNodes.end());
136 // Scan down, adding this node and any flagged succs to FlaggedNodes if they
137 // have a user of the flag operand.
139 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
140 SDOperand FlagVal(N, N->getNumValues()-1);
142 // There are either zero or one users of the Flag result.
143 bool HasFlagUse = false;
144 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
146 if (FlagVal.isOperandOf(UI->getUser())) {
148 NodeSUnit->FlaggedNodes.push_back(N);
149 assert(N->getNodeId() == -1 && "Node already inserted!");
150 N->setNodeId(NodeSUnit->NodeNum);
154 if (!HasFlagUse) break;
157 // Now all flagged nodes are in FlaggedNodes and N is the bottom-most node.
160 assert(N->getNodeId() == -1 && "Node already inserted!");
161 N->setNodeId(NodeSUnit->NodeNum);
163 ComputeLatency(NodeSUnit);
166 // Pass 2: add the preds, succs, etc.
167 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
168 SUnit *SU = &SUnits[su];
169 SDNode *MainNode = SU->Node;
171 if (MainNode->isTargetOpcode()) {
172 unsigned Opc = MainNode->getTargetOpcode();
173 const TargetInstrDesc &TID = TII->get(Opc);
174 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
175 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
176 SU->isTwoAddress = true;
180 if (TID.isCommutable())
181 SU->isCommutable = true;
184 // Find all predecessors and successors of the group.
185 // Temporarily add N to make code simpler.
186 SU->FlaggedNodes.push_back(MainNode);
188 for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
189 SDNode *N = SU->FlaggedNodes[n];
190 if (N->isTargetOpcode() &&
191 TII->get(N->getTargetOpcode()).getImplicitDefs() &&
192 CountResults(N) > TII->get(N->getTargetOpcode()).getNumDefs())
193 SU->hasPhysRegDefs = true;
195 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
196 SDNode *OpN = N->getOperand(i).Val;
197 if (isPassiveNode(OpN)) continue; // Not scheduled.
198 SUnit *OpSU = &SUnits[OpN->getNodeId()];
199 assert(OpSU && "Node has no SUnit!");
200 if (OpSU == SU) continue; // In the same group.
202 MVT OpVT = N->getOperand(i).getValueType();
203 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
204 bool isChain = OpVT == MVT::Other;
206 unsigned PhysReg = 0;
208 // Determine if this is a physical register dependency.
209 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
210 SU->addPred(OpSU, isChain, false, PhysReg, Cost);
214 // Remove MainNode from FlaggedNodes again.
215 SU->FlaggedNodes.pop_back();
219 void ScheduleDAG::ComputeLatency(SUnit *SU) {
220 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
222 // Compute the latency for the node. We use the sum of the latencies for
223 // all nodes flagged together into this SUnit.
224 if (InstrItins.isEmpty()) {
225 // No latency information.
229 if (SU->Node->isTargetOpcode()) {
230 unsigned SchedClass =
231 TII->get(SU->Node->getTargetOpcode()).getSchedClass();
232 const InstrStage *S = InstrItins.begin(SchedClass);
233 const InstrStage *E = InstrItins.end(SchedClass);
235 SU->Latency += S->Cycles;
237 for (unsigned i = 0, e = SU->FlaggedNodes.size(); i != e; ++i) {
238 SDNode *FNode = SU->FlaggedNodes[i];
239 if (FNode->isTargetOpcode()) {
240 unsigned SchedClass =TII->get(FNode->getTargetOpcode()).getSchedClass();
241 const InstrStage *S = InstrItins.begin(SchedClass);
242 const InstrStage *E = InstrItins.end(SchedClass);
244 SU->Latency += S->Cycles;
250 /// CalculateDepths - compute depths using algorithms for the longest
252 void ScheduleDAG::CalculateDepths() {
253 unsigned DAGSize = SUnits.size();
254 std::vector<unsigned> InDegree(DAGSize);
255 std::vector<SUnit*> WorkList;
256 WorkList.reserve(DAGSize);
258 // Initialize the data structures
259 for (unsigned i = 0, e = DAGSize; i != e; ++i) {
260 SUnit *SU = &SUnits[i];
261 int NodeNum = SU->NodeNum;
262 unsigned Degree = SU->Preds.size();
263 InDegree[NodeNum] = Degree;
266 // Is it a node without dependencies?
268 assert(SU->Preds.empty() && "SUnit should have no predecessors");
269 // Collect leaf nodes
270 WorkList.push_back(SU);
274 // Process nodes in the topological order
275 while (!WorkList.empty()) {
276 SUnit *SU = WorkList.back();
278 unsigned &SUDepth = SU->Depth;
280 // Use dynamic programming:
281 // When current node is being processed, all of its dependencies
282 // are already processed.
283 // So, just iterate over all predecessors and take the longest path
284 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
286 unsigned PredDepth = I->Dep->Depth;
287 if (PredDepth+1 > SUDepth) {
288 SUDepth = PredDepth + 1;
292 // Update InDegrees of all nodes depending on current SUnit
293 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
296 if (!--InDegree[SU->NodeNum])
297 // If all dependencies of the node are processed already,
298 // then the longest path for the node can be computed now
299 WorkList.push_back(SU);
304 /// CalculateHeights - compute heights using algorithms for the longest
306 void ScheduleDAG::CalculateHeights() {
307 unsigned DAGSize = SUnits.size();
308 std::vector<unsigned> InDegree(DAGSize);
309 std::vector<SUnit*> WorkList;
310 WorkList.reserve(DAGSize);
312 // Initialize the data structures
313 for (unsigned i = 0, e = DAGSize; i != e; ++i) {
314 SUnit *SU = &SUnits[i];
315 int NodeNum = SU->NodeNum;
316 unsigned Degree = SU->Succs.size();
317 InDegree[NodeNum] = Degree;
320 // Is it a node without dependencies?
322 assert(SU->Succs.empty() && "Something wrong");
323 assert(WorkList.empty() && "Should be empty");
324 // Collect leaf nodes
325 WorkList.push_back(SU);
329 // Process nodes in the topological order
330 while (!WorkList.empty()) {
331 SUnit *SU = WorkList.back();
333 unsigned &SUHeight = SU->Height;
335 // Use dynamic programming:
336 // When current node is being processed, all of its dependencies
337 // are already processed.
338 // So, just iterate over all successors and take the longest path
339 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
341 unsigned SuccHeight = I->Dep->Height;
342 if (SuccHeight+1 > SUHeight) {
343 SUHeight = SuccHeight + 1;
347 // Update InDegrees of all nodes depending on current SUnit
348 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
351 if (!--InDegree[SU->NodeNum])
352 // If all dependencies of the node are processed already,
353 // then the longest path for the node can be computed now
354 WorkList.push_back(SU);
359 /// CountResults - The results of target nodes have register or immediate
360 /// operands first, then an optional chain, and optional flag operands (which do
361 /// not go into the resulting MachineInstr).
362 unsigned ScheduleDAG::CountResults(SDNode *Node) {
363 unsigned N = Node->getNumValues();
364 while (N && Node->getValueType(N - 1) == MVT::Flag)
366 if (N && Node->getValueType(N - 1) == MVT::Other)
367 --N; // Skip over chain result.
371 /// CountOperands - The inputs to target nodes have any actual inputs first,
372 /// followed by special operands that describe memory references, then an
373 /// optional chain operand, then flag operands. Compute the number of
374 /// actual operands that will go into the resulting MachineInstr.
375 unsigned ScheduleDAG::CountOperands(SDNode *Node) {
376 unsigned N = ComputeMemOperandsEnd(Node);
377 while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).Val))
378 --N; // Ignore MEMOPERAND nodes
382 /// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode
384 unsigned ScheduleDAG::ComputeMemOperandsEnd(SDNode *Node) {
385 unsigned N = Node->getNumOperands();
386 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
388 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
389 --N; // Ignore chain if it exists.
393 static const TargetRegisterClass *getInstrOperandRegClass(
394 const TargetRegisterInfo *TRI,
395 const TargetInstrInfo *TII,
396 const TargetInstrDesc &II,
398 if (Op >= II.getNumOperands()) {
399 assert(II.isVariadic() && "Invalid operand # of instruction");
402 if (II.OpInfo[Op].isLookupPtrRegClass())
403 return TII->getPointerRegClass();
404 return TRI->getRegClass(II.OpInfo[Op].RegClass);
407 void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
408 bool IsClone, unsigned SrcReg,
409 DenseMap<SDOperand, unsigned> &VRBaseMap) {
411 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
412 // Just use the input register directly!
414 VRBaseMap.erase(SDOperand(Node, ResNo));
415 bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo),SrcReg));
416 isNew = isNew; // Silence compiler warning.
417 assert(isNew && "Node emitted out of order - early");
421 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
422 // the CopyToReg'd destination register instead of creating a new vreg.
423 bool MatchReg = true;
424 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
426 SDNode *Use = UI->getUser();
428 if (Use->getOpcode() == ISD::CopyToReg &&
429 Use->getOperand(2).Val == Node &&
430 Use->getOperand(2).ResNo == ResNo) {
431 unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
432 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
435 } else if (DestReg != SrcReg)
438 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
439 SDOperand Op = Use->getOperand(i);
440 if (Op.Val != Node || Op.ResNo != ResNo)
442 MVT VT = Node->getValueType(Op.ResNo);
443 if (VT != MVT::Other && VT != MVT::Flag)
452 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
453 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, Node->getValueType(ResNo));
455 // Figure out the register class to create for the destreg.
457 DstRC = MRI.getRegClass(VRBase);
459 DstRC = TLI->getRegClassFor(Node->getValueType(ResNo));
462 // If all uses are reading from the src physical register and copying the
463 // register is either impossible or very expensive, then don't create a copy.
464 if (MatchReg && SrcRC->getCopyCost() < 0) {
467 // Create the reg, emit the copy.
468 VRBase = MRI.createVirtualRegister(DstRC);
469 TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
473 VRBaseMap.erase(SDOperand(Node, ResNo));
474 bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo), VRBase));
475 isNew = isNew; // Silence compiler warning.
476 assert(isNew && "Node emitted out of order - early");
479 /// getDstOfCopyToRegUse - If the only use of the specified result number of
480 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
481 unsigned ScheduleDAG::getDstOfOnlyCopyToRegUse(SDNode *Node,
482 unsigned ResNo) const {
483 if (!Node->hasOneUse())
486 SDNode *Use = Node->use_begin()->getUser();
487 if (Use->getOpcode() == ISD::CopyToReg &&
488 Use->getOperand(2).Val == Node &&
489 Use->getOperand(2).ResNo == ResNo) {
490 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
491 if (TargetRegisterInfo::isVirtualRegister(Reg))
497 void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
498 const TargetInstrDesc &II,
499 DenseMap<SDOperand, unsigned> &VRBaseMap) {
500 assert(Node->getTargetOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
501 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
503 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
504 // If the specific node value is only used by a CopyToReg and the dest reg
505 // is a vreg, use the CopyToReg'd destination register instead of creating
508 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
510 SDNode *Use = UI->getUser();
511 if (Use->getOpcode() == ISD::CopyToReg &&
512 Use->getOperand(2).Val == Node &&
513 Use->getOperand(2).ResNo == i) {
514 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
515 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
517 MI->addOperand(MachineOperand::CreateReg(Reg, true));
523 // Create the result registers for this node and add the result regs to
524 // the machine instruction.
526 const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
527 assert(RC && "Isn't a register operand!");
528 VRBase = MRI.createVirtualRegister(RC);
529 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
532 bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase));
533 isNew = isNew; // Silence compiler warning.
534 assert(isNew && "Node emitted out of order - early");
538 /// getVR - Return the virtual register corresponding to the specified result
539 /// of the specified node.
540 unsigned ScheduleDAG::getVR(SDOperand Op,
541 DenseMap<SDOperand, unsigned> &VRBaseMap) {
542 if (Op.isTargetOpcode() &&
543 Op.getTargetOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
544 // Add an IMPLICIT_DEF instruction before every use.
545 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.Val, Op.ResNo);
546 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
547 // does not include operand register class info.
549 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
550 VReg = MRI.createVirtualRegister(RC);
552 BuildMI(BB, TII->get(TargetInstrInfo::IMPLICIT_DEF), VReg);
556 DenseMap<SDOperand, unsigned>::iterator I = VRBaseMap.find(Op);
557 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
562 /// AddOperand - Add the specified operand to the specified machine instr. II
563 /// specifies the instruction information for the node, and IIOpNum is the
564 /// operand number (in the II) that we are adding. IIOpNum and II are used for
566 void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
568 const TargetInstrDesc *II,
569 DenseMap<SDOperand, unsigned> &VRBaseMap) {
570 if (Op.isTargetOpcode()) {
571 // Note that this case is redundant with the final else block, but we
572 // include it because it is the most common and it makes the logic
574 assert(Op.getValueType() != MVT::Other &&
575 Op.getValueType() != MVT::Flag &&
576 "Chain and flag operands should occur at end of operand list!");
577 // Get/emit the operand.
578 unsigned VReg = getVR(Op, VRBaseMap);
579 const TargetInstrDesc &TID = MI->getDesc();
580 bool isOptDef = IIOpNum < TID.getNumOperands() &&
581 TID.OpInfo[IIOpNum].isOptionalDef();
582 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
584 // Verify that it is right.
585 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
588 // There may be no register class for this operand if it is a variadic
589 // argument (RC will be NULL in this case). In this case, we just assume
590 // the regclass is ok.
591 const TargetRegisterClass *RC =
592 getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
593 assert((RC || II->isVariadic()) && "Expected reg class info!");
594 const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
595 if (RC && VRC != RC) {
596 cerr << "Register class of operand and regclass of use don't agree!\n";
597 cerr << "Operand = " << IIOpNum << "\n";
598 cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
599 cerr << "MI = "; MI->print(cerr);
600 cerr << "VReg = " << VReg << "\n";
601 cerr << "VReg RegClass size = " << VRC->getSize()
602 << ", align = " << VRC->getAlignment() << "\n";
603 cerr << "Expected RegClass size = " << RC->getSize()
604 << ", align = " << RC->getAlignment() << "\n";
605 cerr << "Fatal error, aborting.\n";
610 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
611 MI->addOperand(MachineOperand::CreateImm(C->getValue()));
612 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
613 ConstantFP *CFP = ConstantFP::get(F->getValueAPF());
614 MI->addOperand(MachineOperand::CreateFPImm(CFP));
615 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
616 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
617 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
618 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
619 } else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
620 MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
621 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
622 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
623 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
624 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex()));
625 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
626 int Offset = CP->getOffset();
627 unsigned Align = CP->getAlignment();
628 const Type *Type = CP->getType();
629 // MachineConstantPool wants an explicit alignment.
631 Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
633 // Alignment of vector types. FIXME!
634 Align = TM.getTargetData()->getABITypeSize(Type);
635 Align = Log2_64(Align);
640 if (CP->isMachineConstantPoolEntry())
641 Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
643 Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
644 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
645 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
646 MI->addOperand(MachineOperand::CreateES(ES->getSymbol()));
648 assert(Op.getValueType() != MVT::Other &&
649 Op.getValueType() != MVT::Flag &&
650 "Chain and flag operands should occur at end of operand list!");
651 unsigned VReg = getVR(Op, VRBaseMap);
652 MI->addOperand(MachineOperand::CreateReg(VReg, false));
654 // Verify that it is right. Note that the reg class of the physreg and the
655 // vreg don't necessarily need to match, but the target copy insertion has
656 // to be able to handle it. This handles things like copies from ST(0) to
657 // an FP vreg on x86.
658 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
659 if (II && !II->isVariadic()) {
660 assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
661 "Don't have operand info for this instruction!");
667 void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
668 MI->addMemOperand(MO);
671 // Returns the Register Class of a subregister
672 static const TargetRegisterClass *getSubRegisterRegClass(
673 const TargetRegisterClass *TRC,
675 // Pick the register class of the subregister
676 TargetRegisterInfo::regclass_iterator I =
677 TRC->subregclasses_begin() + SubIdx-1;
678 assert(I < TRC->subregclasses_end() &&
679 "Invalid subregister index for register class");
683 static const TargetRegisterClass *getSuperregRegisterClass(
684 const TargetRegisterClass *TRC,
687 // Pick the register class of the superegister for this type
688 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
689 E = TRC->superregclasses_end(); I != E; ++I)
690 if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
692 assert(false && "Couldn't find the register class");
696 /// EmitSubregNode - Generate machine code for subreg nodes.
698 void ScheduleDAG::EmitSubregNode(SDNode *Node,
699 DenseMap<SDOperand, unsigned> &VRBaseMap) {
701 unsigned Opc = Node->getTargetOpcode();
703 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
704 // the CopyToReg'd destination register instead of creating a new vreg.
705 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
707 SDNode *Use = UI->getUser();
708 if (Use->getOpcode() == ISD::CopyToReg &&
709 Use->getOperand(2).Val == Node) {
710 unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
711 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
718 if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
719 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getValue();
721 // Create the extract_subreg machine instruction.
722 MachineInstr *MI = BuildMI(TII->get(TargetInstrInfo::EXTRACT_SUBREG));
724 // Figure out the register class to create for the destreg.
725 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
726 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
727 const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
730 // Grab the destination register
732 const TargetRegisterClass *DRC = MRI.getRegClass(VRBase);
733 assert(SRC && DRC && SRC == DRC &&
734 "Source subregister and destination must have the same class");
738 assert(SRC && "Couldn't find source register class");
739 VRBase = MRI.createVirtualRegister(SRC);
742 // Add def, source, and subreg index
743 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
744 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
745 MI->addOperand(MachineOperand::CreateImm(SubIdx));
747 } else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
748 Opc == TargetInstrInfo::SUBREG_TO_REG) {
749 SDOperand N0 = Node->getOperand(0);
750 SDOperand N1 = Node->getOperand(1);
751 SDOperand N2 = Node->getOperand(2);
752 unsigned SubReg = getVR(N1, VRBaseMap);
753 unsigned SubIdx = cast<ConstantSDNode>(N2)->getValue();
756 // Figure out the register class to create for the destreg.
757 const TargetRegisterClass *TRC = 0;
759 TRC = MRI.getRegClass(VRBase);
761 TRC = getSuperregRegisterClass(MRI.getRegClass(SubReg), SubIdx,
762 Node->getValueType(0));
763 assert(TRC && "Couldn't determine register class for insert_subreg");
764 VRBase = MRI.createVirtualRegister(TRC); // Create the reg
767 // Create the insert_subreg or subreg_to_reg machine instruction.
768 MachineInstr *MI = BuildMI(TII->get(Opc));
769 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
771 // If creating a subreg_to_reg, then the first input operand
772 // is an implicit value immediate, otherwise it's a register
773 if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
774 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
775 MI->addOperand(MachineOperand::CreateImm(SD->getValue()));
777 AddOperand(MI, N0, 0, 0, VRBaseMap);
778 // Add the subregster being inserted
779 AddOperand(MI, N1, 0, 0, VRBaseMap);
780 MI->addOperand(MachineOperand::CreateImm(SubIdx));
783 assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
785 bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,0), VRBase));
786 isNew = isNew; // Silence compiler warning.
787 assert(isNew && "Node emitted out of order - early");
790 /// EmitNode - Generate machine code for an node and needed dependencies.
792 void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
793 DenseMap<SDOperand, unsigned> &VRBaseMap) {
794 // If machine instruction
795 if (Node->isTargetOpcode()) {
796 unsigned Opc = Node->getTargetOpcode();
798 // Handle subreg insert/extract specially
799 if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
800 Opc == TargetInstrInfo::INSERT_SUBREG ||
801 Opc == TargetInstrInfo::SUBREG_TO_REG) {
802 EmitSubregNode(Node, VRBaseMap);
806 if (Opc == TargetInstrInfo::IMPLICIT_DEF)
807 // We want a unique VR for each IMPLICIT_DEF use.
810 const TargetInstrDesc &II = TII->get(Opc);
811 unsigned NumResults = CountResults(Node);
812 unsigned NodeOperands = CountOperands(Node);
813 unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
814 bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
815 II.getImplicitDefs() != 0;
817 unsigned NumMIOperands = NodeOperands + NumResults;
818 assert((II.getNumOperands() == NumMIOperands ||
819 HasPhysRegOuts || II.isVariadic()) &&
820 "#operands for dag node doesn't match .td file!");
823 // Create the new machine instruction.
824 MachineInstr *MI = BuildMI(II);
826 // Add result register values for things that are defined by this
829 CreateVirtualRegisters(Node, MI, II, VRBaseMap);
831 // Emit all of the actual operands of this instruction, adding them to the
832 // instruction as appropriate.
833 for (unsigned i = 0; i != NodeOperands; ++i)
834 AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
836 // Emit all of the memory operands of this instruction
837 for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
838 AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO);
840 // Commute node if it has been determined to be profitable.
841 if (CommuteSet.count(Node)) {
842 MachineInstr *NewMI = TII->commuteInstruction(MI);
844 DOUT << "Sched: COMMUTING FAILED!\n";
846 DOUT << "Sched: COMMUTED TO: " << *NewMI;
855 if (II.usesCustomDAGSchedInsertionHook())
856 // Insert this instruction into the basic block using a target
857 // specific inserter which may returns a new basic block.
858 BB = TLI->EmitInstrWithCustomInserter(MI, BB);
862 // Additional results must be an physical register def.
863 if (HasPhysRegOuts) {
864 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
865 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
866 if (Node->hasAnyUseOfValue(i))
867 EmitCopyFromReg(Node, i, IsClone, Reg, VRBaseMap);
871 switch (Node->getOpcode()) {
876 assert(0 && "This target-independent node should have been selected!");
878 case ISD::EntryToken:
879 assert(0 && "EntryToken should have been excluded from the schedule!");
881 case ISD::TokenFactor: // fall thru
886 BB->push_back(BuildMI(TII->get(TargetInstrInfo::DBG_LABEL))
887 .addImm(cast<LabelSDNode>(Node)->getLabelID()));
890 BB->push_back(BuildMI(TII->get(TargetInstrInfo::EH_LABEL))
891 .addImm(cast<LabelSDNode>(Node)->getLabelID()));
893 case ISD::CopyToReg: {
895 SDOperand SrcVal = Node->getOperand(2);
896 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
897 SrcReg = R->getReg();
899 SrcReg = getVR(SrcVal, VRBaseMap);
901 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
902 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
905 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
906 // Get the register classes of the src/dst.
907 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
908 SrcTRC = MRI.getRegClass(SrcReg);
910 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
912 if (TargetRegisterInfo::isVirtualRegister(DestReg))
913 DstTRC = MRI.getRegClass(DestReg);
915 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
916 Node->getOperand(1).getValueType());
917 TII->copyRegToReg(*BB, BB->end(), DestReg, SrcReg, DstTRC, SrcTRC);
920 case ISD::CopyFromReg: {
921 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
922 EmitCopyFromReg(Node, 0, IsClone, SrcReg, VRBaseMap);
925 case ISD::INLINEASM: {
926 unsigned NumOps = Node->getNumOperands();
927 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
928 --NumOps; // Ignore the flag operand.
930 // Create the inline asm machine instruction.
931 MachineInstr *MI = BuildMI(TII->get(TargetInstrInfo::INLINEASM));
933 // Add the asm string as an external symbol operand.
935 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
936 MI->addOperand(MachineOperand::CreateES(AsmStr));
938 // Add all of the operand registers to the instruction.
939 for (unsigned i = 2; i != NumOps;) {
940 unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
941 unsigned NumVals = Flags >> 3;
943 MI->addOperand(MachineOperand::CreateImm(Flags));
944 ++i; // Skip the ID value.
947 default: assert(0 && "Bad flags!");
948 case 1: // Use of register.
949 for (; NumVals; --NumVals, ++i) {
950 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
951 MI->addOperand(MachineOperand::CreateReg(Reg, false));
954 case 2: // Def of register.
955 for (; NumVals; --NumVals, ++i) {
956 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
957 MI->addOperand(MachineOperand::CreateReg(Reg, true));
960 case 3: { // Immediate.
961 for (; NumVals; --NumVals, ++i) {
962 if (ConstantSDNode *CS =
963 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
964 MI->addOperand(MachineOperand::CreateImm(CS->getValue()));
965 } else if (GlobalAddressSDNode *GA =
966 dyn_cast<GlobalAddressSDNode>(Node->getOperand(i))) {
967 MI->addOperand(MachineOperand::CreateGA(GA->getGlobal(),
970 BasicBlockSDNode *BB =cast<BasicBlockSDNode>(Node->getOperand(i));
971 MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
976 case 4: // Addressing mode.
977 // The addressing mode has been selected, just add all of the
978 // operands to the machine instruction.
979 for (; NumVals; --NumVals, ++i)
980 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
991 void ScheduleDAG::EmitNoop() {
992 TII->insertNoop(*BB, BB->end());
995 void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
996 DenseMap<SUnit*, unsigned> &VRBaseMap) {
997 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
999 if (I->isCtrl) continue; // ignore chain preds
1000 if (!I->Dep->Node) {
1001 // Copy to physical register.
1002 DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->Dep);
1003 assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
1004 // Find the destination physical register.
1006 for (SUnit::const_succ_iterator II = SU->Succs.begin(),
1007 EE = SU->Succs.end(); II != EE; ++II) {
1013 assert(I->Reg && "Unknown physical register!");
1014 TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
1015 SU->CopyDstRC, SU->CopySrcRC);
1017 // Copy from physical register.
1018 assert(I->Reg && "Unknown physical register!");
1019 unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
1020 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
1021 isNew = isNew; // Silence compiler warning.
1022 assert(isNew && "Node emitted out of order - early");
1023 TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
1024 SU->CopyDstRC, SU->CopySrcRC);
1030 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
1031 /// physical register has only a single copy use, then coalesced the copy
1033 void ScheduleDAG::EmitLiveInCopy(MachineBasicBlock *MBB,
1034 MachineBasicBlock::iterator &InsertPos,
1035 unsigned VirtReg, unsigned PhysReg,
1036 const TargetRegisterClass *RC,
1037 DenseMap<MachineInstr*, unsigned> &CopyRegMap){
1038 unsigned NumUses = 0;
1039 MachineInstr *UseMI = NULL;
1040 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
1041 UE = MRI.use_end(); UI != UE; ++UI) {
1047 // If the number of uses is not one, or the use is not a move instruction,
1048 // don't coalesce. Also, only coalesce away a virtual register to virtual
1050 bool Coalesced = false;
1051 unsigned SrcReg, DstReg;
1053 TII->isMoveInstr(*UseMI, SrcReg, DstReg) &&
1054 TargetRegisterInfo::isVirtualRegister(DstReg)) {
1059 // Now find an ideal location to insert the copy.
1060 MachineBasicBlock::iterator Pos = InsertPos;
1061 while (Pos != MBB->begin()) {
1062 MachineInstr *PrevMI = prior(Pos);
1063 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
1064 // copyRegToReg might emit multiple instructions to do a copy.
1065 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
1066 if (CopyDstReg && !TRI->regsOverlap(CopyDstReg, PhysReg))
1067 // This is what the BB looks like right now:
1072 // We want to insert "r1025 = mov r1". Inserting this copy below the
1073 // move to r1024 makes it impossible for that move to be coalesced.
1080 break; // Woot! Found a good location.
1084 TII->copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
1085 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
1087 if (&*InsertPos == UseMI) ++InsertPos;
1092 /// EmitLiveInCopies - If this is the first basic block in the function,
1093 /// and if it has live ins that need to be copied into vregs, emit the
1094 /// copies into the top of the block.
1095 void ScheduleDAG::EmitLiveInCopies(MachineBasicBlock *MBB) {
1096 DenseMap<MachineInstr*, unsigned> CopyRegMap;
1097 MachineBasicBlock::iterator InsertPos = MBB->begin();
1098 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
1099 E = MRI.livein_end(); LI != E; ++LI)
1101 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
1102 EmitLiveInCopy(MBB, InsertPos, LI->second, LI->first, RC, CopyRegMap);
1106 /// EmitSchedule - Emit the machine code in scheduled order.
1107 void ScheduleDAG::EmitSchedule() {
1108 bool isEntryBB = &MF->front() == BB;
1110 if (isEntryBB && !SchedLiveInCopies) {
1111 // If this is the first basic block in the function, and if it has live ins
1112 // that need to be copied into vregs, emit the copies into the top of the
1113 // block before emitting the code for the block.
1114 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
1115 E = MRI.livein_end(); LI != E; ++LI)
1117 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
1118 TII->copyRegToReg(*MF->begin(), MF->begin()->end(), LI->second,
1123 // Finally, emit the code for all of the scheduled instructions.
1124 DenseMap<SDOperand, unsigned> VRBaseMap;
1125 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
1126 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
1127 SUnit *SU = Sequence[i];
1129 // Null SUnit* is a noop.
1133 for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; ++j)
1134 EmitNode(SU->FlaggedNodes[j], SU->OrigNode != SU, VRBaseMap);
1136 EmitCrossRCCopy(SU, CopyVRBaseMap);
1138 EmitNode(SU->Node, SU->OrigNode != SU, VRBaseMap);
1141 if (isEntryBB && SchedLiveInCopies)
1142 EmitLiveInCopies(MF->begin());
1145 /// dump - dump the schedule.
1146 void ScheduleDAG::dumpSchedule() const {
1147 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
1148 if (SUnit *SU = Sequence[i])
1151 cerr << "**** NOOP ****\n";
1156 /// Run - perform scheduling.
1158 MachineBasicBlock *ScheduleDAG::Run() {
1163 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
1164 /// a group of nodes flagged together.
1165 void SUnit::dump(const SelectionDAG *G) const {
1166 cerr << "SU(" << NodeNum << "): ";
1170 cerr << "CROSS RC COPY ";
1172 if (FlaggedNodes.size() != 0) {
1173 for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
1175 FlaggedNodes[i]->dump(G);
1181 void SUnit::dumpAll(const SelectionDAG *G) const {
1184 cerr << " # preds left : " << NumPredsLeft << "\n";
1185 cerr << " # succs left : " << NumSuccsLeft << "\n";
1186 cerr << " Latency : " << Latency << "\n";
1187 cerr << " Depth : " << Depth << "\n";
1188 cerr << " Height : " << Height << "\n";
1190 if (Preds.size() != 0) {
1191 cerr << " Predecessors:\n";
1192 for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
1198 cerr << I->Dep << " - SU(" << I->Dep->NodeNum << ")";
1204 if (Succs.size() != 0) {
1205 cerr << " Successors:\n";
1206 for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
1212 cerr << I->Dep << " - SU(" << I->Dep->NodeNum << ")";