1 //===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by James M. Laskey and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple two pass scheduler. The first pass attempts to push
11 // backward any lengthy instructions and critical paths. The second pass packs
12 // instructions into semi-optimal time slots.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "sched"
17 #include "llvm/Type.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
30 /// BuildSchedUnits - Build SUnits from the selection dag that we are input.
31 /// This SUnit graph is similar to the SelectionDAG, but represents flagged
32 /// together nodes with a single SUnit.
33 void ScheduleDAG::BuildSchedUnits() {
34 // Reserve entries in the vector for each of the SUnits we are creating. This
35 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
37 SUnits.reserve(std::distance(DAG.allnodes_begin(), DAG.allnodes_end()));
39 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
41 for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(),
42 E = DAG.allnodes_end(); NI != E; ++NI) {
43 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
46 // If this node has already been processed, stop now.
47 if (SUnitMap[NI]) continue;
49 SUnit *NodeSUnit = NewSUnit(NI);
51 // See if anything is flagged to this node, if so, add them to flagged
52 // nodes. Nodes can have at most one flag input and one flag output. Flags
53 // are required the be the last operand and result of a node.
55 // Scan up, adding flagged preds to FlaggedNodes.
57 if (N->getNumOperands() &&
58 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
60 N = N->getOperand(N->getNumOperands()-1).Val;
61 NodeSUnit->FlaggedNodes.push_back(N);
62 SUnitMap[N] = NodeSUnit;
63 } while (N->getNumOperands() &&
64 N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
65 std::reverse(NodeSUnit->FlaggedNodes.begin(),
66 NodeSUnit->FlaggedNodes.end());
69 // Scan down, adding this node and any flagged succs to FlaggedNodes if they
70 // have a user of the flag operand.
72 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
73 SDOperand FlagVal(N, N->getNumValues()-1);
75 // There are either zero or one users of the Flag result.
76 bool HasFlagUse = false;
77 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
79 if (FlagVal.isOperand(*UI)) {
81 NodeSUnit->FlaggedNodes.push_back(N);
82 SUnitMap[N] = NodeSUnit;
86 if (!HasFlagUse) break;
89 // Now all flagged nodes are in FlaggedNodes and N is the bottom-most node.
92 SUnitMap[N] = NodeSUnit;
94 // Compute the latency for the node. We use the sum of the latencies for
95 // all nodes flagged together into this SUnit.
96 if (InstrItins.isEmpty()) {
97 // No latency information.
98 NodeSUnit->Latency = 1;
100 NodeSUnit->Latency = 0;
101 if (N->isTargetOpcode()) {
102 unsigned SchedClass = TII->getSchedClass(N->getTargetOpcode());
103 InstrStage *S = InstrItins.begin(SchedClass);
104 InstrStage *E = InstrItins.end(SchedClass);
106 NodeSUnit->Latency += S->Cycles;
108 for (unsigned i = 0, e = NodeSUnit->FlaggedNodes.size(); i != e; ++i) {
109 SDNode *FNode = NodeSUnit->FlaggedNodes[i];
110 if (FNode->isTargetOpcode()) {
111 unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode());
112 InstrStage *S = InstrItins.begin(SchedClass);
113 InstrStage *E = InstrItins.end(SchedClass);
115 NodeSUnit->Latency += S->Cycles;
121 // Pass 2: add the preds, succs, etc.
122 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
123 SUnit *SU = &SUnits[su];
124 SDNode *MainNode = SU->Node;
126 if (MainNode->isTargetOpcode()) {
127 unsigned Opc = MainNode->getTargetOpcode();
128 for (unsigned i = 0, ee = TII->getNumOperands(Opc); i != ee; ++i) {
129 if (TII->getOperandConstraint(Opc, i, TOI::TIED_TO) != -1) {
130 SU->isTwoAddress = true;
134 if (TII->isCommutableInstr(Opc))
135 SU->isCommutable = true;
138 // Find all predecessors and successors of the group.
139 // Temporarily add N to make code simpler.
140 SU->FlaggedNodes.push_back(MainNode);
142 for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
143 SDNode *N = SU->FlaggedNodes[n];
145 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
146 SDNode *OpN = N->getOperand(i).Val;
147 if (isPassiveNode(OpN)) continue; // Not scheduled.
148 SUnit *OpSU = SUnitMap[OpN];
149 assert(OpSU && "Node has no SUnit!");
150 if (OpSU == SU) continue; // In the same group.
152 MVT::ValueType OpVT = N->getOperand(i).getValueType();
153 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
154 bool isChain = OpVT == MVT::Other;
156 if (SU->addPred(OpSU, isChain)) {
161 SU->NumChainPredsLeft++;
164 if (OpSU->addSucc(SU, isChain)) {
167 OpSU->NumSuccsLeft++;
169 OpSU->NumChainSuccsLeft++;
175 // Remove MainNode from FlaggedNodes again.
176 SU->FlaggedNodes.pop_back();
182 void ScheduleDAG::CalculateDepths() {
183 std::vector<std::pair<SUnit*, unsigned> > WorkList;
184 for (unsigned i = 0, e = SUnits.size(); i != e; ++i)
185 if (SUnits[i].Preds.size() == 0/* && &SUnits[i] != Entry*/)
186 WorkList.push_back(std::make_pair(&SUnits[i], 0U));
188 while (!WorkList.empty()) {
189 SUnit *SU = WorkList.back().first;
190 unsigned Depth = WorkList.back().second;
192 if (SU->Depth == 0 || Depth > SU->Depth) {
194 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
196 WorkList.push_back(std::make_pair(I->first, Depth+1));
201 void ScheduleDAG::CalculateHeights() {
202 std::vector<std::pair<SUnit*, unsigned> > WorkList;
203 SUnit *Root = SUnitMap[DAG.getRoot().Val];
204 WorkList.push_back(std::make_pair(Root, 0U));
206 while (!WorkList.empty()) {
207 SUnit *SU = WorkList.back().first;
208 unsigned Height = WorkList.back().second;
210 if (SU->Height == 0 || Height > SU->Height) {
212 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
214 WorkList.push_back(std::make_pair(I->first, Height+1));
219 /// CountResults - The results of target nodes have register or immediate
220 /// operands first, then an optional chain, and optional flag operands (which do
221 /// not go into the machine instrs.)
222 unsigned ScheduleDAG::CountResults(SDNode *Node) {
223 unsigned N = Node->getNumValues();
224 while (N && Node->getValueType(N - 1) == MVT::Flag)
226 if (N && Node->getValueType(N - 1) == MVT::Other)
227 --N; // Skip over chain result.
231 /// CountOperands The inputs to target nodes have any actual inputs first,
232 /// followed by an optional chain operand, then flag operands. Compute the
233 /// number of actual operands that will go into the machine instr.
234 unsigned ScheduleDAG::CountOperands(SDNode *Node) {
235 unsigned N = Node->getNumOperands();
236 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
238 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
239 --N; // Ignore chain if it exists.
243 static const TargetRegisterClass *getInstrOperandRegClass(
244 const MRegisterInfo *MRI,
245 const TargetInstrInfo *TII,
246 const TargetInstrDescriptor *II,
248 if (Op >= II->numOperands) {
249 assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
252 const TargetOperandInfo &toi = II->OpInfo[Op];
253 return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
254 ? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
257 static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI,
261 const TargetInstrInfo *TII,
262 const TargetInstrDescriptor &II) {
263 // Create the result registers for this node and add the result regs to
264 // the machine instruction.
266 RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
267 MI->addRegOperand(ResultReg, true);
268 for (unsigned i = 1; i != NumResults; ++i) {
269 const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
270 assert(RC && "Isn't a register operand!");
271 MI->addRegOperand(RegMap->createVirtualRegister(RC), true);
276 /// getVR - Return the virtual register corresponding to the specified result
277 /// of the specified node.
278 static unsigned getVR(SDOperand Op, DenseMap<SDNode*, unsigned> &VRBaseMap) {
279 DenseMap<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
280 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
281 return I->second + Op.ResNo;
285 /// AddOperand - Add the specified operand to the specified machine instr. II
286 /// specifies the instruction information for the node, and IIOpNum is the
287 /// operand number (in the II) that we are adding. IIOpNum and II are used for
289 void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
291 const TargetInstrDescriptor *II,
292 DenseMap<SDNode*, unsigned> &VRBaseMap) {
293 if (Op.isTargetOpcode()) {
294 // Note that this case is redundant with the final else block, but we
295 // include it because it is the most common and it makes the logic
297 assert(Op.getValueType() != MVT::Other &&
298 Op.getValueType() != MVT::Flag &&
299 "Chain and flag operands should occur at end of operand list!");
301 // Get/emit the operand.
302 unsigned VReg = getVR(Op, VRBaseMap);
303 MI->addRegOperand(VReg, false);
305 // Verify that it is right.
306 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
308 const TargetRegisterClass *RC =
309 getInstrOperandRegClass(MRI, TII, II, IIOpNum);
310 assert(RC && "Don't have operand info for this instruction!");
311 const TargetRegisterClass *VRC = RegMap->getRegClass(VReg);
313 cerr << "Register class of operand and regclass of use don't agree!\n";
315 cerr << "Operand = " << IIOpNum << "\n";
316 cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
317 cerr << "MI = "; MI->print(cerr);
318 cerr << "VReg = " << VReg << "\n";
319 cerr << "VReg RegClass size = " << VRC->getSize()
320 << ", align = " << VRC->getAlignment() << "\n";
321 cerr << "Expected RegClass size = " << RC->getSize()
322 << ", align = " << RC->getAlignment() << "\n";
324 cerr << "Fatal error, aborting.\n";
328 } else if (ConstantSDNode *C =
329 dyn_cast<ConstantSDNode>(Op)) {
330 MI->addImmOperand(C->getValue());
331 } else if (RegisterSDNode *R =
332 dyn_cast<RegisterSDNode>(Op)) {
333 MI->addRegOperand(R->getReg(), false);
334 } else if (GlobalAddressSDNode *TGA =
335 dyn_cast<GlobalAddressSDNode>(Op)) {
336 MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
337 } else if (BasicBlockSDNode *BB =
338 dyn_cast<BasicBlockSDNode>(Op)) {
339 MI->addMachineBasicBlockOperand(BB->getBasicBlock());
340 } else if (FrameIndexSDNode *FI =
341 dyn_cast<FrameIndexSDNode>(Op)) {
342 MI->addFrameIndexOperand(FI->getIndex());
343 } else if (JumpTableSDNode *JT =
344 dyn_cast<JumpTableSDNode>(Op)) {
345 MI->addJumpTableIndexOperand(JT->getIndex());
346 } else if (ConstantPoolSDNode *CP =
347 dyn_cast<ConstantPoolSDNode>(Op)) {
348 int Offset = CP->getOffset();
349 unsigned Align = CP->getAlignment();
350 const Type *Type = CP->getType();
351 // MachineConstantPool wants an explicit alignment.
353 Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
355 // Alignment of vector types. FIXME!
356 Align = TM.getTargetData()->getTypeSize(Type);
357 Align = Log2_64(Align);
362 if (CP->isMachineConstantPoolEntry())
363 Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
365 Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
366 MI->addConstantPoolIndexOperand(Idx, Offset);
367 } else if (ExternalSymbolSDNode *ES =
368 dyn_cast<ExternalSymbolSDNode>(Op)) {
369 MI->addExternalSymbolOperand(ES->getSymbol());
371 assert(Op.getValueType() != MVT::Other &&
372 Op.getValueType() != MVT::Flag &&
373 "Chain and flag operands should occur at end of operand list!");
374 unsigned VReg = getVR(Op, VRBaseMap);
375 MI->addRegOperand(VReg, false);
377 // Verify that it is right.
378 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
380 const TargetRegisterClass *RC =
381 getInstrOperandRegClass(MRI, TII, II, IIOpNum);
382 assert(RC && "Don't have operand info for this instruction!");
383 assert(RegMap->getRegClass(VReg) == RC &&
384 "Register class of operand and regclass of use don't agree!");
390 // Returns the Register Class of a physical register
391 static const TargetRegisterClass *getPhysicalRegisterRegClass(
392 const MRegisterInfo *MRI,
395 assert(MRegisterInfo::isPhysicalRegister(reg) &&
396 "reg must be a physical register");
397 // Pick the register class of the right type that contains this physreg.
398 for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
399 E = MRI->regclass_end(); I != E; ++I)
400 if ((*I)->hasType(VT) && (*I)->contains(reg))
402 assert(false && "Couldn't find the register class");
406 /// EmitNode - Generate machine code for an node and needed dependencies.
408 void ScheduleDAG::EmitNode(SDNode *Node,
409 DenseMap<SDNode*, unsigned> &VRBaseMap) {
410 unsigned VRBase = 0; // First virtual register for node
412 // If machine instruction
413 if (Node->isTargetOpcode()) {
414 unsigned Opc = Node->getTargetOpcode();
415 const TargetInstrDescriptor &II = TII->get(Opc);
417 unsigned NumResults = CountResults(Node);
418 unsigned NodeOperands = CountOperands(Node);
419 unsigned NumMIOperands = NodeOperands + NumResults;
421 assert((unsigned(II.numOperands) == NumMIOperands ||
422 (II.Flags & M_VARIABLE_OPS)) &&
423 "#operands for dag node doesn't match .td file!");
426 // Create the new machine instruction.
427 MachineInstr *MI = new MachineInstr(II);
429 // Add result register values for things that are defined by this
432 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
433 // the CopyToReg'd destination register instead of creating a new vreg.
434 if (NumResults == 1) {
435 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
438 if (Use->getOpcode() == ISD::CopyToReg &&
439 Use->getOperand(2).Val == Node) {
440 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
441 if (MRegisterInfo::isVirtualRegister(Reg)) {
443 MI->addRegOperand(Reg, true);
450 // Otherwise, create new virtual registers.
451 if (NumResults && VRBase == 0)
452 VRBase = CreateVirtualRegisters(MRI, MI, NumResults, RegMap, TII, II);
454 // Emit all of the actual operands of this instruction, adding them to the
455 // instruction as appropriate.
456 for (unsigned i = 0; i != NodeOperands; ++i)
457 AddOperand(MI, Node->getOperand(i), i+NumResults, &II, VRBaseMap);
459 // Commute node if it has been determined to be profitable.
460 if (CommuteSet.count(Node)) {
461 MachineInstr *NewMI = TII->commuteInstruction(MI);
463 DOUT << "Sched: COMMUTING FAILED!\n";
465 DOUT << "Sched: COMMUTED TO: " << *NewMI;
473 // Now that we have emitted all operands, emit this instruction itself.
474 if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
475 BB->insert(BB->end(), MI);
477 // Insert this instruction into the end of the basic block, potentially
478 // taking some custom action.
479 BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
482 switch (Node->getOpcode()) {
487 assert(0 && "This target-independent node should have been selected!");
488 case ISD::EntryToken: // fall thru
489 case ISD::TokenFactor:
492 case ISD::CopyToReg: {
494 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(2)))
497 InReg = getVR(Node->getOperand(2), VRBaseMap);
498 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
499 if (InReg != DestReg) {// Coalesced away the copy?
500 const TargetRegisterClass *TRC = 0;
501 // Get the target register class
502 if (MRegisterInfo::isVirtualRegister(InReg))
503 TRC = RegMap->getRegClass(InReg);
505 TRC = getPhysicalRegisterRegClass(MRI,
506 Node->getOperand(2).getValueType(),
508 MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC);
512 case ISD::CopyFromReg: {
513 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
514 if (MRegisterInfo::isVirtualRegister(SrcReg)) {
515 VRBase = SrcReg; // Just use the input register directly!
519 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
520 // the CopyToReg'd destination register instead of creating a new vreg.
521 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
524 if (Use->getOpcode() == ISD::CopyToReg &&
525 Use->getOperand(2).Val == Node) {
526 unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
527 if (MRegisterInfo::isVirtualRegister(DestReg)) {
534 // Figure out the register class to create for the destreg.
535 const TargetRegisterClass *TRC = 0;
537 TRC = RegMap->getRegClass(VRBase);
539 TRC = getPhysicalRegisterRegClass(MRI, Node->getValueType(0), SrcReg);
541 // Create the reg, emit the copy.
542 VRBase = RegMap->createVirtualRegister(TRC);
544 MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
547 case ISD::INLINEASM: {
548 unsigned NumOps = Node->getNumOperands();
549 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
550 --NumOps; // Ignore the flag operand.
552 // Create the inline asm machine instruction.
554 new MachineInstr(BB, TII->get(TargetInstrInfo::INLINEASM));
556 // Add the asm string as an external symbol operand.
558 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
559 MI->addExternalSymbolOperand(AsmStr);
561 // Add all of the operand registers to the instruction.
562 for (unsigned i = 2; i != NumOps;) {
563 unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
564 unsigned NumVals = Flags >> 3;
566 MI->addImmOperand(Flags);
567 ++i; // Skip the ID value.
570 default: assert(0 && "Bad flags!");
571 case 1: // Use of register.
572 for (; NumVals; --NumVals, ++i) {
573 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
574 MI->addRegOperand(Reg, false);
577 case 2: // Def of register.
578 for (; NumVals; --NumVals, ++i) {
579 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
580 MI->addRegOperand(Reg, true);
583 case 3: { // Immediate.
584 assert(NumVals == 1 && "Unknown immediate value!");
585 if (ConstantSDNode *CS=dyn_cast<ConstantSDNode>(Node->getOperand(i))){
586 MI->addImmOperand(CS->getValue());
588 GlobalAddressSDNode *GA =
589 cast<GlobalAddressSDNode>(Node->getOperand(i));
590 MI->addGlobalAddressOperand(GA->getGlobal(), GA->getOffset());
595 case 4: // Addressing mode.
596 // The addressing mode has been selected, just add all of the
597 // operands to the machine instruction.
598 for (; NumVals; --NumVals, ++i)
599 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
608 assert(!VRBaseMap.count(Node) && "Node emitted out of order - early");
609 VRBaseMap[Node] = VRBase;
612 void ScheduleDAG::EmitNoop() {
613 TII->insertNoop(*BB, BB->end());
616 /// EmitSchedule - Emit the machine code in scheduled order.
617 void ScheduleDAG::EmitSchedule() {
618 // If this is the first basic block in the function, and if it has live ins
619 // that need to be copied into vregs, emit the copies into the top of the
620 // block before emitting the code for the block.
621 MachineFunction &MF = DAG.getMachineFunction();
622 if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) {
623 for (MachineFunction::livein_iterator LI = MF.livein_begin(),
624 E = MF.livein_end(); LI != E; ++LI)
626 MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
627 LI->first, RegMap->getRegClass(LI->second));
631 // Finally, emit the code for all of the scheduled instructions.
632 DenseMap<SDNode*, unsigned> VRBaseMap;
633 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
634 if (SUnit *SU = Sequence[i]) {
635 for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++)
636 EmitNode(SU->FlaggedNodes[j], VRBaseMap);
637 EmitNode(SU->Node, VRBaseMap);
639 // Null SUnit* is a noop.
645 /// dump - dump the schedule.
646 void ScheduleDAG::dumpSchedule() const {
647 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
648 if (SUnit *SU = Sequence[i])
651 cerr << "**** NOOP ****\n";
656 /// Run - perform scheduling.
658 MachineBasicBlock *ScheduleDAG::Run() {
659 TII = TM.getInstrInfo();
660 MRI = TM.getRegisterInfo();
661 RegMap = BB->getParent()->getSSARegMap();
662 ConstPool = BB->getParent()->getConstantPool();
668 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
669 /// a group of nodes flagged together.
670 void SUnit::dump(const SelectionDAG *G) const {
671 cerr << "SU(" << NodeNum << "): ";
674 if (FlaggedNodes.size() != 0) {
675 for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
677 FlaggedNodes[i]->dump(G);
683 void SUnit::dumpAll(const SelectionDAG *G) const {
686 cerr << " # preds left : " << NumPredsLeft << "\n";
687 cerr << " # succs left : " << NumSuccsLeft << "\n";
688 cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
689 cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
690 cerr << " Latency : " << Latency << "\n";
691 cerr << " Depth : " << Depth << "\n";
692 cerr << " Height : " << Height << "\n";
694 if (Preds.size() != 0) {
695 cerr << " Predecessors:\n";
696 for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
702 cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";
705 if (Succs.size() != 0) {
706 cerr << " Successors:\n";
707 for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
713 cerr << I->first << " - SU(" << I->first->NodeNum << ")\n";