1 //===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the ScheduleDAG class, which creates
11 // MachineInstrs according to the computed schedule.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pre-RA-sched"
16 #include "llvm/CodeGen/ScheduleDAG.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
31 STATISTIC(NumCommutes, "Number of instructions commuted");
33 /// getInstrOperandRegClass - Return register class of the operand of an
34 /// instruction of the specified TargetInstrDesc.
35 static const TargetRegisterClass*
36 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
37 const TargetInstrInfo *TII, const TargetInstrDesc &II,
39 if (Op >= II.getNumOperands()) {
40 assert(II.isVariadic() && "Invalid operand # of instruction");
43 if (II.OpInfo[Op].isLookupPtrRegClass())
44 return TII->getPointerRegClass();
45 return TRI->getRegClass(II.OpInfo[Op].RegClass);
48 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
49 /// implicit physical register output.
50 void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
51 bool IsClone, unsigned SrcReg,
52 DenseMap<SDValue, unsigned> &VRBaseMap) {
54 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
55 // Just use the input register directly!
56 SDValue Op(Node, ResNo);
59 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
60 isNew = isNew; // Silence compiler warning.
61 assert(isNew && "Node emitted out of order - early");
65 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
66 // the CopyToReg'd destination register instead of creating a new vreg.
68 const TargetRegisterClass *UseRC = NULL;
69 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
73 if (User->getOpcode() == ISD::CopyToReg &&
74 User->getOperand(2).getNode() == Node &&
75 User->getOperand(2).getResNo() == ResNo) {
76 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
77 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
80 } else if (DestReg != SrcReg)
83 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
84 SDValue Op = User->getOperand(i);
85 if (Op.getNode() != Node || Op.getResNo() != ResNo)
87 MVT VT = Node->getValueType(Op.getResNo());
88 if (VT == MVT::Other || VT == MVT::Flag)
91 if (User->isMachineOpcode()) {
92 const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
93 const TargetRegisterClass *RC =
94 getInstrOperandRegClass(TRI,TII,II,i+II.getNumDefs());
99 "Multiple uses expecting different register classes!");
108 MVT VT = Node->getValueType(ResNo);
109 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
110 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
112 // Figure out the register class to create for the destreg.
114 DstRC = MRI.getRegClass(VRBase);
116 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
119 DstRC = TLI->getRegClassFor(VT);
122 // If all uses are reading from the src physical register and copying the
123 // register is either impossible or very expensive, then don't create a copy.
124 if (MatchReg && SrcRC->getCopyCost() < 0) {
127 // Create the reg, emit the copy.
128 VRBase = MRI.createVirtualRegister(DstRC);
130 TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
131 Emitted = Emitted; // Silence compiler warning.
132 assert(Emitted && "Unable to issue a copy instruction!");
135 SDValue Op(Node, ResNo);
138 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
139 isNew = isNew; // Silence compiler warning.
140 assert(isNew && "Node emitted out of order - early");
143 /// getDstOfCopyToRegUse - If the only use of the specified result number of
144 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
145 unsigned ScheduleDAG::getDstOfOnlyCopyToRegUse(SDNode *Node,
146 unsigned ResNo) const {
147 if (!Node->hasOneUse())
150 SDNode *User = *Node->use_begin();
151 if (User->getOpcode() == ISD::CopyToReg &&
152 User->getOperand(2).getNode() == Node &&
153 User->getOperand(2).getResNo() == ResNo) {
154 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
155 if (TargetRegisterInfo::isVirtualRegister(Reg))
161 void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
162 const TargetInstrDesc &II,
163 DenseMap<SDValue, unsigned> &VRBaseMap) {
164 assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
165 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
167 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
168 // If the specific node value is only used by a CopyToReg and the dest reg
169 // is a vreg, use the CopyToReg'd destination register instead of creating
172 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
175 if (User->getOpcode() == ISD::CopyToReg &&
176 User->getOperand(2).getNode() == Node &&
177 User->getOperand(2).getResNo() == i) {
178 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
179 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
181 MI->addOperand(MachineOperand::CreateReg(Reg, true));
187 // Create the result registers for this node and add the result regs to
188 // the machine instruction.
190 const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
191 assert(RC && "Isn't a register operand!");
192 VRBase = MRI.createVirtualRegister(RC);
193 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
197 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
198 isNew = isNew; // Silence compiler warning.
199 assert(isNew && "Node emitted out of order - early");
203 /// getVR - Return the virtual register corresponding to the specified result
204 /// of the specified node.
205 unsigned ScheduleDAG::getVR(SDValue Op,
206 DenseMap<SDValue, unsigned> &VRBaseMap) {
207 if (Op.isMachineOpcode() &&
208 Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
209 // Add an IMPLICIT_DEF instruction before every use.
210 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
211 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
212 // does not include operand register class info.
214 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
215 VReg = MRI.createVirtualRegister(RC);
217 BuildMI(BB, TII->get(TargetInstrInfo::IMPLICIT_DEF), VReg);
221 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
222 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
227 /// AddOperand - Add the specified operand to the specified machine instr. II
228 /// specifies the instruction information for the node, and IIOpNum is the
229 /// operand number (in the II) that we are adding. IIOpNum and II are used for
231 void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
233 const TargetInstrDesc *II,
234 DenseMap<SDValue, unsigned> &VRBaseMap,
235 bool overlapsEarlyClobber) {
236 if (Op.isMachineOpcode()) {
237 // Note that this case is redundant with the final else block, but we
238 // include it because it is the most common and it makes the logic
240 assert(Op.getValueType() != MVT::Other &&
241 Op.getValueType() != MVT::Flag &&
242 "Chain and flag operands should occur at end of operand list!");
243 // Get/emit the operand.
244 unsigned VReg = getVR(Op, VRBaseMap);
245 const TargetInstrDesc &TID = MI->getDesc();
246 bool isOptDef = IIOpNum < TID.getNumOperands() &&
247 TID.OpInfo[IIOpNum].isOptionalDef();
248 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, false, false,
250 overlapsEarlyClobber));
252 // Verify that it is right.
253 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
256 // There may be no register class for this operand if it is a variadic
257 // argument (RC will be NULL in this case). In this case, we just assume
258 // the regclass is ok.
259 const TargetRegisterClass *RC =
260 getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
261 assert((RC || II->isVariadic()) && "Expected reg class info!");
262 const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
263 if (RC && VRC != RC) {
264 cerr << "Register class of operand and regclass of use don't agree!\n";
265 cerr << "Operand = " << IIOpNum << "\n";
266 cerr << "Op->Val = "; Op.getNode()->dump(&DAG); cerr << "\n";
267 cerr << "MI = "; MI->print(cerr);
268 cerr << "VReg = " << VReg << "\n";
269 cerr << "VReg RegClass size = " << VRC->getSize()
270 << ", align = " << VRC->getAlignment() << "\n";
271 cerr << "Expected RegClass size = " << RC->getSize()
272 << ", align = " << RC->getAlignment() << "\n";
273 cerr << "Fatal error, aborting.\n";
278 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
279 MI->addOperand(MachineOperand::CreateImm(C->getZExtValue()));
280 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
281 const ConstantFP *CFP = F->getConstantFPValue();
282 MI->addOperand(MachineOperand::CreateFPImm(CFP));
283 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
284 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false, false,
285 false, false, 0, false,
286 overlapsEarlyClobber));
287 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
288 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
289 } else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
290 MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
291 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
292 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
293 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
294 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex()));
295 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
296 int Offset = CP->getOffset();
297 unsigned Align = CP->getAlignment();
298 const Type *Type = CP->getType();
299 // MachineConstantPool wants an explicit alignment.
301 Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
303 // Alignment of vector types. FIXME!
304 Align = TM.getTargetData()->getABITypeSize(Type);
305 Align = Log2_64(Align);
310 if (CP->isMachineConstantPoolEntry())
311 Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
313 Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
314 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
315 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
316 MI->addOperand(MachineOperand::CreateES(ES->getSymbol()));
318 assert(Op.getValueType() != MVT::Other &&
319 Op.getValueType() != MVT::Flag &&
320 "Chain and flag operands should occur at end of operand list!");
321 unsigned VReg = getVR(Op, VRBaseMap);
322 MI->addOperand(MachineOperand::CreateReg(VReg, false, false,
323 false, false, 0, false,
324 overlapsEarlyClobber));
326 // Verify that it is right. Note that the reg class of the physreg and the
327 // vreg don't necessarily need to match, but the target copy insertion has
328 // to be able to handle it. This handles things like copies from ST(0) to
329 // an FP vreg on x86.
330 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
331 if (II && !II->isVariadic()) {
332 assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
333 "Don't have operand info for this instruction!");
338 void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
339 MI->addMemOperand(*MF, MO);
342 /// getSubRegisterRegClass - Returns the register class of specified register
343 /// class' "SubIdx"'th sub-register class.
344 static const TargetRegisterClass*
345 getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx) {
346 // Pick the register class of the subregister
347 TargetRegisterInfo::regclass_iterator I =
348 TRC->subregclasses_begin() + SubIdx-1;
349 assert(I < TRC->subregclasses_end() &&
350 "Invalid subregister index for register class");
354 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
355 /// "SubIdx"'th sub-register class is the specified register class and whose
356 /// type matches the specified type.
357 static const TargetRegisterClass*
358 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
359 unsigned SubIdx, MVT VT) {
360 // Pick the register class of the superegister for this type
361 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
362 E = TRC->superregclasses_end(); I != E; ++I)
363 if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
365 assert(false && "Couldn't find the register class");
369 /// EmitSubregNode - Generate machine code for subreg nodes.
371 void ScheduleDAG::EmitSubregNode(SDNode *Node,
372 DenseMap<SDValue, unsigned> &VRBaseMap) {
374 unsigned Opc = Node->getMachineOpcode();
376 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
377 // the CopyToReg'd destination register instead of creating a new vreg.
378 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
381 if (User->getOpcode() == ISD::CopyToReg &&
382 User->getOperand(2).getNode() == Node) {
383 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
384 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
391 if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
392 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
394 // Create the extract_subreg machine instruction.
395 MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
397 // Figure out the register class to create for the destreg.
398 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
399 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
400 const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
403 // Grab the destination register
405 const TargetRegisterClass *DRC = MRI.getRegClass(VRBase);
406 assert(SRC && DRC && SRC == DRC &&
407 "Source subregister and destination must have the same class");
411 assert(SRC && "Couldn't find source register class");
412 VRBase = MRI.createVirtualRegister(SRC);
415 // Add def, source, and subreg index
416 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
417 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
418 MI->addOperand(MachineOperand::CreateImm(SubIdx));
420 } else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
421 Opc == TargetInstrInfo::SUBREG_TO_REG) {
422 SDValue N0 = Node->getOperand(0);
423 SDValue N1 = Node->getOperand(1);
424 SDValue N2 = Node->getOperand(2);
425 unsigned SubReg = getVR(N1, VRBaseMap);
426 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
429 // Figure out the register class to create for the destreg.
430 const TargetRegisterClass *TRC = 0;
432 TRC = MRI.getRegClass(VRBase);
434 TRC = getSuperRegisterRegClass(MRI.getRegClass(SubReg), SubIdx,
435 Node->getValueType(0));
436 assert(TRC && "Couldn't determine register class for insert_subreg");
437 VRBase = MRI.createVirtualRegister(TRC); // Create the reg
440 // Create the insert_subreg or subreg_to_reg machine instruction.
441 MachineInstr *MI = BuildMI(*MF, TII->get(Opc));
442 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
444 // If creating a subreg_to_reg, then the first input operand
445 // is an implicit value immediate, otherwise it's a register
446 if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
447 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
448 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
450 AddOperand(MI, N0, 0, 0, VRBaseMap);
451 // Add the subregster being inserted
452 AddOperand(MI, N1, 0, 0, VRBaseMap);
453 MI->addOperand(MachineOperand::CreateImm(SubIdx));
456 assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
459 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
460 isNew = isNew; // Silence compiler warning.
461 assert(isNew && "Node emitted out of order - early");
464 /// EmitNode - Generate machine code for an node and needed dependencies.
466 void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
467 DenseMap<SDValue, unsigned> &VRBaseMap) {
468 // If machine instruction
469 if (Node->isMachineOpcode()) {
470 unsigned Opc = Node->getMachineOpcode();
472 // Handle subreg insert/extract specially
473 if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
474 Opc == TargetInstrInfo::INSERT_SUBREG ||
475 Opc == TargetInstrInfo::SUBREG_TO_REG) {
476 EmitSubregNode(Node, VRBaseMap);
480 if (Opc == TargetInstrInfo::IMPLICIT_DEF)
481 // We want a unique VR for each IMPLICIT_DEF use.
484 const TargetInstrDesc &II = TII->get(Opc);
485 unsigned NumResults = CountResults(Node);
486 unsigned NodeOperands = CountOperands(Node);
487 unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
488 bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
489 II.getImplicitDefs() != 0;
491 unsigned NumMIOperands = NodeOperands + NumResults;
492 assert((II.getNumOperands() == NumMIOperands ||
493 HasPhysRegOuts || II.isVariadic()) &&
494 "#operands for dag node doesn't match .td file!");
497 // Create the new machine instruction.
498 MachineInstr *MI = BuildMI(*MF, II);
500 // Add result register values for things that are defined by this
503 CreateVirtualRegisters(Node, MI, II, VRBaseMap);
505 // Emit all of the actual operands of this instruction, adding them to the
506 // instruction as appropriate.
507 for (unsigned i = 0; i != NodeOperands; ++i)
508 AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
510 // Emit all of the memory operands of this instruction
511 for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
512 AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO);
514 // Commute node if it has been determined to be profitable.
515 if (CommuteSet.count(Node)) {
516 MachineInstr *NewMI = TII->commuteInstruction(MI);
518 DOUT << "Sched: COMMUTING FAILED!\n";
520 DOUT << "Sched: COMMUTED TO: " << *NewMI;
522 MF->DeleteMachineInstr(MI);
529 if (II.usesCustomDAGSchedInsertionHook())
530 // Insert this instruction into the basic block using a target
531 // specific inserter which may returns a new basic block.
532 BB = TLI->EmitInstrWithCustomInserter(MI, BB);
536 // Additional results must be an physical register def.
537 if (HasPhysRegOuts) {
538 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
539 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
540 if (Node->hasAnyUseOfValue(i))
541 EmitCopyFromReg(Node, i, IsClone, Reg, VRBaseMap);
547 switch (Node->getOpcode()) {
552 assert(0 && "This target-independent node should have been selected!");
554 case ISD::EntryToken:
555 assert(0 && "EntryToken should have been excluded from the schedule!");
557 case ISD::TokenFactor: // fall thru
559 case ISD::CopyToReg: {
561 SDValue SrcVal = Node->getOperand(2);
562 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
563 SrcReg = R->getReg();
565 SrcReg = getVR(SrcVal, VRBaseMap);
567 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
568 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
571 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
572 // Get the register classes of the src/dst.
573 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
574 SrcTRC = MRI.getRegClass(SrcReg);
576 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
578 if (TargetRegisterInfo::isVirtualRegister(DestReg))
579 DstTRC = MRI.getRegClass(DestReg);
581 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
582 Node->getOperand(1).getValueType());
583 TII->copyRegToReg(*BB, BB->end(), DestReg, SrcReg, DstTRC, SrcTRC);
586 case ISD::CopyFromReg: {
587 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
588 EmitCopyFromReg(Node, 0, IsClone, SrcReg, VRBaseMap);
591 case ISD::INLINEASM: {
592 unsigned NumOps = Node->getNumOperands();
593 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
594 --NumOps; // Ignore the flag operand.
596 // Create the inline asm machine instruction.
597 MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::INLINEASM));
599 // Add the asm string as an external symbol operand.
601 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
602 MI->addOperand(MachineOperand::CreateES(AsmStr));
604 // Add all of the operand registers to the instruction.
605 for (unsigned i = 2; i != NumOps;) {
606 bool overlapsEarlyClobber = false;
608 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
609 unsigned NumVals = Flags >> 3;
611 MI->addOperand(MachineOperand::CreateImm(Flags));
612 ++i; // Skip the ID value.
615 default: assert(0 && "Bad flags!");
616 case 2: // Def of register.
617 for (; NumVals; --NumVals, ++i) {
618 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
619 MI->addOperand(MachineOperand::CreateReg(Reg, true));
622 case 6: // Def of earlyclobber register.
623 for (; NumVals; --NumVals, ++i) {
624 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
625 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
629 case 7: // Addressing mode overlapping earlyclobber.
630 case 5: // Use of register overlapping earlyclobber.
631 overlapsEarlyClobber = true;
633 case 1: // Use of register.
634 case 3: // Immediate.
635 case 4: // Addressing mode.
636 // The addressing mode has been selected, just add all of the
637 // operands to the machine instruction.
638 for (; NumVals; --NumVals, ++i)
639 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
640 overlapsEarlyClobber);
650 void ScheduleDAG::EmitNoop() {
651 TII->insertNoop(*BB, BB->end());
654 void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
655 DenseMap<SUnit*, unsigned> &VRBaseMap) {
656 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
658 if (I->isCtrl) continue; // ignore chain preds
660 // Copy to physical register.
661 DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->Dep);
662 assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
663 // Find the destination physical register.
665 for (SUnit::const_succ_iterator II = SU->Succs.begin(),
666 EE = SU->Succs.end(); II != EE; ++II) {
672 assert(I->Reg && "Unknown physical register!");
673 TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
674 SU->CopyDstRC, SU->CopySrcRC);
676 // Copy from physical register.
677 assert(I->Reg && "Unknown physical register!");
678 unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
679 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
680 isNew = isNew; // Silence compiler warning.
681 assert(isNew && "Node emitted out of order - early");
682 TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
683 SU->CopyDstRC, SU->CopySrcRC);
689 /// EmitSchedule - Emit the machine code in scheduled order.
690 MachineBasicBlock *ScheduleDAG::EmitSchedule() {
691 DenseMap<SDValue, unsigned> VRBaseMap;
692 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
693 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
694 SUnit *SU = Sequence[i];
696 // Null SUnit* is a noop.
700 for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; ++j)
701 EmitNode(SU->FlaggedNodes[j], SU->OrigNode != SU, VRBaseMap);
703 EmitCrossRCCopy(SU, CopyVRBaseMap);
705 EmitNode(SU->Node, SU->OrigNode != SU, VRBaseMap);