1 //===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the ScheduleDAG class, which creates
11 // MachineInstrs according to the computed schedule.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pre-RA-sched"
16 #include "llvm/CodeGen/ScheduleDAG.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
31 STATISTIC(NumCommutes, "Number of instructions commuted");
33 /// getInstrOperandRegClass - Return register class of the operand of an
34 /// instruction of the specified TargetInstrDesc.
35 static const TargetRegisterClass*
36 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
37 const TargetInstrInfo *TII, const TargetInstrDesc &II,
39 if (Op >= II.getNumOperands()) {
40 assert(II.isVariadic() && "Invalid operand # of instruction");
43 if (II.OpInfo[Op].isLookupPtrRegClass())
44 return TII->getPointerRegClass();
45 return TRI->getRegClass(II.OpInfo[Op].RegClass);
48 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
49 /// implicit physical register output.
50 void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
51 bool IsClone, unsigned SrcReg,
52 DenseMap<SDValue, unsigned> &VRBaseMap) {
54 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
55 // Just use the input register directly!
56 SDValue Op(Node, ResNo);
59 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
60 isNew = isNew; // Silence compiler warning.
61 assert(isNew && "Node emitted out of order - early");
65 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
66 // the CopyToReg'd destination register instead of creating a new vreg.
68 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
72 if (User->getOpcode() == ISD::CopyToReg &&
73 User->getOperand(2).getNode() == Node &&
74 User->getOperand(2).getResNo() == ResNo) {
75 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
76 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
79 } else if (DestReg != SrcReg)
82 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
83 SDValue Op = User->getOperand(i);
84 if (Op.getNode() != Node || Op.getResNo() != ResNo)
86 MVT VT = Node->getValueType(Op.getResNo());
87 if (VT != MVT::Other && VT != MVT::Flag)
96 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
97 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, Node->getValueType(ResNo));
99 // Figure out the register class to create for the destreg.
101 DstRC = MRI.getRegClass(VRBase);
103 DstRC = TLI->getRegClassFor(Node->getValueType(ResNo));
106 // If all uses are reading from the src physical register and copying the
107 // register is either impossible or very expensive, then don't create a copy.
108 if (MatchReg && SrcRC->getCopyCost() < 0) {
111 // Create the reg, emit the copy.
112 VRBase = MRI.createVirtualRegister(DstRC);
113 TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
116 SDValue Op(Node, ResNo);
119 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
120 isNew = isNew; // Silence compiler warning.
121 assert(isNew && "Node emitted out of order - early");
124 /// getDstOfCopyToRegUse - If the only use of the specified result number of
125 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
126 unsigned ScheduleDAG::getDstOfOnlyCopyToRegUse(SDNode *Node,
127 unsigned ResNo) const {
128 if (!Node->hasOneUse())
131 SDNode *User = *Node->use_begin();
132 if (User->getOpcode() == ISD::CopyToReg &&
133 User->getOperand(2).getNode() == Node &&
134 User->getOperand(2).getResNo() == ResNo) {
135 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
136 if (TargetRegisterInfo::isVirtualRegister(Reg))
142 void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
143 const TargetInstrDesc &II,
144 DenseMap<SDValue, unsigned> &VRBaseMap) {
145 assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
146 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
148 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
149 // If the specific node value is only used by a CopyToReg and the dest reg
150 // is a vreg, use the CopyToReg'd destination register instead of creating
153 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
156 if (User->getOpcode() == ISD::CopyToReg &&
157 User->getOperand(2).getNode() == Node &&
158 User->getOperand(2).getResNo() == i) {
159 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
160 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
162 MI->addOperand(MachineOperand::CreateReg(Reg, true));
168 // Create the result registers for this node and add the result regs to
169 // the machine instruction.
171 const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
172 assert(RC && "Isn't a register operand!");
173 VRBase = MRI.createVirtualRegister(RC);
174 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
178 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
179 isNew = isNew; // Silence compiler warning.
180 assert(isNew && "Node emitted out of order - early");
184 /// getVR - Return the virtual register corresponding to the specified result
185 /// of the specified node.
186 unsigned ScheduleDAG::getVR(SDValue Op,
187 DenseMap<SDValue, unsigned> &VRBaseMap) {
188 if (Op.isMachineOpcode() &&
189 Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
190 // Add an IMPLICIT_DEF instruction before every use.
191 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
192 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
193 // does not include operand register class info.
195 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
196 VReg = MRI.createVirtualRegister(RC);
198 BuildMI(BB, TII->get(TargetInstrInfo::IMPLICIT_DEF), VReg);
202 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
203 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
208 /// AddOperand - Add the specified operand to the specified machine instr. II
209 /// specifies the instruction information for the node, and IIOpNum is the
210 /// operand number (in the II) that we are adding. IIOpNum and II are used for
212 void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
214 const TargetInstrDesc *II,
215 DenseMap<SDValue, unsigned> &VRBaseMap) {
216 if (Op.isMachineOpcode()) {
217 // Note that this case is redundant with the final else block, but we
218 // include it because it is the most common and it makes the logic
220 assert(Op.getValueType() != MVT::Other &&
221 Op.getValueType() != MVT::Flag &&
222 "Chain and flag operands should occur at end of operand list!");
223 // Get/emit the operand.
224 unsigned VReg = getVR(Op, VRBaseMap);
225 const TargetInstrDesc &TID = MI->getDesc();
226 bool isOptDef = IIOpNum < TID.getNumOperands() &&
227 TID.OpInfo[IIOpNum].isOptionalDef();
228 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
230 // Verify that it is right.
231 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
234 // There may be no register class for this operand if it is a variadic
235 // argument (RC will be NULL in this case). In this case, we just assume
236 // the regclass is ok.
237 const TargetRegisterClass *RC =
238 getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
239 assert((RC || II->isVariadic()) && "Expected reg class info!");
240 const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
241 if (RC && VRC != RC) {
242 cerr << "Register class of operand and regclass of use don't agree!\n";
243 cerr << "Operand = " << IIOpNum << "\n";
244 cerr << "Op->Val = "; Op.getNode()->dump(&DAG); cerr << "\n";
245 cerr << "MI = "; MI->print(cerr);
246 cerr << "VReg = " << VReg << "\n";
247 cerr << "VReg RegClass size = " << VRC->getSize()
248 << ", align = " << VRC->getAlignment() << "\n";
249 cerr << "Expected RegClass size = " << RC->getSize()
250 << ", align = " << RC->getAlignment() << "\n";
251 cerr << "Fatal error, aborting.\n";
256 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
257 MI->addOperand(MachineOperand::CreateImm(C->getZExtValue()));
258 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
259 ConstantFP *CFP = ConstantFP::get(F->getValueAPF());
260 MI->addOperand(MachineOperand::CreateFPImm(CFP));
261 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
262 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
263 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
264 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
265 } else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
266 MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
267 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
268 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
269 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
270 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex()));
271 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
272 int Offset = CP->getOffset();
273 unsigned Align = CP->getAlignment();
274 const Type *Type = CP->getType();
275 // MachineConstantPool wants an explicit alignment.
277 Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
279 // Alignment of vector types. FIXME!
280 Align = TM.getTargetData()->getABITypeSize(Type);
281 Align = Log2_64(Align);
286 if (CP->isMachineConstantPoolEntry())
287 Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
289 Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
290 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
291 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
292 MI->addOperand(MachineOperand::CreateES(ES->getSymbol()));
294 assert(Op.getValueType() != MVT::Other &&
295 Op.getValueType() != MVT::Flag &&
296 "Chain and flag operands should occur at end of operand list!");
297 unsigned VReg = getVR(Op, VRBaseMap);
298 MI->addOperand(MachineOperand::CreateReg(VReg, false));
300 // Verify that it is right. Note that the reg class of the physreg and the
301 // vreg don't necessarily need to match, but the target copy insertion has
302 // to be able to handle it. This handles things like copies from ST(0) to
303 // an FP vreg on x86.
304 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
305 if (II && !II->isVariadic()) {
306 assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
307 "Don't have operand info for this instruction!");
312 void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
313 MI->addMemOperand(*MF, MO);
316 /// getSubRegisterRegClass - Returns the register class of specified register
317 /// class' "SubIdx"'th sub-register class.
318 static const TargetRegisterClass*
319 getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx) {
320 // Pick the register class of the subregister
321 TargetRegisterInfo::regclass_iterator I =
322 TRC->subregclasses_begin() + SubIdx-1;
323 assert(I < TRC->subregclasses_end() &&
324 "Invalid subregister index for register class");
328 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
329 /// "SubIdx"'th sub-register class is the specified register class and whose
330 /// type matches the specified type.
331 static const TargetRegisterClass*
332 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
333 unsigned SubIdx, MVT VT) {
334 // Pick the register class of the superegister for this type
335 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
336 E = TRC->superregclasses_end(); I != E; ++I)
337 if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
339 assert(false && "Couldn't find the register class");
343 /// EmitSubregNode - Generate machine code for subreg nodes.
345 void ScheduleDAG::EmitSubregNode(SDNode *Node,
346 DenseMap<SDValue, unsigned> &VRBaseMap) {
348 unsigned Opc = Node->getMachineOpcode();
350 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
351 // the CopyToReg'd destination register instead of creating a new vreg.
352 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
355 if (User->getOpcode() == ISD::CopyToReg &&
356 User->getOperand(2).getNode() == Node) {
357 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
358 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
365 if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
366 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
368 // Create the extract_subreg machine instruction.
369 MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
371 // Figure out the register class to create for the destreg.
372 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
373 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
374 const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
377 // Grab the destination register
379 const TargetRegisterClass *DRC = MRI.getRegClass(VRBase);
380 assert(SRC && DRC && SRC == DRC &&
381 "Source subregister and destination must have the same class");
385 assert(SRC && "Couldn't find source register class");
386 VRBase = MRI.createVirtualRegister(SRC);
389 // Add def, source, and subreg index
390 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
391 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
392 MI->addOperand(MachineOperand::CreateImm(SubIdx));
394 } else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
395 Opc == TargetInstrInfo::SUBREG_TO_REG) {
396 SDValue N0 = Node->getOperand(0);
397 SDValue N1 = Node->getOperand(1);
398 SDValue N2 = Node->getOperand(2);
399 unsigned SubReg = getVR(N1, VRBaseMap);
400 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
403 // Figure out the register class to create for the destreg.
404 const TargetRegisterClass *TRC = 0;
406 TRC = MRI.getRegClass(VRBase);
408 TRC = getSuperRegisterRegClass(MRI.getRegClass(SubReg), SubIdx,
409 Node->getValueType(0));
410 assert(TRC && "Couldn't determine register class for insert_subreg");
411 VRBase = MRI.createVirtualRegister(TRC); // Create the reg
414 // Create the insert_subreg or subreg_to_reg machine instruction.
415 MachineInstr *MI = BuildMI(*MF, TII->get(Opc));
416 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
418 // If creating a subreg_to_reg, then the first input operand
419 // is an implicit value immediate, otherwise it's a register
420 if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
421 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
422 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
424 AddOperand(MI, N0, 0, 0, VRBaseMap);
425 // Add the subregster being inserted
426 AddOperand(MI, N1, 0, 0, VRBaseMap);
427 MI->addOperand(MachineOperand::CreateImm(SubIdx));
430 assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
433 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
434 isNew = isNew; // Silence compiler warning.
435 assert(isNew && "Node emitted out of order - early");
438 /// EmitNode - Generate machine code for an node and needed dependencies.
440 void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
441 DenseMap<SDValue, unsigned> &VRBaseMap) {
442 // If machine instruction
443 if (Node->isMachineOpcode()) {
444 unsigned Opc = Node->getMachineOpcode();
446 // Handle subreg insert/extract specially
447 if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
448 Opc == TargetInstrInfo::INSERT_SUBREG ||
449 Opc == TargetInstrInfo::SUBREG_TO_REG) {
450 EmitSubregNode(Node, VRBaseMap);
454 if (Opc == TargetInstrInfo::IMPLICIT_DEF)
455 // We want a unique VR for each IMPLICIT_DEF use.
458 const TargetInstrDesc &II = TII->get(Opc);
459 unsigned NumResults = CountResults(Node);
460 unsigned NodeOperands = CountOperands(Node);
461 unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
462 bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
463 II.getImplicitDefs() != 0;
465 unsigned NumMIOperands = NodeOperands + NumResults;
466 assert((II.getNumOperands() == NumMIOperands ||
467 HasPhysRegOuts || II.isVariadic()) &&
468 "#operands for dag node doesn't match .td file!");
471 // Create the new machine instruction.
472 MachineInstr *MI = BuildMI(*MF, II);
474 // Add result register values for things that are defined by this
477 CreateVirtualRegisters(Node, MI, II, VRBaseMap);
479 // Emit all of the actual operands of this instruction, adding them to the
480 // instruction as appropriate.
481 for (unsigned i = 0; i != NodeOperands; ++i)
482 AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
484 // Emit all of the memory operands of this instruction
485 for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
486 AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO);
488 // Commute node if it has been determined to be profitable.
489 if (CommuteSet.count(Node)) {
490 MachineInstr *NewMI = TII->commuteInstruction(MI);
492 DOUT << "Sched: COMMUTING FAILED!\n";
494 DOUT << "Sched: COMMUTED TO: " << *NewMI;
496 MF->DeleteMachineInstr(MI);
503 if (II.usesCustomDAGSchedInsertionHook())
504 // Insert this instruction into the basic block using a target
505 // specific inserter which may returns a new basic block.
506 BB = TLI->EmitInstrWithCustomInserter(MI, BB);
510 // Additional results must be an physical register def.
511 if (HasPhysRegOuts) {
512 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
513 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
514 if (Node->hasAnyUseOfValue(i))
515 EmitCopyFromReg(Node, i, IsClone, Reg, VRBaseMap);
521 switch (Node->getOpcode()) {
526 assert(0 && "This target-independent node should have been selected!");
528 case ISD::EntryToken:
529 assert(0 && "EntryToken should have been excluded from the schedule!");
531 case ISD::TokenFactor: // fall thru
533 case ISD::CopyToReg: {
535 SDValue SrcVal = Node->getOperand(2);
536 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
537 SrcReg = R->getReg();
539 SrcReg = getVR(SrcVal, VRBaseMap);
541 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
542 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
545 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
546 // Get the register classes of the src/dst.
547 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
548 SrcTRC = MRI.getRegClass(SrcReg);
550 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
552 if (TargetRegisterInfo::isVirtualRegister(DestReg))
553 DstTRC = MRI.getRegClass(DestReg);
555 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
556 Node->getOperand(1).getValueType());
557 TII->copyRegToReg(*BB, BB->end(), DestReg, SrcReg, DstTRC, SrcTRC);
560 case ISD::CopyFromReg: {
561 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
562 EmitCopyFromReg(Node, 0, IsClone, SrcReg, VRBaseMap);
565 case ISD::INLINEASM: {
566 unsigned NumOps = Node->getNumOperands();
567 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
568 --NumOps; // Ignore the flag operand.
570 // Create the inline asm machine instruction.
571 MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::INLINEASM));
573 // Add the asm string as an external symbol operand.
575 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
576 MI->addOperand(MachineOperand::CreateES(AsmStr));
578 // Add all of the operand registers to the instruction.
579 for (unsigned i = 2; i != NumOps;) {
581 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
582 unsigned NumVals = Flags >> 3;
584 MI->addOperand(MachineOperand::CreateImm(Flags));
585 ++i; // Skip the ID value.
588 default: assert(0 && "Bad flags!");
589 case 2: // Def of register.
590 for (; NumVals; --NumVals, ++i) {
591 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
592 MI->addOperand(MachineOperand::CreateReg(Reg, true));
595 case 1: // Use of register.
596 case 3: // Immediate.
597 case 4: // Addressing mode.
598 // The addressing mode has been selected, just add all of the
599 // operands to the machine instruction.
600 for (; NumVals; --NumVals, ++i)
601 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
611 void ScheduleDAG::EmitNoop() {
612 TII->insertNoop(*BB, BB->end());
615 void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
616 DenseMap<SUnit*, unsigned> &VRBaseMap) {
617 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
619 if (I->isCtrl) continue; // ignore chain preds
621 // Copy to physical register.
622 DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->Dep);
623 assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
624 // Find the destination physical register.
626 for (SUnit::const_succ_iterator II = SU->Succs.begin(),
627 EE = SU->Succs.end(); II != EE; ++II) {
633 assert(I->Reg && "Unknown physical register!");
634 TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
635 SU->CopyDstRC, SU->CopySrcRC);
637 // Copy from physical register.
638 assert(I->Reg && "Unknown physical register!");
639 unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
640 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
641 isNew = isNew; // Silence compiler warning.
642 assert(isNew && "Node emitted out of order - early");
643 TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
644 SU->CopyDstRC, SU->CopySrcRC);
650 /// EmitSchedule - Emit the machine code in scheduled order.
651 MachineBasicBlock *ScheduleDAG::EmitSchedule() {
652 DenseMap<SDValue, unsigned> VRBaseMap;
653 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
654 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
655 SUnit *SU = Sequence[i];
657 // Null SUnit* is a noop.
661 for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; ++j)
662 EmitNode(SU->FlaggedNodes[j], SU->OrigNode != SU, VRBaseMap);
664 EmitCrossRCCopy(SU, CopyVRBaseMap);
666 EmitNode(SU->Node, SU->OrigNode != SU, VRBaseMap);