1 //===---- ScheduleDAGList.cpp - Implement a list scheduler for isel DAG ---===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements bottom-up and top-down list schedulers, using standard
11 // algorithms. The basic approach uses a priority queue of available nodes to
12 // schedule. One at a time, nodes are taken from the priority queue (thus in
13 // priority order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "sched"
22 #include "llvm/CodeGen/ScheduleDAG.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/ADT/Statistic.h"
36 Statistic<> NumNoops ("scheduler", "Number of noops inserted");
37 Statistic<> NumStalls("scheduler", "Number of pipeline stalls");
39 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or a
40 /// group of nodes flagged together.
42 SDNode *Node; // Representative node.
43 std::vector<SDNode*> FlaggedNodes; // All nodes flagged to Node.
44 std::set<SUnit*> Preds; // All real predecessors.
45 std::set<SUnit*> ChainPreds; // All chain predecessors.
46 std::set<SUnit*> Succs; // All real successors.
47 std::set<SUnit*> ChainSuccs; // All chain successors.
48 int NumPredsLeft; // # of preds not scheduled.
49 int NumSuccsLeft; // # of succs not scheduled.
50 int NumChainPredsLeft; // # of chain preds not scheduled.
51 int NumChainSuccsLeft; // # of chain succs not scheduled.
52 int SethiUllman; // Sethi Ullman number.
53 bool isTwoAddress; // Is a two-address instruction.
54 bool isDefNUseOperand; // Is a def&use operand.
55 unsigned Latency; // Node latency.
56 unsigned CycleBound; // Upper/lower cycle to be scheduled at.
57 unsigned Slot; // Cycle node is scheduled at.
61 : Node(node), NumPredsLeft(0), NumSuccsLeft(0),
62 NumChainPredsLeft(0), NumChainSuccsLeft(0),
64 isTwoAddress(false), isDefNUseOperand(false),
65 Latency(0), CycleBound(0), Slot(0), Next(NULL) {}
67 void dump(const SelectionDAG *G, bool All=true) const;
70 void SUnit::dump(const SelectionDAG *G, bool All) const {
74 if (FlaggedNodes.size() != 0) {
75 for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
77 FlaggedNodes[i]->dump(G);
83 std::cerr << " # preds left : " << NumPredsLeft << "\n";
84 std::cerr << " # succs left : " << NumSuccsLeft << "\n";
85 std::cerr << " # chain preds left : " << NumChainPredsLeft << "\n";
86 std::cerr << " # chain succs left : " << NumChainSuccsLeft << "\n";
87 std::cerr << " Latency : " << Latency << "\n";
88 std::cerr << " SethiUllman : " << SethiUllman << "\n";
90 if (Preds.size() != 0) {
91 std::cerr << " Predecessors:\n";
92 for (std::set<SUnit*>::const_iterator I = Preds.begin(),
93 E = Preds.end(); I != E; ++I) {
98 if (ChainPreds.size() != 0) {
99 std::cerr << " Chained Preds:\n";
100 for (std::set<SUnit*>::const_iterator I = ChainPreds.begin(),
101 E = ChainPreds.end(); I != E; ++I) {
103 (*I)->dump(G, false);
106 if (Succs.size() != 0) {
107 std::cerr << " Successors:\n";
108 for (std::set<SUnit*>::const_iterator I = Succs.begin(),
109 E = Succs.end(); I != E; ++I) {
111 (*I)->dump(G, false);
114 if (ChainSuccs.size() != 0) {
115 std::cerr << " Chained succs:\n";
116 for (std::set<SUnit*>::const_iterator I = ChainSuccs.begin(),
117 E = ChainSuccs.end(); I != E; ++I) {
119 (*I)->dump(G, false);
125 /// Sorting functions for the Available queue.
126 struct ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
127 bool operator()(const SUnit* left, const SUnit* right) const {
128 int LBonus = (int)left ->isDefNUseOperand;
129 int RBonus = (int)right->isDefNUseOperand;
131 // Special tie breaker: if two nodes share a operand, the one that
132 // use it as a def&use operand is preferred.
133 if (left->isTwoAddress && !right->isTwoAddress) {
134 SDNode *DUNode = left->Node->getOperand(0).Val;
135 if (DUNode->isOperand(right->Node))
138 if (!left->isTwoAddress && right->isTwoAddress) {
139 SDNode *DUNode = right->Node->getOperand(0).Val;
140 if (DUNode->isOperand(left->Node))
144 // Priority1 is just the number of live range genned.
145 int LPriority1 = left ->NumPredsLeft - LBonus;
146 int RPriority1 = right->NumPredsLeft - RBonus;
147 int LPriority2 = left ->SethiUllman + LBonus;
148 int RPriority2 = right->SethiUllman + RBonus;
150 if (LPriority1 > RPriority1)
152 else if (LPriority1 == RPriority1)
153 if (LPriority2 < RPriority2)
155 else if (LPriority2 == RPriority2)
156 if (left->CycleBound > right->CycleBound)
164 /// ScheduleDAGList - List scheduler.
165 class ScheduleDAGList : public ScheduleDAG {
167 // SDNode to SUnit mapping (many to one).
168 std::map<SDNode*, SUnit*> SUnitMap;
169 // The schedule. Null SUnit*'s represent noop instructions.
170 std::vector<SUnit*> Sequence;
171 // Current scheduling cycle.
173 // First and last SUnit created.
174 SUnit *HeadSUnit, *TailSUnit;
176 /// isBottomUp - This is true if the scheduling problem is bottom-up, false if
180 /// HazardRec - The hazard recognizer to use.
181 HazardRecognizer *HazardRec;
183 typedef std::priority_queue<SUnit*, std::vector<SUnit*>, ls_rr_sort>
187 ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb,
188 const TargetMachine &tm, bool isbottomup,
189 HazardRecognizer *HR)
190 : ScheduleDAG(listSchedulingBURR, dag, bb, tm),
191 CurrCycle(0), HeadSUnit(NULL), TailSUnit(NULL), isBottomUp(isbottomup),
196 SUnit *SU = HeadSUnit;
198 SUnit *NextSU = SU->Next;
210 SUnit *NewSUnit(SDNode *N);
211 void ReleasePred(AvailableQueueTy &Avail,SUnit *PredSU, bool isChain = false);
212 void ReleaseSucc(AvailableQueueTy &Avail,SUnit *SuccSU, bool isChain = false);
213 void ScheduleNodeBottomUp(AvailableQueueTy &Avail, SUnit *SU);
214 void ScheduleNodeTopDown(AvailableQueueTy &Avail, SUnit *SU);
215 int CalcNodePriority(SUnit *SU);
216 void CalculatePriorities();
217 void ListScheduleTopDown();
218 void ListScheduleBottomUp();
219 void BuildSchedUnits();
224 HazardRecognizer::~HazardRecognizer() {}
227 /// NewSUnit - Creates a new SUnit and return a ptr to it.
228 SUnit *ScheduleDAGList::NewSUnit(SDNode *N) {
229 SUnit *CurrSUnit = new SUnit(N);
231 if (HeadSUnit == NULL)
232 HeadSUnit = CurrSUnit;
233 if (TailSUnit != NULL)
234 TailSUnit->Next = CurrSUnit;
235 TailSUnit = CurrSUnit;
240 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
241 /// the Available queue is the count reaches zero. Also update its cycle bound.
242 void ScheduleDAGList::ReleasePred(AvailableQueueTy &Available,
243 SUnit *PredSU, bool isChain) {
244 // FIXME: the distance between two nodes is not always == the predecessor's
245 // latency. For example, the reader can very well read the register written
246 // by the predecessor later than the issue cycle. It also depends on the
247 // interrupt model (drain vs. freeze).
248 PredSU->CycleBound = std::max(PredSU->CycleBound, CurrCycle + PredSU->Latency);
251 PredSU->NumSuccsLeft--;
253 PredSU->NumChainSuccsLeft--;
256 if (PredSU->NumSuccsLeft < 0 || PredSU->NumChainSuccsLeft < 0) {
257 std::cerr << "*** List scheduling failed! ***\n";
259 std::cerr << " has been released too many times!\n";
264 if ((PredSU->NumSuccsLeft + PredSU->NumChainSuccsLeft) == 0) {
265 // EntryToken has to go last! Special case it here.
266 if (PredSU->Node->getOpcode() != ISD::EntryToken)
267 Available.push(PredSU);
271 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
272 /// the Available queue is the count reaches zero. Also update its cycle bound.
273 void ScheduleDAGList::ReleaseSucc(AvailableQueueTy &Available,
274 SUnit *SuccSU, bool isChain) {
275 // FIXME: the distance between two nodes is not always == the predecessor's
276 // latency. For example, the reader can very well read the register written
277 // by the predecessor later than the issue cycle. It also depends on the
278 // interrupt model (drain vs. freeze).
279 SuccSU->CycleBound = std::max(SuccSU->CycleBound, CurrCycle + SuccSU->Latency);
282 SuccSU->NumPredsLeft--;
284 SuccSU->NumChainPredsLeft--;
287 if (SuccSU->NumPredsLeft < 0 || SuccSU->NumChainPredsLeft < 0) {
288 std::cerr << "*** List scheduling failed! ***\n";
290 std::cerr << " has been released too many times!\n";
295 if ((SuccSU->NumPredsLeft + SuccSU->NumChainPredsLeft) == 0)
296 Available.push(SuccSU);
299 /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
300 /// count of its predecessors. If a predecessor pending count is zero, add it to
301 /// the Available queue.
302 void ScheduleDAGList::ScheduleNodeBottomUp(AvailableQueueTy &Available,
304 DEBUG(std::cerr << "*** Scheduling: ");
305 DEBUG(SU->dump(&DAG, false));
307 Sequence.push_back(SU);
308 SU->Slot = CurrCycle;
310 // Bottom up: release predecessors
311 for (std::set<SUnit*>::iterator I1 = SU->Preds.begin(),
312 E1 = SU->Preds.end(); I1 != E1; ++I1) {
313 ReleasePred(Available, *I1);
316 for (std::set<SUnit*>::iterator I2 = SU->ChainPreds.begin(),
317 E2 = SU->ChainPreds.end(); I2 != E2; ++I2)
318 ReleasePred(Available, *I2, true);
323 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
324 /// count of its successors. If a successor pending count is zero, add it to
325 /// the Available queue.
326 void ScheduleDAGList::ScheduleNodeTopDown(AvailableQueueTy &Available,
328 DEBUG(std::cerr << "*** Scheduling: ");
329 DEBUG(SU->dump(&DAG, false));
331 Sequence.push_back(SU);
332 SU->Slot = CurrCycle;
334 // Bottom up: release successors.
335 for (std::set<SUnit*>::iterator I1 = SU->Succs.begin(),
336 E1 = SU->Succs.end(); I1 != E1; ++I1) {
337 ReleaseSucc(Available, *I1);
340 for (std::set<SUnit*>::iterator I2 = SU->ChainSuccs.begin(),
341 E2 = SU->ChainSuccs.end(); I2 != E2; ++I2)
342 ReleaseSucc(Available, *I2, true);
347 /// isReady - True if node's lower cycle bound is less or equal to the current
348 /// scheduling cycle. Always true if all nodes have uniform latency 1.
349 static inline bool isReady(SUnit *SU, unsigned CurrCycle) {
350 return SU->CycleBound <= CurrCycle;
353 /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
355 void ScheduleDAGList::ListScheduleBottomUp() {
357 AvailableQueueTy Available;
359 // Add root to Available queue.
360 Available.push(SUnitMap[DAG.getRoot().Val]);
362 // While Available queue is not empty, grab the node with the highest
363 // priority. If it is not ready put it back. Schedule the node.
364 std::vector<SUnit*> NotReady;
365 while (!Available.empty()) {
366 SUnit *CurrNode = Available.top();
369 while (!isReady(CurrNode, CurrCycle)) {
370 NotReady.push_back(CurrNode);
371 CurrNode = Available.top();
375 // Add the nodes that aren't ready back onto the available list.
376 while (!NotReady.empty()) {
377 Available.push(NotReady.back());
381 ScheduleNodeBottomUp(Available, CurrNode);
384 // Add entry node last
385 if (DAG.getEntryNode().Val != DAG.getRoot().Val) {
386 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
387 Entry->Slot = CurrCycle;
388 Sequence.push_back(Entry);
391 // Reverse the order if it is bottom up.
392 std::reverse(Sequence.begin(), Sequence.end());
396 // Verify that all SUnits were scheduled.
397 bool AnyNotSched = false;
398 for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) {
399 if (SU->NumSuccsLeft != 0 || SU->NumChainSuccsLeft != 0) {
401 std::cerr << "*** List scheduling failed! ***\n";
403 std::cerr << "has not been scheduled!\n";
407 assert(!AnyNotSched);
411 /// ListScheduleTopDown - The main loop of list scheduling for top-down
413 void ScheduleDAGList::ListScheduleTopDown() {
415 AvailableQueueTy Available;
417 // Emit the entry node first.
418 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
419 ScheduleNodeTopDown(Available, Entry);
420 HazardRec->EmitInstruction(Entry->Node);
422 // All leaves to Available queue.
423 for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) {
424 // It is available if it has no predecessors.
425 if ((SU->Preds.size() + SU->ChainPreds.size()) == 0 && SU != Entry)
429 // While Available queue is not empty, grab the node with the highest
430 // priority. If it is not ready put it back. Schedule the node.
431 std::vector<SUnit*> NotReady;
432 while (!Available.empty()) {
433 SUnit *FoundNode = 0;
435 bool HasNoopHazards = false;
437 SUnit *CurNode = Available.top();
440 // Get the node represented by this SUnit.
441 SDNode *N = CurNode->Node;
442 // If this is a pseudo op, like copyfromreg, look to see if there is a
443 // real target node flagged to it. If so, use the target node.
444 for (unsigned i = 0, e = CurNode->FlaggedNodes.size();
445 N->getOpcode() < ISD::BUILTIN_OP_END && i != e; ++i)
446 N = CurNode->FlaggedNodes[i];
448 HazardRecognizer::HazardType HT = HazardRec->getHazardType(N);
449 if (HT == HazardRecognizer::NoHazard) {
454 // Remember if this is a noop hazard.
455 HasNoopHazards |= HT == HazardRecognizer::NoopHazard;
457 NotReady.push_back(CurNode);
458 } while (!Available.empty());
460 // Add the nodes that aren't ready back onto the available list.
461 while (!NotReady.empty()) {
462 Available.push(NotReady.back());
466 // If we found a node to schedule, do it now.
468 ScheduleNodeTopDown(Available, FoundNode);
469 HazardRec->EmitInstruction(FoundNode->Node);
470 } else if (!HasNoopHazards) {
471 // Otherwise, we have a pipeline stall, but no other problem, just advance
472 // the current cycle and try again.
473 DEBUG(std::cerr << "*** Advancing cycle, no work to do\n");
474 HazardRec->AdvanceCycle();
477 // Otherwise, we have no instructions to issue and we have instructions
478 // that will fault if we don't do this right. This is the case for
479 // processors without pipeline interlocks and other cases.
480 DEBUG(std::cerr << "*** Emitting noop\n");
481 HazardRec->EmitNoop();
482 Sequence.push_back(0); // NULL SUnit* -> noop
488 // Verify that all SUnits were scheduled.
489 bool AnyNotSched = false;
490 for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) {
491 if (SU->NumPredsLeft != 0 || SU->NumChainPredsLeft != 0) {
493 std::cerr << "*** List scheduling failed! ***\n";
495 std::cerr << "has not been scheduled!\n";
499 assert(!AnyNotSched);
504 /// CalcNodePriority - Priority is the Sethi Ullman number.
505 /// Smaller number is the higher priority.
506 int ScheduleDAGList::CalcNodePriority(SUnit *SU) {
507 if (SU->SethiUllman != INT_MIN)
508 return SU->SethiUllman;
510 if (SU->Preds.size() == 0) {
514 for (std::set<SUnit*>::iterator I = SU->Preds.begin(),
515 E = SU->Preds.end(); I != E; ++I) {
517 int PredSethiUllman = CalcNodePriority(PredSU);
518 if (PredSethiUllman > SU->SethiUllman) {
519 SU->SethiUllman = PredSethiUllman;
521 } else if (PredSethiUllman == SU->SethiUllman)
525 if (SU->Node->getOpcode() != ISD::TokenFactor)
526 SU->SethiUllman += Extra;
528 SU->SethiUllman = (Extra == 1) ? 0 : Extra-1;
531 return SU->SethiUllman;
534 /// CalculatePriorities - Calculate priorities of all scheduling units.
535 void ScheduleDAGList::CalculatePriorities() {
536 for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) {
537 // FIXME: assumes uniform latency for now.
539 (void)CalcNodePriority(SU);
540 DEBUG(SU->dump(&DAG));
541 DEBUG(std::cerr << "\n");
545 void ScheduleDAGList::BuildSchedUnits() {
546 // Pass 1: create the SUnit's.
547 for (unsigned i = 0, NC = NodeCount; i < NC; i++) {
548 NodeInfo *NI = &Info[i];
549 SDNode *N = NI->Node;
550 if (isPassiveNode(N))
554 if (NI->isInGroup()) {
555 if (NI != NI->Group->getBottom()) // Bottom up, so only look at bottom
556 continue; // node of the NodeGroup
559 // Find the flagged nodes.
560 SDOperand FlagOp = N->getOperand(N->getNumOperands() - 1);
561 SDNode *Flag = FlagOp.Val;
562 unsigned ResNo = FlagOp.ResNo;
563 while (Flag->getValueType(ResNo) == MVT::Flag) {
564 NodeInfo *FNI = getNI(Flag);
565 assert(FNI->Group == NI->Group);
566 SU->FlaggedNodes.insert(SU->FlaggedNodes.begin(), Flag);
569 FlagOp = Flag->getOperand(Flag->getNumOperands() - 1);
571 ResNo = FlagOp.ResNo;
579 // Pass 2: add the preds, succs, etc.
580 for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) {
581 SDNode *N = SU->Node;
582 NodeInfo *NI = getNI(N);
584 if (N->isTargetOpcode() && TII->isTwoAddrInstr(N->getTargetOpcode()))
585 SU->isTwoAddress = true;
587 if (NI->isInGroup()) {
588 // Find all predecessors (of the group).
589 NodeGroupOpIterator NGOI(NI);
590 while (!NGOI.isEnd()) {
591 SDOperand Op = NGOI.next();
592 SDNode *OpN = Op.Val;
593 MVT::ValueType VT = OpN->getValueType(Op.ResNo);
594 NodeInfo *OpNI = getNI(OpN);
595 if (OpNI->Group != NI->Group && !isPassiveNode(OpN)) {
596 assert(VT != MVT::Flag);
597 SUnit *OpSU = SUnitMap[OpN];
598 if (VT == MVT::Other) {
599 if (SU->ChainPreds.insert(OpSU).second)
600 SU->NumChainPredsLeft++;
601 if (OpSU->ChainSuccs.insert(SU).second)
602 OpSU->NumChainSuccsLeft++;
604 if (SU->Preds.insert(OpSU).second)
606 if (OpSU->Succs.insert(SU).second)
607 OpSU->NumSuccsLeft++;
612 // Find node predecessors.
613 for (unsigned j = 0, e = N->getNumOperands(); j != e; j++) {
614 SDOperand Op = N->getOperand(j);
615 SDNode *OpN = Op.Val;
616 MVT::ValueType VT = OpN->getValueType(Op.ResNo);
617 if (!isPassiveNode(OpN)) {
618 assert(VT != MVT::Flag);
619 SUnit *OpSU = SUnitMap[OpN];
620 if (VT == MVT::Other) {
621 if (SU->ChainPreds.insert(OpSU).second)
622 SU->NumChainPredsLeft++;
623 if (OpSU->ChainSuccs.insert(SU).second)
624 OpSU->NumChainSuccsLeft++;
626 if (SU->Preds.insert(OpSU).second)
628 if (OpSU->Succs.insert(SU).second)
629 OpSU->NumSuccsLeft++;
630 if (j == 0 && SU->isTwoAddress)
631 OpSU->isDefNUseOperand = true;
639 /// EmitSchedule - Emit the machine code in scheduled order.
640 void ScheduleDAGList::EmitSchedule() {
641 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
642 if (SUnit *SU = Sequence[i]) {
643 for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++) {
644 SDNode *N = SU->FlaggedNodes[j];
647 EmitNode(getNI(SU->Node));
649 // Null SUnit* is a noop.
655 /// dump - dump the schedule.
656 void ScheduleDAGList::dump() const {
657 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
658 if (SUnit *SU = Sequence[i])
659 SU->dump(&DAG, false);
661 std::cerr << "**** NOOP ****\n";
665 /// Schedule - Schedule the DAG using list scheduling.
666 /// FIXME: Right now it only supports the burr (bottom up register reducing)
668 void ScheduleDAGList::Schedule() {
669 DEBUG(std::cerr << "********** List Scheduling **********\n");
671 // Build scheduling units.
674 // Calculate node priorities.
675 CalculatePriorities();
677 // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
679 ListScheduleBottomUp();
681 ListScheduleTopDown();
683 DEBUG(std::cerr << "*** Final schedule ***\n");
685 DEBUG(std::cerr << "\n");
687 // Emit in scheduled order
691 llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG &DAG,
692 MachineBasicBlock *BB) {
693 return new ScheduleDAGList(DAG, BB, DAG.getTarget(), true,
694 new HazardRecognizer());
697 /// createTDListDAGScheduler - This creates a top-down list scheduler with the
698 /// specified hazard recognizer.
699 ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAG &DAG,
700 MachineBasicBlock *BB,
701 HazardRecognizer *HR) {
702 return new ScheduleDAGList(DAG, BB, DAG.getTarget(), false, HR);