1 //===----- ScheduleDAGList.cpp - Reg pressure reduction list scheduler ----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements bottom-up and top-down register pressure reduction list
11 // schedulers, using standard algorithms. The basic approach uses a priority
12 // queue of available nodes to schedule. One at a time, nodes are taken from
13 // the priority queue (thus in priority order), checked for legality to
14 // schedule, and emitted if legal.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "pre-RA-sched"
19 #include "llvm/CodeGen/ScheduleDAG.h"
20 #include "llvm/CodeGen/SchedulerRegistry.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/ADT/SmallPtrSet.h"
29 #include "llvm/ADT/SmallSet.h"
30 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Support/CommandLine.h"
36 STATISTIC(NumBacktracks, "Number of times scheduler backtraced");
37 STATISTIC(NumUnfolds, "Number of nodes unfolded");
38 STATISTIC(NumDups, "Number of duplicated nodes");
39 STATISTIC(NumCCCopies, "Number of cross class copies");
41 static RegisterScheduler
42 burrListDAGScheduler("list-burr",
43 " Bottom-up register reduction list scheduling",
44 createBURRListDAGScheduler);
45 static RegisterScheduler
46 tdrListrDAGScheduler("list-tdrr",
47 " Top-down register reduction list scheduling",
48 createTDRRListDAGScheduler);
51 //===----------------------------------------------------------------------===//
52 /// ScheduleDAGRRList - The actual register reduction list scheduler
53 /// implementation. This supports both top-down and bottom-up scheduling.
55 class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAG {
57 /// isBottomUp - This is true if the scheduling problem is bottom-up, false if
61 /// AvailableQueue - The priority queue to use for the available SUnits.
63 SchedulingPriorityQueue *AvailableQueue;
65 /// LiveRegs / LiveRegDefs - A set of physical registers and their definition
66 /// that are "live". These nodes must be scheduled before any other nodes that
67 /// modifies the registers can be scheduled.
68 SmallSet<unsigned, 4> LiveRegs;
69 std::vector<SUnit*> LiveRegDefs;
70 std::vector<unsigned> LiveRegCycles;
73 ScheduleDAGRRList(SelectionDAG &dag, MachineBasicBlock *bb,
74 const TargetMachine &tm, bool isbottomup,
75 SchedulingPriorityQueue *availqueue)
76 : ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup),
77 AvailableQueue(availqueue) {
80 ~ScheduleDAGRRList() {
81 delete AvailableQueue;
87 void ReleasePred(SUnit*, bool, unsigned);
88 void ReleaseSucc(SUnit*, bool isChain, unsigned);
89 void CapturePred(SUnit*, SUnit*, bool);
90 void ScheduleNodeBottomUp(SUnit*, unsigned);
91 void ScheduleNodeTopDown(SUnit*, unsigned);
92 void UnscheduleNodeBottomUp(SUnit*);
93 void BacktrackBottomUp(SUnit*, unsigned, unsigned&);
94 SUnit *CopyAndMoveSuccessors(SUnit*);
95 void InsertCCCopiesAndMoveSuccs(SUnit*, unsigned,
96 const TargetRegisterClass*,
97 const TargetRegisterClass*,
98 SmallVector<SUnit*, 2>&);
99 bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&);
100 void ListScheduleTopDown();
101 void ListScheduleBottomUp();
102 void CommuteNodesToReducePressure();
104 } // end anonymous namespace
107 /// Schedule - Schedule the DAG using list scheduling.
108 void ScheduleDAGRRList::Schedule() {
109 DOUT << "********** List Scheduling **********\n";
111 LiveRegDefs.resize(MRI->getNumRegs(), NULL);
112 LiveRegCycles.resize(MRI->getNumRegs(), 0);
114 // Build scheduling units.
117 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
118 SUnits[su].dumpAll(&DAG));
122 AvailableQueue->initNodes(SUnitMap, SUnits);
124 // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
126 ListScheduleBottomUp();
128 ListScheduleTopDown();
130 AvailableQueue->releaseState();
132 CommuteNodesToReducePressure();
134 DOUT << "*** Final schedule ***\n";
135 DEBUG(dumpSchedule());
138 // Emit in scheduled order
142 /// CommuteNodesToReducePressure - If a node is two-address and commutable, and
143 /// it is not the last use of its first operand, add it to the CommuteSet if
144 /// possible. It will be commuted when it is translated to a MI.
145 void ScheduleDAGRRList::CommuteNodesToReducePressure() {
146 SmallPtrSet<SUnit*, 4> OperandSeen;
147 for (unsigned i = Sequence.size()-1; i != 0; --i) { // Ignore first node.
148 SUnit *SU = Sequence[i];
149 if (!SU || !SU->Node) continue;
150 if (SU->isCommutable) {
151 unsigned Opc = SU->Node->getTargetOpcode();
152 unsigned NumRes = TII->getNumDefs(Opc);
153 unsigned NumOps = CountOperands(SU->Node);
154 for (unsigned j = 0; j != NumOps; ++j) {
155 if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) == -1)
158 SDNode *OpN = SU->Node->getOperand(j).Val;
159 SUnit *OpSU = SUnitMap[OpN][SU->InstanceNo];
160 if (OpSU && OperandSeen.count(OpSU) == 1) {
161 // Ok, so SU is not the last use of OpSU, but SU is two-address so
162 // it will clobber OpSU. Try to commute SU if no other source operands
164 bool DoCommute = true;
165 for (unsigned k = 0; k < NumOps; ++k) {
167 OpN = SU->Node->getOperand(k).Val;
168 OpSU = SUnitMap[OpN][SU->InstanceNo];
169 if (OpSU && OperandSeen.count(OpSU) == 1) {
176 CommuteSet.insert(SU->Node);
179 // Only look at the first use&def node for now.
184 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
187 OperandSeen.insert(I->Dep);
192 //===----------------------------------------------------------------------===//
193 // Bottom-Up Scheduling
194 //===----------------------------------------------------------------------===//
196 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
197 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
198 void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
200 // FIXME: the distance between two nodes is not always == the predecessor's
201 // latency. For example, the reader can very well read the register written
202 // by the predecessor later than the issue cycle. It also depends on the
203 // interrupt model (drain vs. freeze).
204 PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency);
206 --PredSU->NumSuccsLeft;
209 if (PredSU->NumSuccsLeft < 0) {
210 cerr << "*** List scheduling failed! ***\n";
212 cerr << " has been released too many times!\n";
217 if (PredSU->NumSuccsLeft == 0) {
218 // EntryToken has to go last! Special case it here.
219 if (!PredSU->Node || PredSU->Node->getOpcode() != ISD::EntryToken) {
220 PredSU->isAvailable = true;
221 AvailableQueue->push(PredSU);
226 /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
227 /// count of its predecessors. If a predecessor pending count is zero, add it to
228 /// the Available queue.
229 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
230 DOUT << "*** Scheduling [" << CurCycle << "]: ";
231 DEBUG(SU->dump(&DAG));
232 SU->Cycle = CurCycle;
234 AvailableQueue->ScheduledNode(SU);
236 // Bottom up: release predecessors
237 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
239 ReleasePred(I->Dep, I->isCtrl, CurCycle);
241 // This is a physical register dependency and it's impossible or
242 // expensive to copy the register. Make sure nothing that can
243 // clobber the register is scheduled between the predecessor and
245 if (LiveRegs.insert(I->Reg)) {
246 LiveRegDefs[I->Reg] = I->Dep;
247 LiveRegCycles[I->Reg] = CurCycle;
252 // Release all the implicit physical register defs that are live.
253 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
256 if (LiveRegCycles[I->Reg] == I->Dep->Cycle) {
257 LiveRegs.erase(I->Reg);
258 assert(LiveRegDefs[I->Reg] == SU &&
259 "Physical register dependency violated?");
260 LiveRegDefs[I->Reg] = NULL;
261 LiveRegCycles[I->Reg] = 0;
266 SU->isScheduled = true;
269 /// CapturePred - This does the opposite of ReleasePred. Since SU is being
270 /// unscheduled, incrcease the succ left count of its predecessors. Remove
271 /// them from AvailableQueue if necessary.
272 void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) {
273 PredSU->CycleBound = 0;
274 for (SUnit::succ_iterator I = PredSU->Succs.begin(), E = PredSU->Succs.end();
278 PredSU->CycleBound = std::max(PredSU->CycleBound,
279 I->Dep->Cycle + PredSU->Latency);
282 if (PredSU->isAvailable) {
283 PredSU->isAvailable = false;
284 if (!PredSU->isPending)
285 AvailableQueue->remove(PredSU);
288 ++PredSU->NumSuccsLeft;
291 /// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and
292 /// its predecessor states to reflect the change.
293 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
294 DOUT << "*** Unscheduling [" << SU->Cycle << "]: ";
295 DEBUG(SU->dump(&DAG));
297 AvailableQueue->UnscheduledNode(SU);
299 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
301 CapturePred(I->Dep, SU, I->isCtrl);
302 if (I->Cost < 0 && SU->Cycle == LiveRegCycles[I->Reg]) {
303 LiveRegs.erase(I->Reg);
304 assert(LiveRegDefs[I->Reg] == I->Dep &&
305 "Physical register dependency violated?");
306 LiveRegDefs[I->Reg] = NULL;
307 LiveRegCycles[I->Reg] = 0;
311 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
314 if (LiveRegs.insert(I->Reg)) {
315 assert(!LiveRegDefs[I->Reg] &&
316 "Physical register dependency violated?");
317 LiveRegDefs[I->Reg] = SU;
319 if (I->Dep->Cycle < LiveRegCycles[I->Reg])
320 LiveRegCycles[I->Reg] = I->Dep->Cycle;
325 SU->isScheduled = false;
326 SU->isAvailable = true;
327 AvailableQueue->push(SU);
330 // FIXME: This is probably too slow!
331 static void isReachable(SUnit *SU, SUnit *TargetSU,
332 SmallPtrSet<SUnit*, 32> &Visited, bool &Reached) {
334 if (SU == TargetSU) {
338 if (!Visited.insert(SU)) return;
340 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E;
342 isReachable(I->Dep, TargetSU, Visited, Reached);
345 static bool isReachable(SUnit *SU, SUnit *TargetSU) {
346 SmallPtrSet<SUnit*, 32> Visited;
347 bool Reached = false;
348 isReachable(SU, TargetSU, Visited, Reached);
352 /// willCreateCycle - Returns true if adding an edge from SU to TargetSU will
354 static bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
355 if (isReachable(TargetSU, SU))
357 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
359 if (I->Cost < 0 && isReachable(TargetSU, I->Dep))
364 /// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in
365 /// BTCycle in order to schedule a specific node. Returns the last unscheduled
366 /// SUnit. Also returns if a successor is unscheduled in the process.
367 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, unsigned BtCycle,
368 unsigned &CurCycle) {
370 while (CurCycle > BtCycle) {
371 OldSU = Sequence.back();
373 if (SU->isSucc(OldSU))
374 // Don't try to remove SU from AvailableQueue.
375 SU->isAvailable = false;
376 UnscheduleNodeBottomUp(OldSU);
381 if (SU->isSucc(OldSU)) {
382 assert(false && "Something is wrong!");
389 /// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
390 /// successors to the newly created node.
391 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
392 if (SU->FlaggedNodes.size())
395 SDNode *N = SU->Node;
400 bool TryUnfold = false;
401 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
402 MVT::ValueType VT = N->getValueType(i);
405 else if (VT == MVT::Other)
408 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
409 const SDOperand &Op = N->getOperand(i);
410 MVT::ValueType VT = Op.Val->getValueType(Op.ResNo);
416 SmallVector<SDNode*, 4> NewNodes;
417 if (!MRI->unfoldMemoryOperand(DAG, N, NewNodes))
420 DOUT << "Unfolding SU # " << SU->NodeNum << "\n";
421 assert(NewNodes.size() == 2 && "Expected a load folding node!");
424 SDNode *LoadNode = NewNodes[0];
425 unsigned NumVals = N->getNumValues();
426 unsigned OldNumVals = SU->Node->getNumValues();
427 for (unsigned i = 0; i != NumVals; ++i)
428 DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, i), SDOperand(N, i));
429 DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, OldNumVals-1),
430 SDOperand(LoadNode, 1));
432 SUnit *LoadSU = NewSUnit(LoadNode);
433 SUnit *NewSU = NewSUnit(N);
434 SUnitMap[LoadNode].push_back(LoadSU);
435 SUnitMap[N].push_back(NewSU);
436 const TargetInstrDescriptor *TID = &TII->get(LoadNode->getTargetOpcode());
437 for (unsigned i = 0; i != TID->numOperands; ++i) {
438 if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) {
439 LoadSU->isTwoAddress = true;
443 if (TID->Flags & M_COMMUTABLE)
444 LoadSU->isCommutable = true;
446 TID = &TII->get(N->getTargetOpcode());
447 for (unsigned i = 0; i != TID->numOperands; ++i) {
448 if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) {
449 NewSU->isTwoAddress = true;
453 if (TID->Flags & M_COMMUTABLE)
454 NewSU->isCommutable = true;
456 // FIXME: Calculate height / depth and propagate the changes?
457 LoadSU->Depth = NewSU->Depth = SU->Depth;
458 LoadSU->Height = NewSU->Height = SU->Height;
459 ComputeLatency(LoadSU);
460 ComputeLatency(NewSU);
462 SUnit *ChainPred = NULL;
463 SmallVector<SDep, 4> ChainSuccs;
464 SmallVector<SDep, 4> LoadPreds;
465 SmallVector<SDep, 4> NodePreds;
466 SmallVector<SDep, 4> NodeSuccs;
467 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
471 else if (I->Dep->Node && I->Dep->Node->isOperand(LoadNode))
472 LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false));
474 NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false));
476 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
479 ChainSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost,
480 I->isCtrl, I->isSpecial));
482 NodeSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost,
483 I->isCtrl, I->isSpecial));
486 SU->removePred(ChainPred, true, false);
487 LoadSU->addPred(ChainPred, true, false);
488 for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
489 SDep *Pred = &LoadPreds[i];
490 SU->removePred(Pred->Dep, Pred->isCtrl, Pred->isSpecial);
491 LoadSU->addPred(Pred->Dep, Pred->isCtrl, Pred->isSpecial,
492 Pred->Reg, Pred->Cost);
494 for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
495 SDep *Pred = &NodePreds[i];
496 SU->removePred(Pred->Dep, Pred->isCtrl, Pred->isSpecial);
497 NewSU->addPred(Pred->Dep, Pred->isCtrl, Pred->isSpecial,
498 Pred->Reg, Pred->Cost);
500 for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) {
501 SDep *Succ = &NodeSuccs[i];
502 Succ->Dep->removePred(SU, Succ->isCtrl, Succ->isSpecial);
503 Succ->Dep->addPred(NewSU, Succ->isCtrl, Succ->isSpecial,
504 Succ->Reg, Succ->Cost);
506 for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
507 SDep *Succ = &ChainSuccs[i];
508 Succ->Dep->removePred(SU, Succ->isCtrl, Succ->isSpecial);
509 Succ->Dep->addPred(LoadSU, Succ->isCtrl, Succ->isSpecial,
510 Succ->Reg, Succ->Cost);
512 NewSU->addPred(LoadSU, false, false);
514 AvailableQueue->addNode(LoadSU);
515 AvailableQueue->addNode(NewSU);
519 if (NewSU->NumSuccsLeft == 0) {
520 NewSU->isAvailable = true;
526 DOUT << "Duplicating SU # " << SU->NodeNum << "\n";
529 // New SUnit has the exact same predecessors.
530 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
533 NewSU->addPred(I->Dep, I->isCtrl, false, I->Reg, I->Cost);
534 NewSU->Depth = std::max(NewSU->Depth, I->Dep->Depth+1);
537 // Only copy scheduled successors. Cut them from old node's successor
538 // list and move them over.
539 SmallVector<std::pair<SUnit*, bool>, 4> DelDeps;
540 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
544 if (I->Dep->isScheduled) {
545 NewSU->Height = std::max(NewSU->Height, I->Dep->Height+1);
546 I->Dep->addPred(NewSU, I->isCtrl, false, I->Reg, I->Cost);
547 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
550 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
551 SUnit *Succ = DelDeps[i].first;
552 bool isCtrl = DelDeps[i].second;
553 Succ->removePred(SU, isCtrl, false);
556 AvailableQueue->updateNode(SU);
557 AvailableQueue->addNode(NewSU);
563 /// InsertCCCopiesAndMoveSuccs - Insert expensive cross register class copies
564 /// and move all scheduled successors of the given SUnit to the last copy.
565 void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
566 const TargetRegisterClass *DestRC,
567 const TargetRegisterClass *SrcRC,
568 SmallVector<SUnit*, 2> &Copies) {
569 SUnit *CopyFromSU = NewSUnit(NULL);
570 CopyFromSU->CopySrcRC = SrcRC;
571 CopyFromSU->CopyDstRC = DestRC;
572 CopyFromSU->Depth = SU->Depth;
573 CopyFromSU->Height = SU->Height;
575 SUnit *CopyToSU = NewSUnit(NULL);
576 CopyToSU->CopySrcRC = DestRC;
577 CopyToSU->CopyDstRC = SrcRC;
579 // Only copy scheduled successors. Cut them from old node's successor
580 // list and move them over.
581 SmallVector<std::pair<SUnit*, bool>, 4> DelDeps;
582 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
586 if (I->Dep->isScheduled) {
587 CopyToSU->Height = std::max(CopyToSU->Height, I->Dep->Height+1);
588 I->Dep->addPred(CopyToSU, I->isCtrl, false, I->Reg, I->Cost);
589 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
592 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
593 SUnit *Succ = DelDeps[i].first;
594 bool isCtrl = DelDeps[i].second;
595 Succ->removePred(SU, isCtrl, false);
598 CopyFromSU->addPred(SU, false, false, Reg, -1);
599 CopyToSU->addPred(CopyFromSU, false, false, Reg, 1);
601 AvailableQueue->updateNode(SU);
602 AvailableQueue->addNode(CopyFromSU);
603 AvailableQueue->addNode(CopyToSU);
604 Copies.push_back(CopyFromSU);
605 Copies.push_back(CopyToSU);
610 /// getPhysicalRegisterVT - Returns the ValueType of the physical register
611 /// definition of the specified node.
612 /// FIXME: Move to SelectionDAG?
613 static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg,
614 const TargetInstrInfo *TII) {
615 const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
616 assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
617 unsigned NumRes = TID.numDefs;
618 for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef) {
623 return N->getValueType(NumRes);
626 /// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
627 /// scheduling of the given node to satisfy live physical register dependencies.
628 /// If the specific node is the last one that's available to schedule, do
629 /// whatever is necessary (i.e. backtracking or cloning) to make it possible.
630 bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
631 SmallVector<unsigned, 4> &LRegs){
632 if (LiveRegs.empty())
635 SmallSet<unsigned, 4> RegAdded;
636 // If this node would clobber any "live" register, then it's not ready.
637 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
640 unsigned Reg = I->Reg;
641 if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) {
642 if (RegAdded.insert(Reg))
643 LRegs.push_back(Reg);
645 for (const unsigned *Alias = MRI->getAliasSet(Reg);
647 if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
648 if (RegAdded.insert(*Alias))
649 LRegs.push_back(*Alias);
654 for (unsigned i = 0, e = SU->FlaggedNodes.size()+1; i != e; ++i) {
655 SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
656 if (!Node || !Node->isTargetOpcode())
658 const TargetInstrDescriptor &TID = TII->get(Node->getTargetOpcode());
659 if (!TID.ImplicitDefs)
661 for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
662 if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) {
663 if (RegAdded.insert(*Reg))
664 LRegs.push_back(*Reg);
666 for (const unsigned *Alias = MRI->getAliasSet(*Reg);
668 if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
669 if (RegAdded.insert(*Alias))
670 LRegs.push_back(*Alias);
674 return !LRegs.empty();
678 /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
680 void ScheduleDAGRRList::ListScheduleBottomUp() {
681 unsigned CurCycle = 0;
682 // Add root to Available queue.
683 SUnit *RootSU = SUnitMap[DAG.getRoot().Val].front();
684 RootSU->isAvailable = true;
685 AvailableQueue->push(RootSU);
687 // While Available queue is not empty, grab the node with the highest
688 // priority. If it is not ready put it back. Schedule the node.
689 SmallVector<SUnit*, 4> NotReady;
690 while (!AvailableQueue->empty()) {
691 bool Delayed = false;
692 DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap;
693 SUnit *CurSU = AvailableQueue->pop();
695 if (CurSU->CycleBound <= CurCycle) {
696 SmallVector<unsigned, 4> LRegs;
697 if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
700 LRegsMap.insert(std::make_pair(CurSU, LRegs));
703 CurSU->isPending = true; // This SU is not in AvailableQueue right now.
704 NotReady.push_back(CurSU);
705 CurSU = AvailableQueue->pop();
708 // All candidates are delayed due to live physical reg dependencies.
709 // Try backtracking, code duplication, or inserting cross class copies
711 if (Delayed && !CurSU) {
712 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
713 SUnit *TrySU = NotReady[i];
714 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
716 // Try unscheduling up to the point where it's safe to schedule
718 unsigned LiveCycle = CurCycle;
719 for (unsigned j = 0, ee = LRegs.size(); j != ee; ++j) {
720 unsigned Reg = LRegs[j];
721 unsigned LCycle = LiveRegCycles[Reg];
722 LiveCycle = std::min(LiveCycle, LCycle);
724 SUnit *OldSU = Sequence[LiveCycle];
725 if (!WillCreateCycle(TrySU, OldSU)) {
726 BacktrackBottomUp(TrySU, LiveCycle, CurCycle);
727 // Force the current node to be scheduled before the node that
728 // requires the physical reg dep.
729 if (OldSU->isAvailable) {
730 OldSU->isAvailable = false;
731 AvailableQueue->remove(OldSU);
733 TrySU->addPred(OldSU, true, true);
734 // If one or more successors has been unscheduled, then the current
735 // node is no longer avaialable. Schedule a successor that's now
736 // available instead.
737 if (!TrySU->isAvailable)
738 CurSU = AvailableQueue->pop();
741 TrySU->isPending = false;
742 NotReady.erase(NotReady.begin()+i);
749 // Can't backtrace. Try duplicating the nodes that produces these
750 // "expensive to copy" values to break the dependency. In case even
751 // that doesn't work, insert cross class copies.
752 SUnit *TrySU = NotReady[0];
753 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
754 assert(LRegs.size() == 1 && "Can't handle this yet!");
755 unsigned Reg = LRegs[0];
756 SUnit *LRDef = LiveRegDefs[Reg];
757 SUnit *NewDef = CopyAndMoveSuccessors(LRDef);
759 // Issue expensive cross register class copies.
760 MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII);
761 const TargetRegisterClass *RC =
762 MRI->getPhysicalRegisterRegClass(VT, Reg);
763 const TargetRegisterClass *DestRC = MRI->getCrossCopyRegClass(RC);
765 assert(false && "Don't know how to copy this physical register!");
768 SmallVector<SUnit*, 2> Copies;
769 InsertCCCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
770 DOUT << "Adding an edge from SU # " << TrySU->NodeNum
771 << " to SU #" << Copies.front()->NodeNum << "\n";
772 TrySU->addPred(Copies.front(), true, true);
773 NewDef = Copies.back();
776 DOUT << "Adding an edge from SU # " << NewDef->NodeNum
777 << " to SU #" << TrySU->NodeNum << "\n";
778 LiveRegDefs[Reg] = NewDef;
779 NewDef->addPred(TrySU, true, true);
780 TrySU->isAvailable = false;
785 assert(false && "Unable to resolve live physical register dependencies!");
790 // Add the nodes that aren't ready back onto the available list.
791 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
792 NotReady[i]->isPending = false;
793 // May no longer be available due to backtracking.
794 if (NotReady[i]->isAvailable)
795 AvailableQueue->push(NotReady[i]);
800 Sequence.push_back(0);
802 ScheduleNodeBottomUp(CurSU, CurCycle);
803 Sequence.push_back(CurSU);
808 // Add entry node last
809 if (DAG.getEntryNode().Val != DAG.getRoot().Val) {
810 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val].front();
811 Sequence.push_back(Entry);
814 // Reverse the order if it is bottom up.
815 std::reverse(Sequence.begin(), Sequence.end());
819 // Verify that all SUnits were scheduled.
820 bool AnyNotSched = false;
821 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
822 if (SUnits[i].NumSuccsLeft != 0) {
824 cerr << "*** List scheduling failed! ***\n";
825 SUnits[i].dump(&DAG);
826 cerr << "has not been scheduled!\n";
830 assert(!AnyNotSched);
834 //===----------------------------------------------------------------------===//
835 // Top-Down Scheduling
836 //===----------------------------------------------------------------------===//
838 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
839 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
840 void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain,
842 // FIXME: the distance between two nodes is not always == the predecessor's
843 // latency. For example, the reader can very well read the register written
844 // by the predecessor later than the issue cycle. It also depends on the
845 // interrupt model (drain vs. freeze).
846 SuccSU->CycleBound = std::max(SuccSU->CycleBound, CurCycle + SuccSU->Latency);
848 --SuccSU->NumPredsLeft;
851 if (SuccSU->NumPredsLeft < 0) {
852 cerr << "*** List scheduling failed! ***\n";
854 cerr << " has been released too many times!\n";
859 if (SuccSU->NumPredsLeft == 0) {
860 SuccSU->isAvailable = true;
861 AvailableQueue->push(SuccSU);
866 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
867 /// count of its successors. If a successor pending count is zero, add it to
868 /// the Available queue.
869 void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
870 DOUT << "*** Scheduling [" << CurCycle << "]: ";
871 DEBUG(SU->dump(&DAG));
872 SU->Cycle = CurCycle;
874 AvailableQueue->ScheduledNode(SU);
876 // Top down: release successors
877 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
879 ReleaseSucc(I->Dep, I->isCtrl, CurCycle);
880 SU->isScheduled = true;
883 /// ListScheduleTopDown - The main loop of list scheduling for top-down
885 void ScheduleDAGRRList::ListScheduleTopDown() {
886 unsigned CurCycle = 0;
887 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val].front();
889 // All leaves to Available queue.
890 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
891 // It is available if it has no predecessors.
892 if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
893 AvailableQueue->push(&SUnits[i]);
894 SUnits[i].isAvailable = true;
898 // Emit the entry node first.
899 ScheduleNodeTopDown(Entry, CurCycle);
900 Sequence.push_back(Entry);
903 // While Available queue is not empty, grab the node with the highest
904 // priority. If it is not ready put it back. Schedule the node.
905 std::vector<SUnit*> NotReady;
906 while (!AvailableQueue->empty()) {
907 SUnit *CurSU = AvailableQueue->pop();
908 while (CurSU && CurSU->CycleBound > CurCycle) {
909 NotReady.push_back(CurSU);
910 CurSU = AvailableQueue->pop();
913 // Add the nodes that aren't ready back onto the available list.
914 AvailableQueue->push_all(NotReady);
918 Sequence.push_back(0);
920 ScheduleNodeTopDown(CurSU, CurCycle);
921 Sequence.push_back(CurSU);
928 // Verify that all SUnits were scheduled.
929 bool AnyNotSched = false;
930 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
931 if (!SUnits[i].isScheduled) {
933 cerr << "*** List scheduling failed! ***\n";
934 SUnits[i].dump(&DAG);
935 cerr << "has not been scheduled!\n";
939 assert(!AnyNotSched);
945 //===----------------------------------------------------------------------===//
946 // RegReductionPriorityQueue Implementation
947 //===----------------------------------------------------------------------===//
949 // This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
950 // to reduce register pressure.
954 class RegReductionPriorityQueue;
956 /// Sorting functions for the Available queue.
957 struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
958 RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ;
959 bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {}
960 bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
962 bool operator()(const SUnit* left, const SUnit* right) const;
965 struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
966 RegReductionPriorityQueue<td_ls_rr_sort> *SPQ;
967 td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {}
968 td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
970 bool operator()(const SUnit* left, const SUnit* right) const;
972 } // end anonymous namespace
974 static inline bool isCopyFromLiveIn(const SUnit *SU) {
975 SDNode *N = SU->Node;
976 return N && N->getOpcode() == ISD::CopyFromReg &&
977 N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag;
982 class VISIBILITY_HIDDEN RegReductionPriorityQueue
983 : public SchedulingPriorityQueue {
984 std::priority_queue<SUnit*, std::vector<SUnit*>, SF> Queue;
987 RegReductionPriorityQueue() :
990 virtual void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap,
991 std::vector<SUnit> &sunits) {}
993 virtual void addNode(const SUnit *SU) {}
995 virtual void updateNode(const SUnit *SU) {}
997 virtual void releaseState() {}
999 virtual unsigned getNodePriority(const SUnit *SU) const {
1003 unsigned size() const { return Queue.size(); }
1005 bool empty() const { return Queue.empty(); }
1007 void push(SUnit *U) {
1010 void push_all(const std::vector<SUnit *> &Nodes) {
1011 for (unsigned i = 0, e = Nodes.size(); i != e; ++i)
1012 Queue.push(Nodes[i]);
1016 if (empty()) return NULL;
1017 SUnit *V = Queue.top();
1022 /// remove - This is a really inefficient way to remove a node from a
1023 /// priority queue. We should roll our own heap to make this better or
1025 void remove(SUnit *SU) {
1026 std::vector<SUnit*> Temp;
1028 assert(!Queue.empty() && "Not in queue!");
1029 while (Queue.top() != SU) {
1030 Temp.push_back(Queue.top());
1032 assert(!Queue.empty() && "Not in queue!");
1035 // Remove the node from the PQ.
1038 // Add all the other nodes back.
1039 for (unsigned i = 0, e = Temp.size(); i != e; ++i)
1040 Queue.push(Temp[i]);
1045 class VISIBILITY_HIDDEN BURegReductionPriorityQueue
1046 : public RegReductionPriorityQueue<SF> {
1047 // SUnitMap SDNode to SUnit mapping (n -> n).
1048 DenseMap<SDNode*, std::vector<SUnit*> > *SUnitMap;
1050 // SUnits - The SUnits for the current graph.
1051 const std::vector<SUnit> *SUnits;
1053 // SethiUllmanNumbers - The SethiUllman number for each node.
1054 std::vector<unsigned> SethiUllmanNumbers;
1056 const TargetInstrInfo *TII;
1058 explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii)
1061 void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap,
1062 std::vector<SUnit> &sunits) {
1065 // Add pseudo dependency edges for two-address nodes.
1066 AddPseudoTwoAddrDeps();
1067 // Calculate node priorities.
1068 CalculateSethiUllmanNumbers();
1071 void addNode(const SUnit *SU) {
1072 SethiUllmanNumbers.resize(SUnits->size(), 0);
1073 CalcNodeSethiUllmanNumber(SU);
1076 void updateNode(const SUnit *SU) {
1077 SethiUllmanNumbers[SU->NodeNum] = 0;
1078 CalcNodeSethiUllmanNumber(SU);
1081 void releaseState() {
1083 SethiUllmanNumbers.clear();
1086 unsigned getNodePriority(const SUnit *SU) const {
1087 assert(SU->NodeNum < SethiUllmanNumbers.size());
1088 unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0;
1089 if (Opc == ISD::CopyFromReg && !isCopyFromLiveIn(SU))
1090 // CopyFromReg should be close to its def because it restricts
1091 // allocation choices. But if it is a livein then perhaps we want it
1092 // closer to its uses so it can be coalesced.
1094 else if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
1095 // CopyToReg should be close to its uses to facilitate coalescing and
1098 else if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
1099 Opc == TargetInstrInfo::INSERT_SUBREG)
1100 // EXTRACT_SUBREG / INSERT_SUBREG should be close to its use to
1101 // facilitate coalescing.
1103 else if (SU->NumSuccs == 0)
1104 // If SU does not have a use, i.e. it doesn't produce a value that would
1105 // be consumed (e.g. store), then it terminates a chain of computation.
1106 // Give it a large SethiUllman number so it will be scheduled right
1107 // before its predecessors that it doesn't lengthen their live ranges.
1109 else if (SU->NumPreds == 0)
1110 // If SU does not have a def, schedule it close to its uses because it
1111 // does not lengthen any live ranges.
1114 return SethiUllmanNumbers[SU->NodeNum];
1118 bool canClobber(SUnit *SU, SUnit *Op);
1119 void AddPseudoTwoAddrDeps();
1120 void CalculateSethiUllmanNumbers();
1121 unsigned CalcNodeSethiUllmanNumber(const SUnit *SU);
1126 class VISIBILITY_HIDDEN TDRegReductionPriorityQueue
1127 : public RegReductionPriorityQueue<SF> {
1128 // SUnitMap SDNode to SUnit mapping (n -> n).
1129 DenseMap<SDNode*, std::vector<SUnit*> > *SUnitMap;
1131 // SUnits - The SUnits for the current graph.
1132 const std::vector<SUnit> *SUnits;
1134 // SethiUllmanNumbers - The SethiUllman number for each node.
1135 std::vector<unsigned> SethiUllmanNumbers;
1138 TDRegReductionPriorityQueue() {}
1140 void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap,
1141 std::vector<SUnit> &sunits) {
1144 // Calculate node priorities.
1145 CalculateSethiUllmanNumbers();
1148 void addNode(const SUnit *SU) {
1149 SethiUllmanNumbers.resize(SUnits->size(), 0);
1150 CalcNodeSethiUllmanNumber(SU);
1153 void updateNode(const SUnit *SU) {
1154 SethiUllmanNumbers[SU->NodeNum] = 0;
1155 CalcNodeSethiUllmanNumber(SU);
1158 void releaseState() {
1160 SethiUllmanNumbers.clear();
1163 unsigned getNodePriority(const SUnit *SU) const {
1164 assert(SU->NodeNum < SethiUllmanNumbers.size());
1165 return SethiUllmanNumbers[SU->NodeNum];
1169 void CalculateSethiUllmanNumbers();
1170 unsigned CalcNodeSethiUllmanNumber(const SUnit *SU);
1174 /// closestSucc - Returns the scheduled cycle of the successor which is
1175 /// closet to the current cycle.
1176 static unsigned closestSucc(const SUnit *SU) {
1177 unsigned MaxCycle = 0;
1178 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1180 unsigned Cycle = I->Dep->Cycle;
1181 // If there are bunch of CopyToRegs stacked up, they should be considered
1182 // to be at the same position.
1183 if (I->Dep->Node && I->Dep->Node->getOpcode() == ISD::CopyToReg)
1184 Cycle = closestSucc(I->Dep)+1;
1185 if (Cycle > MaxCycle)
1192 bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
1193 // There used to be a special tie breaker here that looked for
1194 // two-address instructions and preferred the instruction with a
1195 // def&use operand. The special case triggered diagnostics when
1196 // _GLIBCXX_DEBUG was enabled because it broke the strict weak
1197 // ordering that priority_queue requires. It didn't help much anyway
1198 // because AddPseudoTwoAddrDeps already covers many of the cases
1199 // where it would have applied. In addition, it's counter-intuitive
1200 // that a tie breaker would be the first thing attempted. There's a
1201 // "real" tie breaker below that is the operation of last resort.
1202 // The fact that the "special tie breaker" would trigger when there
1203 // wasn't otherwise a tie is what broke the strict weak ordering
1206 unsigned LPriority = SPQ->getNodePriority(left);
1207 unsigned RPriority = SPQ->getNodePriority(right);
1208 if (LPriority > RPriority)
1210 else if (LPriority == RPriority) {
1211 // Try schedule def + use closer when Sethi-Ullman numbers are the same.
1216 // and the following instructions are both ready.
1220 // Then schedule t2 = op first.
1227 // This creates more short live intervals.
1228 unsigned LDist = closestSucc(left);
1229 unsigned RDist = closestSucc(right);
1232 else if (LDist == RDist) {
1233 if (left->Height > right->Height)
1235 else if (left->Height == right->Height)
1236 if (left->Depth < right->Depth)
1238 else if (left->Depth == right->Depth)
1239 if (left->CycleBound > right->CycleBound)
1247 bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) {
1248 if (SU->isTwoAddress) {
1249 unsigned Opc = SU->Node->getTargetOpcode();
1250 unsigned NumRes = TII->getNumDefs(Opc);
1251 unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
1252 for (unsigned i = 0; i != NumOps; ++i) {
1253 if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) != -1) {
1254 SDNode *DU = SU->Node->getOperand(i).Val;
1255 if (Op == (*SUnitMap)[DU][SU->InstanceNo])
1264 /// hasCopyToRegUse - Return true if SU has a value successor that is a
1266 static bool hasCopyToRegUse(SUnit *SU) {
1267 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1269 if (I->isCtrl) continue;
1270 SUnit *SuccSU = I->Dep;
1271 if (SuccSU->Node && SuccSU->Node->getOpcode() == ISD::CopyToReg)
1277 /// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
1278 /// it as a def&use operand. Add a pseudo control edge from it to the other
1279 /// node (if it won't create a cycle) so the two-address one will be scheduled
1280 /// first (lower in the schedule). If both nodes are two-address, favor the
1281 /// one that has a CopyToReg use (more likely to be a loop induction update).
1282 /// If both are two-address, but one is commutable while the other is not
1283 /// commutable, favor the one that's not commutable.
1285 void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
1286 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
1287 SUnit *SU = (SUnit *)&((*SUnits)[i]);
1288 if (!SU->isTwoAddress)
1291 SDNode *Node = SU->Node;
1292 if (!Node || !Node->isTargetOpcode() || SU->FlaggedNodes.size() > 0)
1295 unsigned Opc = Node->getTargetOpcode();
1296 unsigned NumRes = TII->getNumDefs(Opc);
1297 unsigned NumOps = ScheduleDAG::CountOperands(Node);
1298 for (unsigned j = 0; j != NumOps; ++j) {
1299 if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) != -1) {
1300 SDNode *DU = SU->Node->getOperand(j).Val;
1301 SUnit *DUSU = (*SUnitMap)[DU][SU->InstanceNo];
1302 if (!DUSU) continue;
1303 for (SUnit::succ_iterator I = DUSU->Succs.begin(),E = DUSU->Succs.end();
1305 if (I->isCtrl) continue;
1306 SUnit *SuccSU = I->Dep;
1307 // Don't constrain nodes with implicit defs. It can create cycles
1308 // plus it may increase register pressures.
1309 if (SuccSU == SU || SuccSU->hasPhysRegDefs)
1311 // Be conservative. Ignore if nodes aren't at the same depth.
1312 if (SuccSU->Depth != SU->Depth)
1314 if (!SuccSU->Node || !SuccSU->Node->isTargetOpcode())
1316 // Don't constraint extract_subreg / insert_subreg these may be
1317 // coalesced away. We don't them close to their uses.
1318 unsigned SuccOpc = SuccSU->Node->getTargetOpcode();
1319 if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG ||
1320 SuccOpc == TargetInstrInfo::INSERT_SUBREG)
1322 if ((!canClobber(SuccSU, DUSU) ||
1323 (hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) ||
1324 (!SU->isCommutable && SuccSU->isCommutable)) &&
1325 !isReachable(SuccSU, SU)) {
1326 DOUT << "Adding an edge from SU # " << SU->NodeNum
1327 << " to SU #" << SuccSU->NodeNum << "\n";
1328 SU->addPred(SuccSU, true, true);
1336 /// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
1337 /// Smaller number is the higher priority.
1339 unsigned BURegReductionPriorityQueue<SF>::
1340 CalcNodeSethiUllmanNumber(const SUnit *SU) {
1341 unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
1342 if (SethiUllmanNumber != 0)
1343 return SethiUllmanNumber;
1346 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1348 if (I->isCtrl) continue; // ignore chain preds
1349 SUnit *PredSU = I->Dep;
1350 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU);
1351 if (PredSethiUllman > SethiUllmanNumber) {
1352 SethiUllmanNumber = PredSethiUllman;
1354 } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl)
1358 SethiUllmanNumber += Extra;
1360 if (SethiUllmanNumber == 0)
1361 SethiUllmanNumber = 1;
1363 return SethiUllmanNumber;
1366 /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
1367 /// scheduling units.
1369 void BURegReductionPriorityQueue<SF>::CalculateSethiUllmanNumbers() {
1370 SethiUllmanNumbers.assign(SUnits->size(), 0);
1372 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
1373 CalcNodeSethiUllmanNumber(&(*SUnits)[i]);
1376 static unsigned SumOfUnscheduledPredsOfSuccs(const SUnit *SU) {
1378 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1380 SUnit *SuccSU = I->Dep;
1381 for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(),
1382 EE = SuccSU->Preds.end(); II != EE; ++II) {
1383 SUnit *PredSU = II->Dep;
1384 if (!PredSU->isScheduled)
1394 bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
1395 unsigned LPriority = SPQ->getNodePriority(left);
1396 unsigned RPriority = SPQ->getNodePriority(right);
1397 bool LIsTarget = left->Node && left->Node->isTargetOpcode();
1398 bool RIsTarget = right->Node && right->Node->isTargetOpcode();
1399 bool LIsFloater = LIsTarget && left->NumPreds == 0;
1400 bool RIsFloater = RIsTarget && right->NumPreds == 0;
1401 unsigned LBonus = (SumOfUnscheduledPredsOfSuccs(left) == 1) ? 2 : 0;
1402 unsigned RBonus = (SumOfUnscheduledPredsOfSuccs(right) == 1) ? 2 : 0;
1404 if (left->NumSuccs == 0 && right->NumSuccs != 0)
1406 else if (left->NumSuccs != 0 && right->NumSuccs == 0)
1409 // Special tie breaker: if two nodes share a operand, the one that use it
1410 // as a def&use operand is preferred.
1411 if (LIsTarget && RIsTarget) {
1412 if (left->isTwoAddress && !right->isTwoAddress) {
1413 SDNode *DUNode = left->Node->getOperand(0).Val;
1414 if (DUNode->isOperand(right->Node))
1417 if (!left->isTwoAddress && right->isTwoAddress) {
1418 SDNode *DUNode = right->Node->getOperand(0).Val;
1419 if (DUNode->isOperand(left->Node))
1427 if (left->NumSuccs == 1)
1429 if (right->NumSuccs == 1)
1432 if (LPriority+LBonus < RPriority+RBonus)
1434 else if (LPriority == RPriority)
1435 if (left->Depth < right->Depth)
1437 else if (left->Depth == right->Depth)
1438 if (left->NumSuccsLeft > right->NumSuccsLeft)
1440 else if (left->NumSuccsLeft == right->NumSuccsLeft)
1441 if (left->CycleBound > right->CycleBound)
1446 /// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
1447 /// Smaller number is the higher priority.
1449 unsigned TDRegReductionPriorityQueue<SF>::
1450 CalcNodeSethiUllmanNumber(const SUnit *SU) {
1451 unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
1452 if (SethiUllmanNumber != 0)
1453 return SethiUllmanNumber;
1455 unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0;
1456 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
1457 SethiUllmanNumber = 0xffff;
1458 else if (SU->NumSuccsLeft == 0)
1459 // If SU does not have a use, i.e. it doesn't produce a value that would
1460 // be consumed (e.g. store), then it terminates a chain of computation.
1461 // Give it a small SethiUllman number so it will be scheduled right before
1462 // its predecessors that it doesn't lengthen their live ranges.
1463 SethiUllmanNumber = 0;
1464 else if (SU->NumPredsLeft == 0 &&
1465 (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
1466 SethiUllmanNumber = 0xffff;
1469 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1471 if (I->isCtrl) continue; // ignore chain preds
1472 SUnit *PredSU = I->Dep;
1473 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU);
1474 if (PredSethiUllman > SethiUllmanNumber) {
1475 SethiUllmanNumber = PredSethiUllman;
1477 } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl)
1481 SethiUllmanNumber += Extra;
1484 return SethiUllmanNumber;
1487 /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
1488 /// scheduling units.
1490 void TDRegReductionPriorityQueue<SF>::CalculateSethiUllmanNumbers() {
1491 SethiUllmanNumbers.assign(SUnits->size(), 0);
1493 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
1494 CalcNodeSethiUllmanNumber(&(*SUnits)[i]);
1497 //===----------------------------------------------------------------------===//
1498 // Public Constructor Functions
1499 //===----------------------------------------------------------------------===//
1501 llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
1503 MachineBasicBlock *BB) {
1504 const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo();
1505 return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true,
1506 new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII));
1509 llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
1511 MachineBasicBlock *BB) {
1512 return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false,
1513 new TDRegReductionPriorityQueue<td_ls_rr_sort>());