1 //===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements bottom-up and top-down register pressure reduction list
11 // schedulers, using standard algorithms. The basic approach uses a priority
12 // queue of available nodes to schedule. One at a time, nodes are taken from
13 // the priority queue (thus in priority order), checked for legality to
14 // schedule, and emitted if legal.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "pre-RA-sched"
19 #include "ScheduleDAGSDNodes.h"
20 #include "llvm/CodeGen/SchedulerRegistry.h"
21 #include "llvm/CodeGen/SelectionDAGISel.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/ADT/PriorityQueue.h"
29 #include "llvm/ADT/SmallSet.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/ADT/STLExtras.h"
35 STATISTIC(NumBacktracks, "Number of times scheduler backtracked");
36 STATISTIC(NumUnfolds, "Number of nodes unfolded");
37 STATISTIC(NumDups, "Number of duplicated nodes");
38 STATISTIC(NumPRCopies, "Number of physical register copies");
40 static RegisterScheduler
41 burrListDAGScheduler("list-burr",
42 "Bottom-up register reduction list scheduling",
43 createBURRListDAGScheduler);
44 static RegisterScheduler
45 tdrListrDAGScheduler("list-tdrr",
46 "Top-down register reduction list scheduling",
47 createTDRRListDAGScheduler);
50 //===----------------------------------------------------------------------===//
51 /// ScheduleDAGRRList - The actual register reduction list scheduler
52 /// implementation. This supports both top-down and bottom-up scheduling.
54 class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAGSDNodes {
56 /// isBottomUp - This is true if the scheduling problem is bottom-up, false if
60 /// AvailableQueue - The priority queue to use for the available SUnits.
61 SchedulingPriorityQueue *AvailableQueue;
63 /// LiveRegDefs - A set of physical registers and their definition
64 /// that are "live". These nodes must be scheduled before any other nodes that
65 /// modifies the registers can be scheduled.
67 std::vector<SUnit*> LiveRegDefs;
68 std::vector<unsigned> LiveRegCycles;
70 /// Topo - A topological ordering for SUnits which permits fast IsReachable
71 /// and similar queries.
72 ScheduleDAGTopologicalSort Topo;
75 ScheduleDAGRRList(MachineFunction &mf,
77 SchedulingPriorityQueue *availqueue)
78 : ScheduleDAGSDNodes(mf), isBottomUp(isbottomup),
79 AvailableQueue(availqueue), Topo(SUnits) {
82 ~ScheduleDAGRRList() {
83 delete AvailableQueue;
88 /// IsReachable - Checks if SU is reachable from TargetSU.
89 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
90 return Topo.IsReachable(SU, TargetSU);
93 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
95 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
96 return Topo.WillCreateCycle(SU, TargetSU);
99 /// AddPred - adds a predecessor edge to SUnit SU.
100 /// This returns true if this is a new predecessor.
101 /// Updates the topological ordering if required.
102 void AddPred(SUnit *SU, const SDep &D) {
103 Topo.AddPred(SU, D.getSUnit());
107 /// RemovePred - removes a predecessor edge from SUnit SU.
108 /// This returns true if an edge was removed.
109 /// Updates the topological ordering if required.
110 void RemovePred(SUnit *SU, const SDep &D) {
111 Topo.RemovePred(SU, D.getSUnit());
116 void ReleasePred(SUnit *SU, const SDep *PredEdge);
117 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
118 void ReleaseSucc(SUnit *SU, const SDep *SuccEdge);
119 void ReleaseSuccessors(SUnit *SU);
120 void CapturePred(SDep *PredEdge);
121 void ScheduleNodeBottomUp(SUnit*, unsigned);
122 void ScheduleNodeTopDown(SUnit*, unsigned);
123 void UnscheduleNodeBottomUp(SUnit*);
124 void BacktrackBottomUp(SUnit*, unsigned, unsigned&);
125 SUnit *CopyAndMoveSuccessors(SUnit*);
126 void InsertCopiesAndMoveSuccs(SUnit*, unsigned,
127 const TargetRegisterClass*,
128 const TargetRegisterClass*,
129 SmallVector<SUnit*, 2>&);
130 bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&);
131 void ListScheduleTopDown();
132 void ListScheduleBottomUp();
135 /// CreateNewSUnit - Creates a new SUnit and returns a pointer to it.
136 /// Updates the topological ordering if required.
137 SUnit *CreateNewSUnit(SDNode *N) {
138 unsigned NumSUnits = SUnits.size();
139 SUnit *NewNode = NewSUnit(N);
140 // Update the topological ordering.
141 if (NewNode->NodeNum >= NumSUnits)
142 Topo.InitDAGTopologicalSorting();
146 /// CreateClone - Creates a new SUnit from an existing one.
147 /// Updates the topological ordering if required.
148 SUnit *CreateClone(SUnit *N) {
149 unsigned NumSUnits = SUnits.size();
150 SUnit *NewNode = Clone(N);
151 // Update the topological ordering.
152 if (NewNode->NodeNum >= NumSUnits)
153 Topo.InitDAGTopologicalSorting();
157 /// ForceUnitLatencies - Return true, since register-pressure-reducing
158 /// scheduling doesn't need actual latency information.
159 bool ForceUnitLatencies() const { return true; }
161 } // end anonymous namespace
164 /// Schedule - Schedule the DAG using list scheduling.
165 void ScheduleDAGRRList::Schedule() {
166 DOUT << "********** List Scheduling **********\n";
169 LiveRegDefs.resize(TRI->getNumRegs(), NULL);
170 LiveRegCycles.resize(TRI->getNumRegs(), 0);
172 // Build the scheduling graph.
175 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
176 SUnits[su].dumpAll(this));
177 Topo.InitDAGTopologicalSorting();
179 AvailableQueue->initNodes(SUnits);
181 // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
183 ListScheduleBottomUp();
185 ListScheduleTopDown();
187 AvailableQueue->releaseState();
190 //===----------------------------------------------------------------------===//
191 // Bottom-Up Scheduling
192 //===----------------------------------------------------------------------===//
194 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
195 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
196 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
197 SUnit *PredSU = PredEdge->getSUnit();
198 --PredSU->NumSuccsLeft;
201 if (PredSU->NumSuccsLeft < 0) {
202 cerr << "*** Scheduling failed! ***\n";
204 cerr << " has been released too many times!\n";
209 // If all the node's successors are scheduled, this node is ready
210 // to be scheduled. Ignore the special EntrySU node.
211 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
212 PredSU->isAvailable = true;
213 AvailableQueue->push(PredSU);
217 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU, unsigned CurCycle) {
218 // Bottom up: release predecessors
219 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
221 ReleasePred(SU, &*I);
222 if (I->isAssignedRegDep()) {
223 // This is a physical register dependency and it's impossible or
224 // expensive to copy the register. Make sure nothing that can
225 // clobber the register is scheduled between the predecessor and
227 if (!LiveRegDefs[I->getReg()]) {
229 LiveRegDefs[I->getReg()] = I->getSUnit();
230 LiveRegCycles[I->getReg()] = CurCycle;
236 /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
237 /// count of its predecessors. If a predecessor pending count is zero, add it to
238 /// the Available queue.
239 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
240 DOUT << "*** Scheduling [" << CurCycle << "]: ";
241 DEBUG(SU->dump(this));
243 assert(CurCycle >= SU->getHeight() && "Node scheduled below its height!");
244 SU->setHeightToAtLeast(CurCycle);
245 Sequence.push_back(SU);
247 ReleasePredecessors(SU, CurCycle);
249 // Release all the implicit physical register defs that are live.
250 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
252 if (I->isAssignedRegDep()) {
253 if (LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) {
254 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
255 assert(LiveRegDefs[I->getReg()] == SU &&
256 "Physical register dependency violated?");
258 LiveRegDefs[I->getReg()] = NULL;
259 LiveRegCycles[I->getReg()] = 0;
264 SU->isScheduled = true;
265 AvailableQueue->ScheduledNode(SU);
268 /// CapturePred - This does the opposite of ReleasePred. Since SU is being
269 /// unscheduled, incrcease the succ left count of its predecessors. Remove
270 /// them from AvailableQueue if necessary.
271 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) {
272 SUnit *PredSU = PredEdge->getSUnit();
273 if (PredSU->isAvailable) {
274 PredSU->isAvailable = false;
275 if (!PredSU->isPending)
276 AvailableQueue->remove(PredSU);
279 ++PredSU->NumSuccsLeft;
282 /// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and
283 /// its predecessor states to reflect the change.
284 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
285 DOUT << "*** Unscheduling [" << SU->getHeight() << "]: ";
286 DEBUG(SU->dump(this));
288 AvailableQueue->UnscheduledNode(SU);
290 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
293 if (I->isAssignedRegDep() && SU->getHeight() == LiveRegCycles[I->getReg()]) {
294 assert(NumLiveRegs > 0 && "NumLiveRegs is already zero!");
295 assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&
296 "Physical register dependency violated?");
298 LiveRegDefs[I->getReg()] = NULL;
299 LiveRegCycles[I->getReg()] = 0;
303 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
305 if (I->isAssignedRegDep()) {
306 if (!LiveRegDefs[I->getReg()]) {
307 LiveRegDefs[I->getReg()] = SU;
310 if (I->getSUnit()->getHeight() < LiveRegCycles[I->getReg()])
311 LiveRegCycles[I->getReg()] = I->getSUnit()->getHeight();
315 SU->setHeightDirty();
316 SU->isScheduled = false;
317 SU->isAvailable = true;
318 AvailableQueue->push(SU);
321 /// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in
322 /// BTCycle in order to schedule a specific node.
323 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, unsigned BtCycle,
324 unsigned &CurCycle) {
326 while (CurCycle > BtCycle) {
327 OldSU = Sequence.back();
329 if (SU->isSucc(OldSU))
330 // Don't try to remove SU from AvailableQueue.
331 SU->isAvailable = false;
332 UnscheduleNodeBottomUp(OldSU);
336 assert(!SU->isSucc(OldSU) && "Something is wrong!");
341 /// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
342 /// successors to the newly created node.
343 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
344 if (SU->getNode()->getFlaggedNode())
347 SDNode *N = SU->getNode();
352 bool TryUnfold = false;
353 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
354 MVT VT = N->getValueType(i);
357 else if (VT == MVT::Other)
360 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
361 const SDValue &Op = N->getOperand(i);
362 MVT VT = Op.getNode()->getValueType(Op.getResNo());
368 SmallVector<SDNode*, 2> NewNodes;
369 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
372 DOUT << "Unfolding SU # " << SU->NodeNum << "\n";
373 assert(NewNodes.size() == 2 && "Expected a load folding node!");
376 SDNode *LoadNode = NewNodes[0];
377 unsigned NumVals = N->getNumValues();
378 unsigned OldNumVals = SU->getNode()->getNumValues();
379 for (unsigned i = 0; i != NumVals; ++i)
380 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i));
381 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1),
382 SDValue(LoadNode, 1));
384 // LoadNode may already exist. This can happen when there is another
385 // load from the same location and producing the same type of value
386 // but it has different alignment or volatileness.
387 bool isNewLoad = true;
389 if (LoadNode->getNodeId() != -1) {
390 LoadSU = &SUnits[LoadNode->getNodeId()];
393 LoadSU = CreateNewSUnit(LoadNode);
394 LoadNode->setNodeId(LoadSU->NodeNum);
395 ComputeLatency(LoadSU);
398 SUnit *NewSU = CreateNewSUnit(N);
399 assert(N->getNodeId() == -1 && "Node already inserted!");
400 N->setNodeId(NewSU->NodeNum);
402 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
403 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
404 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
405 NewSU->isTwoAddress = true;
409 if (TID.isCommutable())
410 NewSU->isCommutable = true;
411 ComputeLatency(NewSU);
413 // Record all the edges to and from the old SU, by category.
414 SmallVector<SDep, 4> ChainPreds;
415 SmallVector<SDep, 4> ChainSuccs;
416 SmallVector<SDep, 4> LoadPreds;
417 SmallVector<SDep, 4> NodePreds;
418 SmallVector<SDep, 4> NodeSuccs;
419 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
422 ChainPreds.push_back(*I);
423 else if (I->getSUnit()->getNode() &&
424 I->getSUnit()->getNode()->isOperandOf(LoadNode))
425 LoadPreds.push_back(*I);
427 NodePreds.push_back(*I);
429 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
432 ChainSuccs.push_back(*I);
434 NodeSuccs.push_back(*I);
437 // Now assign edges to the newly-created nodes.
438 for (unsigned i = 0, e = ChainPreds.size(); i != e; ++i) {
439 const SDep &Pred = ChainPreds[i];
440 RemovePred(SU, Pred);
442 AddPred(LoadSU, Pred);
444 for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
445 const SDep &Pred = LoadPreds[i];
446 RemovePred(SU, Pred);
448 AddPred(LoadSU, Pred);
450 for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
451 const SDep &Pred = NodePreds[i];
452 RemovePred(SU, Pred);
453 AddPred(NewSU, Pred);
455 for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) {
456 SDep D = NodeSuccs[i];
457 SUnit *SuccDep = D.getSUnit();
459 RemovePred(SuccDep, D);
463 for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
464 SDep D = ChainSuccs[i];
465 SUnit *SuccDep = D.getSUnit();
467 RemovePred(SuccDep, D);
474 // Add a data dependency to reflect that NewSU reads the value defined
476 AddPred(NewSU, SDep(LoadSU, SDep::Data, LoadSU->Latency));
479 AvailableQueue->addNode(LoadSU);
480 AvailableQueue->addNode(NewSU);
484 if (NewSU->NumSuccsLeft == 0) {
485 NewSU->isAvailable = true;
491 DOUT << "Duplicating SU # " << SU->NodeNum << "\n";
492 NewSU = CreateClone(SU);
494 // New SUnit has the exact same predecessors.
495 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
497 if (!I->isArtificial())
500 // Only copy scheduled successors. Cut them from old node's successor
501 // list and move them over.
502 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
503 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
505 if (I->isArtificial())
507 SUnit *SuccSU = I->getSUnit();
508 if (SuccSU->isScheduled) {
513 DelDeps.push_back(std::make_pair(SuccSU, D));
516 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i)
517 RemovePred(DelDeps[i].first, DelDeps[i].second);
519 AvailableQueue->updateNode(SU);
520 AvailableQueue->addNode(NewSU);
526 /// InsertCopiesAndMoveSuccs - Insert register copies and move all
527 /// scheduled successors of the given SUnit to the last copy.
528 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
529 const TargetRegisterClass *DestRC,
530 const TargetRegisterClass *SrcRC,
531 SmallVector<SUnit*, 2> &Copies) {
532 SUnit *CopyFromSU = CreateNewSUnit(NULL);
533 CopyFromSU->CopySrcRC = SrcRC;
534 CopyFromSU->CopyDstRC = DestRC;
536 SUnit *CopyToSU = CreateNewSUnit(NULL);
537 CopyToSU->CopySrcRC = DestRC;
538 CopyToSU->CopyDstRC = SrcRC;
540 // Only copy scheduled successors. Cut them from old node's successor
541 // list and move them over.
542 SmallVector<std::pair<SUnit *, SDep>, 4> DelDeps;
543 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
545 if (I->isArtificial())
547 SUnit *SuccSU = I->getSUnit();
548 if (SuccSU->isScheduled) {
550 D.setSUnit(CopyToSU);
552 DelDeps.push_back(std::make_pair(SuccSU, *I));
555 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i)
556 RemovePred(DelDeps[i].first, DelDeps[i].second);
558 AddPred(CopyFromSU, SDep(SU, SDep::Data, SU->Latency, Reg));
559 AddPred(CopyToSU, SDep(CopyFromSU, SDep::Data, CopyFromSU->Latency, 0));
561 AvailableQueue->updateNode(SU);
562 AvailableQueue->addNode(CopyFromSU);
563 AvailableQueue->addNode(CopyToSU);
564 Copies.push_back(CopyFromSU);
565 Copies.push_back(CopyToSU);
570 /// getPhysicalRegisterVT - Returns the ValueType of the physical register
571 /// definition of the specified node.
572 /// FIXME: Move to SelectionDAG?
573 static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
574 const TargetInstrInfo *TII) {
575 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
576 assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
577 unsigned NumRes = TID.getNumDefs();
578 for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
583 return N->getValueType(NumRes);
586 /// CheckForLiveRegDef - Return true and update live register vector if the
587 /// specified register def of the specified SUnit clobbers any "live" registers.
588 static bool CheckForLiveRegDef(SUnit *SU, unsigned Reg,
589 std::vector<SUnit*> &LiveRegDefs,
590 SmallSet<unsigned, 4> &RegAdded,
591 SmallVector<unsigned, 4> &LRegs,
592 const TargetRegisterInfo *TRI) {
594 if (LiveRegDefs[Reg] && LiveRegDefs[Reg] != SU) {
595 if (RegAdded.insert(Reg)) {
596 LRegs.push_back(Reg);
600 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
601 if (LiveRegDefs[*Alias] && LiveRegDefs[*Alias] != SU) {
602 if (RegAdded.insert(*Alias)) {
603 LRegs.push_back(*Alias);
610 /// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
611 /// scheduling of the given node to satisfy live physical register dependencies.
612 /// If the specific node is the last one that's available to schedule, do
613 /// whatever is necessary (i.e. backtracking or cloning) to make it possible.
614 bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
615 SmallVector<unsigned, 4> &LRegs){
616 if (NumLiveRegs == 0)
619 SmallSet<unsigned, 4> RegAdded;
620 // If this node would clobber any "live" register, then it's not ready.
621 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
623 if (I->isAssignedRegDep())
624 CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs,
625 RegAdded, LRegs, TRI);
628 for (SDNode *Node = SU->getNode(); Node; Node = Node->getFlaggedNode()) {
629 if (Node->getOpcode() == ISD::INLINEASM) {
630 // Inline asm can clobber physical defs.
631 unsigned NumOps = Node->getNumOperands();
632 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
633 --NumOps; // Ignore the flag operand.
635 for (unsigned i = 2; i != NumOps;) {
637 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
638 unsigned NumVals = (Flags & 0xffff) >> 3;
640 ++i; // Skip the ID value.
641 if ((Flags & 7) == 2 || (Flags & 7) == 6) {
642 // Check for def of register or earlyclobber register.
643 for (; NumVals; --NumVals, ++i) {
644 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
645 if (TargetRegisterInfo::isPhysicalRegister(Reg))
646 CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
654 if (!Node->isMachineOpcode())
656 const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode());
657 if (!TID.ImplicitDefs)
659 for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg)
660 CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
662 return !LRegs.empty();
666 /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
668 void ScheduleDAGRRList::ListScheduleBottomUp() {
669 unsigned CurCycle = 0;
671 // Release any predecessors of the special Exit node.
672 ReleasePredecessors(&ExitSU, CurCycle);
674 // Add root to Available queue.
675 if (!SUnits.empty()) {
676 SUnit *RootSU = &SUnits[DAG->getRoot().getNode()->getNodeId()];
677 assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
678 RootSU->isAvailable = true;
679 AvailableQueue->push(RootSU);
682 // While Available queue is not empty, grab the node with the highest
683 // priority. If it is not ready put it back. Schedule the node.
684 SmallVector<SUnit*, 4> NotReady;
685 DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap;
686 Sequence.reserve(SUnits.size());
687 while (!AvailableQueue->empty()) {
688 bool Delayed = false;
690 SUnit *CurSU = AvailableQueue->pop();
692 SmallVector<unsigned, 4> LRegs;
693 if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
696 LRegsMap.insert(std::make_pair(CurSU, LRegs));
698 CurSU->isPending = true; // This SU is not in AvailableQueue right now.
699 NotReady.push_back(CurSU);
700 CurSU = AvailableQueue->pop();
703 // All candidates are delayed due to live physical reg dependencies.
704 // Try backtracking, code duplication, or inserting cross class copies
706 if (Delayed && !CurSU) {
707 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
708 SUnit *TrySU = NotReady[i];
709 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
711 // Try unscheduling up to the point where it's safe to schedule
713 unsigned LiveCycle = CurCycle;
714 for (unsigned j = 0, ee = LRegs.size(); j != ee; ++j) {
715 unsigned Reg = LRegs[j];
716 unsigned LCycle = LiveRegCycles[Reg];
717 LiveCycle = std::min(LiveCycle, LCycle);
719 SUnit *OldSU = Sequence[LiveCycle];
720 if (!WillCreateCycle(TrySU, OldSU)) {
721 BacktrackBottomUp(TrySU, LiveCycle, CurCycle);
722 // Force the current node to be scheduled before the node that
723 // requires the physical reg dep.
724 if (OldSU->isAvailable) {
725 OldSU->isAvailable = false;
726 AvailableQueue->remove(OldSU);
728 AddPred(TrySU, SDep(OldSU, SDep::Order, /*Latency=*/1,
729 /*Reg=*/0, /*isNormalMemory=*/false,
730 /*isMustAlias=*/false, /*isArtificial=*/true));
731 // If one or more successors has been unscheduled, then the current
732 // node is no longer avaialable. Schedule a successor that's now
733 // available instead.
734 if (!TrySU->isAvailable)
735 CurSU = AvailableQueue->pop();
738 TrySU->isPending = false;
739 NotReady.erase(NotReady.begin()+i);
746 // Can't backtrack. If it's too expensive to copy the value, then try
747 // duplicate the nodes that produces these "too expensive to copy"
748 // values to break the dependency. In case even that doesn't work,
749 // insert cross class copies.
750 // If it's not too expensive, i.e. cost != -1, issue copies.
751 SUnit *TrySU = NotReady[0];
752 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
753 assert(LRegs.size() == 1 && "Can't handle this yet!");
754 unsigned Reg = LRegs[0];
755 SUnit *LRDef = LiveRegDefs[Reg];
756 MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
757 const TargetRegisterClass *RC =
758 TRI->getPhysicalRegisterRegClass(Reg, VT);
759 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
761 // If cross copy register class is null, then it must be possible copy
762 // the value directly. Do not try duplicate the def.
765 NewDef = CopyAndMoveSuccessors(LRDef);
769 // Issue copies, these can be expensive cross register class copies.
770 SmallVector<SUnit*, 2> Copies;
771 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
772 DOUT << "Adding an edge from SU #" << TrySU->NodeNum
773 << " to SU #" << Copies.front()->NodeNum << "\n";
774 AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1,
775 /*Reg=*/0, /*isNormalMemory=*/false,
776 /*isMustAlias=*/false,
777 /*isArtificial=*/true));
778 NewDef = Copies.back();
781 DOUT << "Adding an edge from SU #" << NewDef->NodeNum
782 << " to SU #" << TrySU->NodeNum << "\n";
783 LiveRegDefs[Reg] = NewDef;
784 AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1,
785 /*Reg=*/0, /*isNormalMemory=*/false,
786 /*isMustAlias=*/false,
787 /*isArtificial=*/true));
788 TrySU->isAvailable = false;
792 assert(CurSU && "Unable to resolve live physical register dependencies!");
795 // Add the nodes that aren't ready back onto the available list.
796 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
797 NotReady[i]->isPending = false;
798 // May no longer be available due to backtracking.
799 if (NotReady[i]->isAvailable)
800 AvailableQueue->push(NotReady[i]);
805 ScheduleNodeBottomUp(CurSU, CurCycle);
809 // Reverse the order if it is bottom up.
810 std::reverse(Sequence.begin(), Sequence.end());
813 VerifySchedule(isBottomUp);
817 //===----------------------------------------------------------------------===//
818 // Top-Down Scheduling
819 //===----------------------------------------------------------------------===//
821 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
822 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
823 void ScheduleDAGRRList::ReleaseSucc(SUnit *SU, const SDep *SuccEdge) {
824 SUnit *SuccSU = SuccEdge->getSUnit();
825 --SuccSU->NumPredsLeft;
828 if (SuccSU->NumPredsLeft < 0) {
829 cerr << "*** Scheduling failed! ***\n";
831 cerr << " has been released too many times!\n";
836 // If all the node's predecessors are scheduled, this node is ready
837 // to be scheduled. Ignore the special ExitSU node.
838 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) {
839 SuccSU->isAvailable = true;
840 AvailableQueue->push(SuccSU);
844 void ScheduleDAGRRList::ReleaseSuccessors(SUnit *SU) {
845 // Top down: release successors
846 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
848 assert(!I->isAssignedRegDep() &&
849 "The list-tdrr scheduler doesn't yet support physreg dependencies!");
851 ReleaseSucc(SU, &*I);
855 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
856 /// count of its successors. If a successor pending count is zero, add it to
857 /// the Available queue.
858 void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
859 DOUT << "*** Scheduling [" << CurCycle << "]: ";
860 DEBUG(SU->dump(this));
862 assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
863 SU->setDepthToAtLeast(CurCycle);
864 Sequence.push_back(SU);
866 ReleaseSuccessors(SU);
867 SU->isScheduled = true;
868 AvailableQueue->ScheduledNode(SU);
871 /// ListScheduleTopDown - The main loop of list scheduling for top-down
873 void ScheduleDAGRRList::ListScheduleTopDown() {
874 unsigned CurCycle = 0;
876 // Release any successors of the special Entry node.
877 ReleaseSuccessors(&EntrySU);
879 // All leaves to Available queue.
880 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
881 // It is available if it has no predecessors.
882 if (SUnits[i].Preds.empty()) {
883 AvailableQueue->push(&SUnits[i]);
884 SUnits[i].isAvailable = true;
888 // While Available queue is not empty, grab the node with the highest
889 // priority. If it is not ready put it back. Schedule the node.
890 Sequence.reserve(SUnits.size());
891 while (!AvailableQueue->empty()) {
892 SUnit *CurSU = AvailableQueue->pop();
895 ScheduleNodeTopDown(CurSU, CurCycle);
900 VerifySchedule(isBottomUp);
905 //===----------------------------------------------------------------------===//
906 // RegReductionPriorityQueue Implementation
907 //===----------------------------------------------------------------------===//
909 // This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
910 // to reduce register pressure.
914 class RegReductionPriorityQueue;
916 /// Sorting functions for the Available queue.
917 struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
918 RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ;
919 bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {}
920 bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
922 bool operator()(const SUnit* left, const SUnit* right) const;
925 struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
926 RegReductionPriorityQueue<td_ls_rr_sort> *SPQ;
927 td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {}
928 td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
930 bool operator()(const SUnit* left, const SUnit* right) const;
932 } // end anonymous namespace
934 /// CalcNodeSethiUllmanNumber - Compute Sethi Ullman number.
935 /// Smaller number is the higher priority.
937 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) {
938 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
939 if (SethiUllmanNumber != 0)
940 return SethiUllmanNumber;
943 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
945 if (I->isCtrl()) continue; // ignore chain preds
946 SUnit *PredSU = I->getSUnit();
947 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers);
948 if (PredSethiUllman > SethiUllmanNumber) {
949 SethiUllmanNumber = PredSethiUllman;
951 } else if (PredSethiUllman == SethiUllmanNumber)
955 SethiUllmanNumber += Extra;
957 if (SethiUllmanNumber == 0)
958 SethiUllmanNumber = 1;
960 return SethiUllmanNumber;
965 class VISIBILITY_HIDDEN RegReductionPriorityQueue
966 : public SchedulingPriorityQueue {
967 PriorityQueue<SUnit*, std::vector<SUnit*>, SF> Queue;
968 unsigned currentQueueId;
971 // SUnits - The SUnits for the current graph.
972 std::vector<SUnit> *SUnits;
974 const TargetInstrInfo *TII;
975 const TargetRegisterInfo *TRI;
976 ScheduleDAGRRList *scheduleDAG;
978 // SethiUllmanNumbers - The SethiUllman number for each node.
979 std::vector<unsigned> SethiUllmanNumbers;
982 RegReductionPriorityQueue(const TargetInstrInfo *tii,
983 const TargetRegisterInfo *tri) :
984 Queue(SF(this)), currentQueueId(0),
985 TII(tii), TRI(tri), scheduleDAG(NULL) {}
987 void initNodes(std::vector<SUnit> &sunits) {
989 // Add pseudo dependency edges for two-address nodes.
990 AddPseudoTwoAddrDeps();
991 // Calculate node priorities.
992 CalculateSethiUllmanNumbers();
995 void addNode(const SUnit *SU) {
996 unsigned SUSize = SethiUllmanNumbers.size();
997 if (SUnits->size() > SUSize)
998 SethiUllmanNumbers.resize(SUSize*2, 0);
999 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1002 void updateNode(const SUnit *SU) {
1003 SethiUllmanNumbers[SU->NodeNum] = 0;
1004 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
1007 void releaseState() {
1009 SethiUllmanNumbers.clear();
1012 unsigned getNodePriority(const SUnit *SU) const {
1013 assert(SU->NodeNum < SethiUllmanNumbers.size());
1014 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
1015 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
1016 // CopyToReg should be close to its uses to facilitate coalescing and
1019 if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
1020 Opc == TargetInstrInfo::INSERT_SUBREG)
1021 // EXTRACT_SUBREG / INSERT_SUBREG should be close to its use to
1022 // facilitate coalescing.
1024 if (SU->NumSuccs == 0 && SU->NumPreds != 0)
1025 // If SU does not have a register use, i.e. it doesn't produce a value
1026 // that would be consumed (e.g. store), then it terminates a chain of
1027 // computation. Give it a large SethiUllman number so it will be
1028 // scheduled right before its predecessors that it doesn't lengthen
1029 // their live ranges.
1031 if (SU->NumPreds == 0 && SU->NumSuccs != 0)
1032 // If SU does not have a register def, schedule it close to its uses
1033 // because it does not lengthen any live ranges.
1035 return SethiUllmanNumbers[SU->NodeNum];
1038 unsigned size() const { return Queue.size(); }
1040 bool empty() const { return Queue.empty(); }
1042 void push(SUnit *U) {
1043 assert(!U->NodeQueueId && "Node in the queue already");
1044 U->NodeQueueId = ++currentQueueId;
1048 void push_all(const std::vector<SUnit *> &Nodes) {
1049 for (unsigned i = 0, e = Nodes.size(); i != e; ++i)
1054 if (empty()) return NULL;
1055 SUnit *V = Queue.top();
1061 void remove(SUnit *SU) {
1062 assert(!Queue.empty() && "Queue is empty!");
1063 assert(SU->NodeQueueId != 0 && "Not in queue!");
1064 Queue.erase_one(SU);
1065 SU->NodeQueueId = 0;
1068 void setScheduleDAG(ScheduleDAGRRList *scheduleDag) {
1069 scheduleDAG = scheduleDag;
1073 bool canClobber(const SUnit *SU, const SUnit *Op);
1074 void AddPseudoTwoAddrDeps();
1075 void CalculateSethiUllmanNumbers();
1078 typedef RegReductionPriorityQueue<bu_ls_rr_sort>
1079 BURegReductionPriorityQueue;
1081 typedef RegReductionPriorityQueue<td_ls_rr_sort>
1082 TDRegReductionPriorityQueue;
1085 /// closestSucc - Returns the scheduled cycle of the successor which is
1086 /// closest to the current cycle.
1087 static unsigned closestSucc(const SUnit *SU) {
1088 unsigned MaxHeight = 0;
1089 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1091 if (I->isCtrl()) continue; // ignore chain succs
1092 unsigned Height = I->getSUnit()->getHeight();
1093 // If there are bunch of CopyToRegs stacked up, they should be considered
1094 // to be at the same position.
1095 if (I->getSUnit()->getNode() &&
1096 I->getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)
1097 Height = closestSucc(I->getSUnit())+1;
1098 if (Height > MaxHeight)
1104 /// calcMaxScratches - Returns an cost estimate of the worse case requirement
1105 /// for scratch registers, i.e. number of data dependencies.
1106 static unsigned calcMaxScratches(const SUnit *SU) {
1107 unsigned Scratches = 0;
1108 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1110 if (I->isCtrl()) continue; // ignore chain preds
1117 bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
1118 unsigned LPriority = SPQ->getNodePriority(left);
1119 unsigned RPriority = SPQ->getNodePriority(right);
1120 if (LPriority != RPriority)
1121 return LPriority > RPriority;
1123 // Try schedule def + use closer when Sethi-Ullman numbers are the same.
1128 // and the following instructions are both ready.
1132 // Then schedule t2 = op first.
1139 // This creates more short live intervals.
1140 unsigned LDist = closestSucc(left);
1141 unsigned RDist = closestSucc(right);
1143 return LDist < RDist;
1145 // How many registers becomes live when the node is scheduled.
1146 unsigned LScratch = calcMaxScratches(left);
1147 unsigned RScratch = calcMaxScratches(right);
1148 if (LScratch != RScratch)
1149 return LScratch > RScratch;
1151 if (left->getHeight() != right->getHeight())
1152 return left->getHeight() > right->getHeight();
1154 if (left->getDepth() != right->getDepth())
1155 return left->getDepth() < right->getDepth();
1157 assert(left->NodeQueueId && right->NodeQueueId &&
1158 "NodeQueueId cannot be zero");
1159 return (left->NodeQueueId > right->NodeQueueId);
1164 RegReductionPriorityQueue<SF>::canClobber(const SUnit *SU, const SUnit *Op) {
1165 if (SU->isTwoAddress) {
1166 unsigned Opc = SU->getNode()->getMachineOpcode();
1167 const TargetInstrDesc &TID = TII->get(Opc);
1168 unsigned NumRes = TID.getNumDefs();
1169 unsigned NumOps = TID.getNumOperands() - NumRes;
1170 for (unsigned i = 0; i != NumOps; ++i) {
1171 if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
1172 SDNode *DU = SU->getNode()->getOperand(i).getNode();
1173 if (DU->getNodeId() != -1 &&
1174 Op->OrigNode == &(*SUnits)[DU->getNodeId()])
1183 /// hasCopyToRegUse - Return true if SU has a value successor that is a
1185 static bool hasCopyToRegUse(const SUnit *SU) {
1186 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1188 if (I->isCtrl()) continue;
1189 const SUnit *SuccSU = I->getSUnit();
1190 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg)
1196 /// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's
1197 /// physical register defs.
1198 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU,
1199 const TargetInstrInfo *TII,
1200 const TargetRegisterInfo *TRI) {
1201 SDNode *N = SuccSU->getNode();
1202 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
1203 const unsigned *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
1204 assert(ImpDefs && "Caller should check hasPhysRegDefs");
1205 for (const SDNode *SUNode = SU->getNode(); SUNode;
1206 SUNode = SUNode->getFlaggedNode()) {
1207 if (!SUNode->isMachineOpcode())
1209 const unsigned *SUImpDefs =
1210 TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
1213 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
1214 MVT VT = N->getValueType(i);
1215 if (VT == MVT::Flag || VT == MVT::Other)
1217 if (!N->hasAnyUseOfValue(i))
1219 unsigned Reg = ImpDefs[i - NumDefs];
1220 for (;*SUImpDefs; ++SUImpDefs) {
1221 unsigned SUReg = *SUImpDefs;
1222 if (TRI->regsOverlap(Reg, SUReg))
1230 /// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
1231 /// it as a def&use operand. Add a pseudo control edge from it to the other
1232 /// node (if it won't create a cycle) so the two-address one will be scheduled
1233 /// first (lower in the schedule). If both nodes are two-address, favor the
1234 /// one that has a CopyToReg use (more likely to be a loop induction update).
1235 /// If both are two-address, but one is commutable while the other is not
1236 /// commutable, favor the one that's not commutable.
1238 void RegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
1239 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
1240 SUnit *SU = &(*SUnits)[i];
1241 if (!SU->isTwoAddress)
1244 SDNode *Node = SU->getNode();
1245 if (!Node || !Node->isMachineOpcode() || SU->getNode()->getFlaggedNode())
1248 unsigned Opc = Node->getMachineOpcode();
1249 const TargetInstrDesc &TID = TII->get(Opc);
1250 unsigned NumRes = TID.getNumDefs();
1251 unsigned NumOps = TID.getNumOperands() - NumRes;
1252 for (unsigned j = 0; j != NumOps; ++j) {
1253 if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
1255 SDNode *DU = SU->getNode()->getOperand(j).getNode();
1256 if (DU->getNodeId() == -1)
1258 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
1259 if (!DUSU) continue;
1260 for (SUnit::const_succ_iterator I = DUSU->Succs.begin(),
1261 E = DUSU->Succs.end(); I != E; ++I) {
1262 if (I->isCtrl()) continue;
1263 SUnit *SuccSU = I->getSUnit();
1266 // Be conservative. Ignore if nodes aren't at roughly the same
1267 // depth and height.
1268 if (SuccSU->getHeight() < SU->getHeight() &&
1269 (SU->getHeight() - SuccSU->getHeight()) > 1)
1271 if (!SuccSU->getNode() || !SuccSU->getNode()->isMachineOpcode())
1273 // Don't constrain nodes with physical register defs if the
1274 // predecessor can clobber them.
1275 if (SuccSU->hasPhysRegDefs) {
1276 if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
1279 // Don't constrain extract_subreg / insert_subreg; these may be
1280 // coalesced away. We want them close to their uses.
1281 unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode();
1282 if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG ||
1283 SuccOpc == TargetInstrInfo::INSERT_SUBREG)
1285 if ((!canClobber(SuccSU, DUSU) ||
1286 (hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) ||
1287 (!SU->isCommutable && SuccSU->isCommutable)) &&
1288 !scheduleDAG->IsReachable(SuccSU, SU)) {
1289 DOUT << "Adding a pseudo-two-addr edge from SU # " << SU->NodeNum
1290 << " to SU #" << SuccSU->NodeNum << "\n";
1291 scheduleDAG->AddPred(SU, SDep(SuccSU, SDep::Order, /*Latency=*/0,
1292 /*Reg=*/0, /*isNormalMemory=*/false,
1293 /*isMustAlias=*/false,
1294 /*isArtificial=*/true));
1301 /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
1302 /// scheduling units.
1304 void RegReductionPriorityQueue<SF>::CalculateSethiUllmanNumbers() {
1305 SethiUllmanNumbers.assign(SUnits->size(), 0);
1307 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
1308 CalcNodeSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers);
1311 /// LimitedSumOfUnscheduledPredsOfSuccs - Compute the sum of the unscheduled
1312 /// predecessors of the successors of the SUnit SU. Stop when the provided
1313 /// limit is exceeded.
1314 static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU,
1317 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1319 const SUnit *SuccSU = I->getSUnit();
1320 for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(),
1321 EE = SuccSU->Preds.end(); II != EE; ++II) {
1322 SUnit *PredSU = II->getSUnit();
1323 if (!PredSU->isScheduled)
1333 bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
1334 unsigned LPriority = SPQ->getNodePriority(left);
1335 unsigned RPriority = SPQ->getNodePriority(right);
1336 bool LIsTarget = left->getNode() && left->getNode()->isMachineOpcode();
1337 bool RIsTarget = right->getNode() && right->getNode()->isMachineOpcode();
1338 bool LIsFloater = LIsTarget && left->NumPreds == 0;
1339 bool RIsFloater = RIsTarget && right->NumPreds == 0;
1340 unsigned LBonus = (LimitedSumOfUnscheduledPredsOfSuccs(left,1) == 1) ? 2 : 0;
1341 unsigned RBonus = (LimitedSumOfUnscheduledPredsOfSuccs(right,1) == 1) ? 2 : 0;
1343 if (left->NumSuccs == 0 && right->NumSuccs != 0)
1345 else if (left->NumSuccs != 0 && right->NumSuccs == 0)
1352 if (left->NumSuccs == 1)
1354 if (right->NumSuccs == 1)
1357 if (LPriority+LBonus != RPriority+RBonus)
1358 return LPriority+LBonus < RPriority+RBonus;
1360 if (left->getDepth() != right->getDepth())
1361 return left->getDepth() < right->getDepth();
1363 if (left->NumSuccsLeft != right->NumSuccsLeft)
1364 return left->NumSuccsLeft > right->NumSuccsLeft;
1366 assert(left->NodeQueueId && right->NodeQueueId &&
1367 "NodeQueueId cannot be zero");
1368 return (left->NodeQueueId > right->NodeQueueId);
1371 //===----------------------------------------------------------------------===//
1372 // Public Constructor Functions
1373 //===----------------------------------------------------------------------===//
1375 llvm::ScheduleDAGSDNodes *
1376 llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
1377 const TargetMachine &TM = IS->TM;
1378 const TargetInstrInfo *TII = TM.getInstrInfo();
1379 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
1381 BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI);
1383 ScheduleDAGRRList *SD =
1384 new ScheduleDAGRRList(*IS->MF, true, PQ);
1385 PQ->setScheduleDAG(SD);
1389 llvm::ScheduleDAGSDNodes *
1390 llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
1391 const TargetMachine &TM = IS->TM;
1392 const TargetInstrInfo *TII = TM.getInstrInfo();
1393 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
1395 TDRegReductionPriorityQueue *PQ = new TDRegReductionPriorityQueue(TII, TRI);
1397 ScheduleDAGRRList *SD =
1398 new ScheduleDAGRRList(*IS->MF, false, PQ);
1399 PQ->setScheduleDAG(SD);