1 //===----- ScheduleDAGList.cpp - Reg pressure reduction list scheduler ----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements bottom-up and top-down register pressure reduction list
11 // schedulers, using standard algorithms. The basic approach uses a priority
12 // queue of available nodes to schedule. One at a time, nodes are taken from
13 // the priority queue (thus in priority order), checked for legality to
14 // schedule, and emitted if legal.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "sched"
19 #include "llvm/CodeGen/ScheduleDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Target/MRegisterInfo.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Support/CommandLine.h"
33 cl::opt<bool> SchedCommuteNodes("sched-commute-nodes", cl::Hidden);
37 //===----------------------------------------------------------------------===//
38 /// ScheduleDAGRRList - The actual register reduction list scheduler
39 /// implementation. This supports both top-down and bottom-up scheduling.
42 class ScheduleDAGRRList : public ScheduleDAG {
44 /// isBottomUp - This is true if the scheduling problem is bottom-up, false if
48 /// AvailableQueue - The priority queue to use for the available SUnits.
50 SchedulingPriorityQueue *AvailableQueue;
53 ScheduleDAGRRList(SelectionDAG &dag, MachineBasicBlock *bb,
54 const TargetMachine &tm, bool isbottomup,
55 SchedulingPriorityQueue *availqueue)
56 : ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup),
57 AvailableQueue(availqueue) {
60 ~ScheduleDAGRRList() {
61 delete AvailableQueue;
67 void ReleasePred(SUnit *PredSU, bool isChain, unsigned CurCycle);
68 void ReleaseSucc(SUnit *SuccSU, bool isChain, unsigned CurCycle);
69 void ScheduleNodeBottomUp(SUnit *SU, unsigned& CurCycle);
70 void ScheduleNodeTopDown(SUnit *SU, unsigned& CurCycle);
71 void ListScheduleTopDown();
72 void ListScheduleBottomUp();
73 void CommuteNodesToReducePressure();
75 } // end anonymous namespace
78 /// Schedule - Schedule the DAG using list scheduling.
79 void ScheduleDAGRRList::Schedule() {
80 DEBUG(std::cerr << "********** List Scheduling **********\n");
82 // Build scheduling units.
87 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
88 SUnits[su].dumpAll(&DAG));
90 AvailableQueue->initNodes(SUnits);
92 // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
94 ListScheduleBottomUp();
96 ListScheduleTopDown();
98 AvailableQueue->releaseState();
100 if (SchedCommuteNodes)
101 CommuteNodesToReducePressure();
103 DEBUG(std::cerr << "*** Final schedule ***\n");
104 DEBUG(dumpSchedule());
105 DEBUG(std::cerr << "\n");
107 // Emit in scheduled order
111 /// CommuteNodesToReducePressure - Is a node is two-address and commutable, and
112 /// it is not the last use of its first operand, add it to the CommuteSet if
113 /// possible. It will be commuted when it is translated to a MI.
114 void ScheduleDAGRRList::CommuteNodesToReducePressure() {
115 std::set<SUnit *> OperandSeen;
116 for (unsigned i = Sequence.size()-1; i != 0; --i) { // Ignore first node.
117 SUnit *SU = Sequence[i];
119 if (SU->isTwoAddress && SU->isCommutable) {
120 SDNode *OpN = SU->Node->getOperand(0).Val;
121 SUnit *OpSU = SUnitMap[OpN];
122 if (OpSU && OperandSeen.count(OpSU) == 1) {
123 // Ok, so SU is not the last use of OpSU, but SU is two-address so
124 // it will clobber OpSU. Try to commute it if possible.
125 bool DoCommute = true;
126 for (unsigned j = 1, e = SU->Node->getNumOperands(); j != e; ++j) {
127 OpN = SU->Node->getOperand(j).Val;
128 OpSU = SUnitMap[OpN];
129 if (OpSU && OperandSeen.count(OpSU) == 1) {
135 CommuteSet.insert(SU->Node);
139 for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Preds.begin(),
140 E = SU->Preds.end(); I != E; ++I) {
142 OperandSeen.insert(I->first);
147 //===----------------------------------------------------------------------===//
148 // Bottom-Up Scheduling
149 //===----------------------------------------------------------------------===//
151 static const TargetRegisterClass *getRegClass(SUnit *SU,
152 const TargetInstrInfo *TII,
153 const MRegisterInfo *MRI,
155 if (SU->Node->isTargetOpcode()) {
156 unsigned Opc = SU->Node->getTargetOpcode();
157 const TargetInstrDescriptor &II = TII->get(Opc);
158 return II.OpInfo->RegClass;
160 assert(SU->Node->getOpcode() == ISD::CopyFromReg);
161 unsigned SrcReg = cast<RegisterSDNode>(SU->Node->getOperand(1))->getReg();
162 if (MRegisterInfo::isVirtualRegister(SrcReg))
163 return RegMap->getRegClass(SrcReg);
165 for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
166 E = MRI->regclass_end(); I != E; ++I)
167 if ((*I)->hasType(SU->Node->getValueType(0)) &&
168 (*I)->contains(SrcReg))
170 assert(false && "Couldn't find register class for reg copy!");
176 static unsigned getNumResults(SUnit *SU) {
177 unsigned NumResults = 0;
178 for (unsigned i = 0, e = SU->Node->getNumValues(); i != e; ++i) {
179 MVT::ValueType VT = SU->Node->getValueType(i);
180 if (VT != MVT::Other && VT != MVT::Flag)
186 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
187 /// the Available queue is the count reaches zero. Also update its cycle bound.
188 void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
190 // FIXME: the distance between two nodes is not always == the predecessor's
191 // latency. For example, the reader can very well read the register written
192 // by the predecessor later than the issue cycle. It also depends on the
193 // interrupt model (drain vs. freeze).
194 PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency);
197 PredSU->NumSuccsLeft--;
199 PredSU->NumChainSuccsLeft--;
202 if (PredSU->NumSuccsLeft < 0 || PredSU->NumChainSuccsLeft < 0) {
203 std::cerr << "*** List scheduling failed! ***\n";
205 std::cerr << " has been released too many times!\n";
210 if ((PredSU->NumSuccsLeft + PredSU->NumChainSuccsLeft) == 0) {
211 // EntryToken has to go last! Special case it here.
212 if (PredSU->Node->getOpcode() != ISD::EntryToken) {
213 PredSU->isAvailable = true;
214 AvailableQueue->push(PredSU);
219 /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
220 /// count of its predecessors. If a predecessor pending count is zero, add it to
221 /// the Available queue.
222 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned& CurCycle) {
223 DEBUG(std::cerr << "*** Scheduling [" << CurCycle << "]: ");
224 DEBUG(SU->dump(&DAG));
225 SU->Cycle = CurCycle;
227 AvailableQueue->ScheduledNode(SU);
228 Sequence.push_back(SU);
230 // Bottom up: release predecessors
231 for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Preds.begin(),
232 E = SU->Preds.end(); I != E; ++I)
233 ReleasePred(I->first, I->second, CurCycle);
234 SU->isScheduled = true;
238 /// isReady - True if node's lower cycle bound is less or equal to the current
239 /// scheduling cycle. Always true if all nodes have uniform latency 1.
240 static inline bool isReady(SUnit *SU, unsigned CurCycle) {
241 return SU->CycleBound <= CurCycle;
244 /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
246 void ScheduleDAGRRList::ListScheduleBottomUp() {
247 unsigned CurCycle = 0;
248 // Add root to Available queue.
249 AvailableQueue->push(SUnitMap[DAG.getRoot().Val]);
251 // While Available queue is not empty, grab the node with the highest
252 // priority. If it is not ready put it back. Schedule the node.
253 std::vector<SUnit*> NotReady;
254 SUnit *CurNode = NULL;
255 while (!AvailableQueue->empty()) {
256 SUnit *CurNode = AvailableQueue->pop();
257 while (!isReady(CurNode, CurCycle)) {
258 NotReady.push_back(CurNode);
259 CurNode = AvailableQueue->pop();
262 // Add the nodes that aren't ready back onto the available list.
263 AvailableQueue->push_all(NotReady);
266 ScheduleNodeBottomUp(CurNode, CurCycle);
269 // Add entry node last
270 if (DAG.getEntryNode().Val != DAG.getRoot().Val) {
271 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
272 Sequence.push_back(Entry);
275 // Reverse the order if it is bottom up.
276 std::reverse(Sequence.begin(), Sequence.end());
280 // Verify that all SUnits were scheduled.
281 bool AnyNotSched = false;
282 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
283 if (SUnits[i].NumSuccsLeft != 0 || SUnits[i].NumChainSuccsLeft != 0) {
285 std::cerr << "*** List scheduling failed! ***\n";
286 SUnits[i].dump(&DAG);
287 std::cerr << "has not been scheduled!\n";
291 assert(!AnyNotSched);
295 //===----------------------------------------------------------------------===//
296 // Top-Down Scheduling
297 //===----------------------------------------------------------------------===//
299 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
300 /// the PendingQueue if the count reaches zero.
301 void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain,
303 // FIXME: the distance between two nodes is not always == the predecessor's
304 // latency. For example, the reader can very well read the register written
305 // by the predecessor later than the issue cycle. It also depends on the
306 // interrupt model (drain vs. freeze).
307 SuccSU->CycleBound = std::max(SuccSU->CycleBound, CurCycle + SuccSU->Latency);
310 SuccSU->NumPredsLeft--;
312 SuccSU->NumChainPredsLeft--;
315 if (SuccSU->NumPredsLeft < 0 || SuccSU->NumChainPredsLeft < 0) {
316 std::cerr << "*** List scheduling failed! ***\n";
318 std::cerr << " has been released too many times!\n";
323 if ((SuccSU->NumPredsLeft + SuccSU->NumChainPredsLeft) == 0) {
324 SuccSU->isAvailable = true;
325 AvailableQueue->push(SuccSU);
330 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
331 /// count of its successors. If a successor pending count is zero, add it to
332 /// the Available queue.
333 void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned& CurCycle) {
334 DEBUG(std::cerr << "*** Scheduling [" << CurCycle << "]: ");
335 DEBUG(SU->dump(&DAG));
336 SU->Cycle = CurCycle;
338 AvailableQueue->ScheduledNode(SU);
339 Sequence.push_back(SU);
341 // Top down: release successors
342 for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Succs.begin(),
343 E = SU->Succs.end(); I != E; ++I)
344 ReleaseSucc(I->first, I->second, CurCycle);
345 SU->isScheduled = true;
349 void ScheduleDAGRRList::ListScheduleTopDown() {
350 unsigned CurCycle = 0;
351 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
353 // All leaves to Available queue.
354 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
355 // It is available if it has no predecessors.
356 if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
357 AvailableQueue->push(&SUnits[i]);
358 SUnits[i].isAvailable = true;
362 // Emit the entry node first.
363 ScheduleNodeTopDown(Entry, CurCycle);
365 // While Available queue is not empty, grab the node with the highest
366 // priority. If it is not ready put it back. Schedule the node.
367 std::vector<SUnit*> NotReady;
368 SUnit *CurNode = NULL;
369 while (!AvailableQueue->empty()) {
370 SUnit *CurNode = AvailableQueue->pop();
371 while (!isReady(CurNode, CurCycle)) {
372 NotReady.push_back(CurNode);
373 CurNode = AvailableQueue->pop();
376 // Add the nodes that aren't ready back onto the available list.
377 AvailableQueue->push_all(NotReady);
380 ScheduleNodeTopDown(CurNode, CurCycle);
385 // Verify that all SUnits were scheduled.
386 bool AnyNotSched = false;
387 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
388 if (!SUnits[i].isScheduled) {
390 std::cerr << "*** List scheduling failed! ***\n";
391 SUnits[i].dump(&DAG);
392 std::cerr << "has not been scheduled!\n";
396 assert(!AnyNotSched);
402 //===----------------------------------------------------------------------===//
403 // RegReductionPriorityQueue Implementation
404 //===----------------------------------------------------------------------===//
406 // This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
407 // to reduce register pressure.
411 class RegReductionPriorityQueue;
413 /// Sorting functions for the Available queue.
414 struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
415 RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ;
416 bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {}
417 bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
419 bool operator()(const SUnit* left, const SUnit* right) const;
422 struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
423 RegReductionPriorityQueue<td_ls_rr_sort> *SPQ;
424 td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {}
425 td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
427 bool operator()(const SUnit* left, const SUnit* right) const;
429 } // end anonymous namespace
433 class RegReductionPriorityQueue : public SchedulingPriorityQueue {
434 std::priority_queue<SUnit*, std::vector<SUnit*>, SF> Queue;
437 RegReductionPriorityQueue() :
440 virtual void initNodes(const std::vector<SUnit> &sunits) {}
441 virtual void releaseState() {}
443 virtual int getSethiUllmanNumber(unsigned NodeNum) const {
447 bool empty() const { return Queue.empty(); }
449 void push(SUnit *U) {
452 void push_all(const std::vector<SUnit *> &Nodes) {
453 for (unsigned i = 0, e = Nodes.size(); i != e; ++i)
454 Queue.push(Nodes[i]);
458 SUnit *V = Queue.top();
465 class BURegReductionPriorityQueue : public RegReductionPriorityQueue<SF> {
466 // SUnits - The SUnits for the current graph.
467 const std::vector<SUnit> *SUnits;
469 // SethiUllmanNumbers - The SethiUllman number for each node.
470 std::vector<int> SethiUllmanNumbers;
473 BURegReductionPriorityQueue() {}
475 void initNodes(const std::vector<SUnit> &sunits) {
477 // Add pseudo dependency edges for two-address nodes.
478 AddPseudoTwoAddrDeps();
479 // Calculate node priorities.
480 CalculatePriorities();
483 void releaseState() {
485 SethiUllmanNumbers.clear();
488 int getSethiUllmanNumber(unsigned NodeNum) const {
489 assert(NodeNum < SethiUllmanNumbers.size());
490 return SethiUllmanNumbers[NodeNum];
494 void AddPseudoTwoAddrDeps();
495 void CalculatePriorities();
496 int CalcNodePriority(const SUnit *SU);
501 class TDRegReductionPriorityQueue : public RegReductionPriorityQueue<SF> {
502 // SUnits - The SUnits for the current graph.
503 const std::vector<SUnit> *SUnits;
505 // SethiUllmanNumbers - The SethiUllman number for each node.
506 std::vector<int> SethiUllmanNumbers;
509 TDRegReductionPriorityQueue() {}
511 void initNodes(const std::vector<SUnit> &sunits) {
513 // Calculate node priorities.
514 CalculatePriorities();
517 void releaseState() {
519 SethiUllmanNumbers.clear();
522 int getSethiUllmanNumber(unsigned NodeNum) const {
523 assert(NodeNum < SethiUllmanNumbers.size());
524 return SethiUllmanNumbers[NodeNum];
528 void CalculatePriorities();
529 int CalcNodePriority(const SUnit *SU);
534 bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
535 unsigned LeftNum = left->NodeNum;
536 unsigned RightNum = right->NodeNum;
537 bool LIsTarget = left->Node->isTargetOpcode();
538 bool RIsTarget = right->Node->isTargetOpcode();
539 int LPriority = SPQ->getSethiUllmanNumber(LeftNum);
540 int RPriority = SPQ->getSethiUllmanNumber(RightNum);
541 bool LIsFloater = LIsTarget && (LPriority == 1 || LPriority == 0);
542 bool RIsFloater = RIsTarget && (RPriority == 1 || RPriority == 0);
546 // Schedule floaters (e.g. load from some constant address) and those nodes
547 // with a single predecessor each first. They maintain / reduce register
554 if (LPriority+LBonus < RPriority+RBonus)
556 else if (LPriority+LBonus == RPriority+RBonus)
557 if (left->NumPredsLeft > right->NumPredsLeft)
559 else if (left->NumPredsLeft+LBonus == right->NumPredsLeft+RBonus)
560 if (left->CycleBound > right->CycleBound)
565 static inline bool isCopyFromLiveIn(const SUnit *SU) {
566 SDNode *N = SU->Node;
567 return N->getOpcode() == ISD::CopyFromReg &&
568 N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag;
571 // FIXME: This is probably too slow!
572 static void isReachable(SUnit *SU, SUnit *TargetSU,
573 std::set<SUnit *> &Visited, bool &Reached) {
575 if (SU == TargetSU) {
579 if (!Visited.insert(SU).second) return;
581 for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Preds.begin(),
582 E = SU->Preds.end(); I != E; ++I)
583 isReachable(I->first, TargetSU, Visited, Reached);
586 static bool isReachable(SUnit *SU, SUnit *TargetSU) {
587 std::set<SUnit *> Visited;
588 bool Reached = false;
589 isReachable(SU, TargetSU, Visited, Reached);
593 static SUnit *getDefUsePredecessor(SUnit *SU) {
594 SDNode *DU = SU->Node->getOperand(0).Val;
595 for (std::set<std::pair<SUnit*, bool> >::iterator
596 I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) {
597 if (I->second) continue; // ignore chain preds
598 SUnit *PredSU = I->first;
599 if (PredSU->Node == DU)
607 static bool canClobber(SUnit *SU, SUnit *Op) {
608 if (SU->isTwoAddress)
609 return Op == getDefUsePredecessor(SU);
613 /// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
614 /// it as a def&use operand. Add a pseudo control edge from it to the other
615 /// node (if it won't create a cycle) so the two-address one will be scheduled
616 /// first (lower in the schedule).
618 void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
619 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
620 SUnit *SU = (SUnit *)&((*SUnits)[i]);
621 SDNode *Node = SU->Node;
622 if (!Node->isTargetOpcode())
625 if (SU->isTwoAddress) {
626 SUnit *DUSU = getDefUsePredecessor(SU);
629 for (std::set<std::pair<SUnit*, bool> >::iterator I = DUSU->Succs.begin(),
630 E = DUSU->Succs.end(); I != E; ++I) {
631 if (I->second) continue;
632 SUnit *SuccSU = I->first;
634 (!canClobber(SuccSU, DUSU) ||
635 (SchedCommuteNodes && !SU->isCommutable && SuccSU->isCommutable))){
636 if (SuccSU->Depth <= SU->Depth+2 && !isReachable(SuccSU, SU)) {
637 DEBUG(std::cerr << "Adding an edge from SU # " << SU->NodeNum
638 << " to SU #" << SuccSU->NodeNum << "\n");
639 if (SU->Preds.insert(std::make_pair(SuccSU, true)).second)
640 SU->NumChainPredsLeft++;
641 if (SuccSU->Succs.insert(std::make_pair(SU, true)).second)
642 SuccSU->NumChainSuccsLeft++;
650 /// CalcNodePriority - Priority is the Sethi Ullman number.
651 /// Smaller number is the higher priority.
653 int BURegReductionPriorityQueue<SF>::CalcNodePriority(const SUnit *SU) {
654 int &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
655 if (SethiUllmanNumber != 0)
656 return SethiUllmanNumber;
658 unsigned Opc = SU->Node->getOpcode();
659 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
660 SethiUllmanNumber = INT_MAX - 10;
661 else if (SU->NumSuccsLeft == 0)
662 // If SU does not have a use, i.e. it doesn't produce a value that would
663 // be consumed (e.g. store), then it terminates a chain of computation.
664 // Give it a small SethiUllman number so it will be scheduled right before its
665 // predecessors that it doesn't lengthen their live ranges.
666 SethiUllmanNumber = INT_MIN + 10;
667 else if (SU->NumPredsLeft == 0 &&
668 (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
669 SethiUllmanNumber = 1;
672 for (std::set<std::pair<SUnit*, bool> >::const_iterator
673 I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) {
674 if (I->second) continue; // ignore chain preds
675 SUnit *PredSU = I->first;
676 int PredSethiUllman = CalcNodePriority(PredSU);
677 if (PredSethiUllman > SethiUllmanNumber) {
678 SethiUllmanNumber = PredSethiUllman;
680 } else if (PredSethiUllman == SethiUllmanNumber && !I->second)
684 SethiUllmanNumber += Extra;
687 return SethiUllmanNumber;
690 /// CalculatePriorities - Calculate priorities of all scheduling units.
692 void BURegReductionPriorityQueue<SF>::CalculatePriorities() {
693 SethiUllmanNumbers.assign(SUnits->size(), 0);
695 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
696 CalcNodePriority(&(*SUnits)[i]);
699 static unsigned SumOfUnscheduledPredsOfSuccs(const SUnit *SU) {
701 for (std::set<std::pair<SUnit*, bool> >::const_iterator
702 I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) {
703 SUnit *SuccSU = I->first;
704 for (std::set<std::pair<SUnit*, bool> >::const_iterator
705 II = SuccSU->Preds.begin(), EE = SuccSU->Preds.end(); II != EE; ++II) {
706 SUnit *PredSU = II->first;
707 if (!PredSU->isScheduled)
717 bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
718 unsigned LeftNum = left->NodeNum;
719 unsigned RightNum = right->NodeNum;
720 int LPriority = SPQ->getSethiUllmanNumber(LeftNum);
721 int RPriority = SPQ->getSethiUllmanNumber(RightNum);
722 bool LIsTarget = left->Node->isTargetOpcode();
723 bool RIsTarget = right->Node->isTargetOpcode();
724 bool LIsFloater = LIsTarget && left->NumPreds == 0;
725 bool RIsFloater = RIsTarget && right->NumPreds == 0;
726 unsigned LBonus = (SumOfUnscheduledPredsOfSuccs(left) == 1) ? 2 : 0;
727 unsigned RBonus = (SumOfUnscheduledPredsOfSuccs(right) == 1) ? 2 : 0;
729 if (left->NumSuccs == 0 && right->NumSuccs != 0)
731 else if (left->NumSuccs != 0 && right->NumSuccs == 0)
734 // Special tie breaker: if two nodes share a operand, the one that use it
735 // as a def&use operand is preferred.
736 if (LIsTarget && RIsTarget) {
737 if (left->isTwoAddress && !right->isTwoAddress) {
738 SDNode *DUNode = left->Node->getOperand(0).Val;
739 if (DUNode->isOperand(right->Node))
742 if (!left->isTwoAddress && right->isTwoAddress) {
743 SDNode *DUNode = right->Node->getOperand(0).Val;
744 if (DUNode->isOperand(left->Node))
752 if (left->NumSuccs == 1)
754 if (right->NumSuccs == 1)
757 if (LPriority+LBonus < RPriority+RBonus)
759 else if (LPriority == RPriority)
760 if (left->Depth < right->Depth)
762 else if (left->Depth == right->Depth)
763 if (left->NumSuccsLeft > right->NumSuccsLeft)
765 else if (left->NumSuccsLeft == right->NumSuccsLeft)
766 if (left->CycleBound > right->CycleBound)
771 /// CalcNodePriority - Priority is the Sethi Ullman number.
772 /// Smaller number is the higher priority.
774 int TDRegReductionPriorityQueue<SF>::CalcNodePriority(const SUnit *SU) {
775 int &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
776 if (SethiUllmanNumber != 0)
777 return SethiUllmanNumber;
779 unsigned Opc = SU->Node->getOpcode();
780 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
781 SethiUllmanNumber = INT_MAX - 10;
782 else if (SU->NumSuccsLeft == 0)
783 // If SU does not have a use, i.e. it doesn't produce a value that would
784 // be consumed (e.g. store), then it terminates a chain of computation.
785 // Give it a small SethiUllman number so it will be scheduled right before its
786 // predecessors that it doesn't lengthen their live ranges.
787 SethiUllmanNumber = INT_MIN + 10;
788 else if (SU->NumPredsLeft == 0 &&
789 (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
790 SethiUllmanNumber = 1;
793 for (std::set<std::pair<SUnit*, bool> >::const_iterator
794 I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) {
795 if (I->second) continue; // ignore chain preds
796 SUnit *PredSU = I->first;
797 int PredSethiUllman = CalcNodePriority(PredSU);
798 if (PredSethiUllman > SethiUllmanNumber) {
799 SethiUllmanNumber = PredSethiUllman;
801 } else if (PredSethiUllman == SethiUllmanNumber && !I->second)
805 SethiUllmanNumber += Extra;
808 return SethiUllmanNumber;
811 /// CalculatePriorities - Calculate priorities of all scheduling units.
813 void TDRegReductionPriorityQueue<SF>::CalculatePriorities() {
814 SethiUllmanNumbers.assign(SUnits->size(), 0);
816 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
817 CalcNodePriority(&(*SUnits)[i]);
820 //===----------------------------------------------------------------------===//
821 // Public Constructor Functions
822 //===----------------------------------------------------------------------===//
824 llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG &DAG,
825 MachineBasicBlock *BB) {
826 return new ScheduleDAGRRList(DAG, BB, DAG.getTarget(), true,
827 new BURegReductionPriorityQueue<bu_ls_rr_sort>());
830 llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAG &DAG,
831 MachineBasicBlock *BB) {
832 return new ScheduleDAGRRList(DAG, BB, DAG.getTarget(), false,
833 new TDRegReductionPriorityQueue<td_ls_rr_sort>());