1 //===----- ScheduleDAGList.cpp - Reg pressure reduction list scheduler ----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements bottom-up and top-down register pressure reduction list
11 // schedulers, using standard algorithms. The basic approach uses a priority
12 // queue of available nodes to schedule. One at a time, nodes are taken from
13 // the priority queue (thus in priority order), checked for legality to
14 // schedule, and emitted if legal.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "sched"
19 #include "llvm/CodeGen/ScheduleDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Target/MRegisterInfo.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Support/CommandLine.h"
33 cl::opt<bool> SchedLowerDefNUse("sched-lower-defnuse", cl::Hidden);
37 //===----------------------------------------------------------------------===//
38 /// ScheduleDAGRRList - The actual register reduction list scheduler
39 /// implementation. This supports both top-down and bottom-up scheduling.
42 class ScheduleDAGRRList : public ScheduleDAG {
44 /// isBottomUp - This is true if the scheduling problem is bottom-up, false if
48 /// AvailableQueue - The priority queue to use for the available SUnits.
50 SchedulingPriorityQueue *AvailableQueue;
53 ScheduleDAGRRList(SelectionDAG &dag, MachineBasicBlock *bb,
54 const TargetMachine &tm, bool isbottomup,
55 SchedulingPriorityQueue *availqueue)
56 : ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup),
57 AvailableQueue(availqueue) {
60 ~ScheduleDAGRRList() {
61 delete AvailableQueue;
67 void ReleasePred(SUnit *PredSU, bool isChain, unsigned CurCycle);
68 void ReleaseSucc(SUnit *SuccSU, bool isChain, unsigned CurCycle);
69 void ScheduleNodeBottomUp(SUnit *SU, unsigned& CurCycle);
70 void ScheduleNodeTopDown(SUnit *SU, unsigned& CurCycle);
71 void ListScheduleTopDown();
72 void ListScheduleBottomUp();
74 } // end anonymous namespace
77 /// Schedule - Schedule the DAG using list scheduling.
78 void ScheduleDAGRRList::Schedule() {
79 DEBUG(std::cerr << "********** List Scheduling **********\n");
81 // Build scheduling units.
86 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
87 SUnits[su].dumpAll(&DAG));
89 AvailableQueue->initNodes(SUnits);
91 // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
93 ListScheduleBottomUp();
95 ListScheduleTopDown();
97 AvailableQueue->releaseState();
99 DEBUG(std::cerr << "*** Final schedule ***\n");
100 DEBUG(dumpSchedule());
101 DEBUG(std::cerr << "\n");
103 // Emit in scheduled order
108 //===----------------------------------------------------------------------===//
109 // Bottom-Up Scheduling
110 //===----------------------------------------------------------------------===//
112 static const TargetRegisterClass *getRegClass(SUnit *SU,
113 const TargetInstrInfo *TII,
114 const MRegisterInfo *MRI,
116 if (SU->Node->isTargetOpcode()) {
117 unsigned Opc = SU->Node->getTargetOpcode();
118 const TargetInstrDescriptor &II = TII->get(Opc);
119 return II.OpInfo->RegClass;
121 assert(SU->Node->getOpcode() == ISD::CopyFromReg);
122 unsigned SrcReg = cast<RegisterSDNode>(SU->Node->getOperand(1))->getReg();
123 if (MRegisterInfo::isVirtualRegister(SrcReg))
124 return RegMap->getRegClass(SrcReg);
126 for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
127 E = MRI->regclass_end(); I != E; ++I)
128 if ((*I)->hasType(SU->Node->getValueType(0)) &&
129 (*I)->contains(SrcReg))
131 assert(false && "Couldn't find register class for reg copy!");
137 static unsigned getNumResults(SUnit *SU) {
138 unsigned NumResults = 0;
139 for (unsigned i = 0, e = SU->Node->getNumValues(); i != e; ++i) {
140 MVT::ValueType VT = SU->Node->getValueType(i);
141 if (VT != MVT::Other && VT != MVT::Flag)
147 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
148 /// the Available queue is the count reaches zero. Also update its cycle bound.
149 void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
151 // FIXME: the distance between two nodes is not always == the predecessor's
152 // latency. For example, the reader can very well read the register written
153 // by the predecessor later than the issue cycle. It also depends on the
154 // interrupt model (drain vs. freeze).
155 PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency);
158 PredSU->NumSuccsLeft--;
160 PredSU->NumChainSuccsLeft--;
163 if (PredSU->NumSuccsLeft < 0 || PredSU->NumChainSuccsLeft < 0) {
164 std::cerr << "*** List scheduling failed! ***\n";
166 std::cerr << " has been released too many times!\n";
171 if ((PredSU->NumSuccsLeft + PredSU->NumChainSuccsLeft) == 0) {
172 // EntryToken has to go last! Special case it here.
173 if (PredSU->Node->getOpcode() != ISD::EntryToken) {
174 PredSU->isAvailable = true;
175 AvailableQueue->push(PredSU);
180 /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
181 /// count of its predecessors. If a predecessor pending count is zero, add it to
182 /// the Available queue.
183 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned& CurCycle) {
184 DEBUG(std::cerr << "*** Scheduling [" << CurCycle << "]: ");
185 DEBUG(SU->dump(&DAG));
186 SU->Cycle = CurCycle;
188 AvailableQueue->ScheduledNode(SU);
189 Sequence.push_back(SU);
191 // Bottom up: release predecessors
192 for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Preds.begin(),
193 E = SU->Preds.end(); I != E; ++I)
194 ReleasePred(I->first, I->second, CurCycle);
195 SU->isScheduled = true;
199 /// isReady - True if node's lower cycle bound is less or equal to the current
200 /// scheduling cycle. Always true if all nodes have uniform latency 1.
201 static inline bool isReady(SUnit *SU, unsigned CurCycle) {
202 return SU->CycleBound <= CurCycle;
205 /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
207 void ScheduleDAGRRList::ListScheduleBottomUp() {
208 unsigned CurCycle = 0;
209 // Add root to Available queue.
210 AvailableQueue->push(SUnitMap[DAG.getRoot().Val]);
212 // While Available queue is not empty, grab the node with the highest
213 // priority. If it is not ready put it back. Schedule the node.
214 std::vector<SUnit*> NotReady;
215 SUnit *CurNode = NULL;
216 while (!AvailableQueue->empty()) {
217 SUnit *CurNode = AvailableQueue->pop();
218 while (!isReady(CurNode, CurCycle)) {
219 NotReady.push_back(CurNode);
220 CurNode = AvailableQueue->pop();
223 // Add the nodes that aren't ready back onto the available list.
224 AvailableQueue->push_all(NotReady);
227 ScheduleNodeBottomUp(CurNode, CurCycle);
230 // Add entry node last
231 if (DAG.getEntryNode().Val != DAG.getRoot().Val) {
232 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
233 Sequence.push_back(Entry);
236 // Reverse the order if it is bottom up.
237 std::reverse(Sequence.begin(), Sequence.end());
241 // Verify that all SUnits were scheduled.
242 bool AnyNotSched = false;
243 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
244 if (SUnits[i].NumSuccsLeft != 0 || SUnits[i].NumChainSuccsLeft != 0) {
246 std::cerr << "*** List scheduling failed! ***\n";
247 SUnits[i].dump(&DAG);
248 std::cerr << "has not been scheduled!\n";
252 assert(!AnyNotSched);
256 //===----------------------------------------------------------------------===//
257 // Top-Down Scheduling
258 //===----------------------------------------------------------------------===//
260 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
261 /// the PendingQueue if the count reaches zero.
262 void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain,
264 // FIXME: the distance between two nodes is not always == the predecessor's
265 // latency. For example, the reader can very well read the register written
266 // by the predecessor later than the issue cycle. It also depends on the
267 // interrupt model (drain vs. freeze).
268 SuccSU->CycleBound = std::max(SuccSU->CycleBound, CurCycle + SuccSU->Latency);
271 SuccSU->NumPredsLeft--;
273 SuccSU->NumChainPredsLeft--;
276 if (SuccSU->NumPredsLeft < 0 || SuccSU->NumChainPredsLeft < 0) {
277 std::cerr << "*** List scheduling failed! ***\n";
279 std::cerr << " has been released too many times!\n";
284 if ((SuccSU->NumPredsLeft + SuccSU->NumChainPredsLeft) == 0) {
285 SuccSU->isAvailable = true;
286 AvailableQueue->push(SuccSU);
291 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
292 /// count of its successors. If a successor pending count is zero, add it to
293 /// the Available queue.
294 void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned& CurCycle) {
295 DEBUG(std::cerr << "*** Scheduling [" << CurCycle << "]: ");
296 DEBUG(SU->dump(&DAG));
297 SU->Cycle = CurCycle;
299 AvailableQueue->ScheduledNode(SU);
300 Sequence.push_back(SU);
302 // Top down: release successors
303 for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Succs.begin(),
304 E = SU->Succs.end(); I != E; ++I)
305 ReleaseSucc(I->first, I->second, CurCycle);
306 SU->isScheduled = true;
310 void ScheduleDAGRRList::ListScheduleTopDown() {
311 unsigned CurCycle = 0;
312 SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
314 // All leaves to Available queue.
315 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
316 // It is available if it has no predecessors.
317 if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
318 AvailableQueue->push(&SUnits[i]);
319 SUnits[i].isAvailable = true;
323 // Emit the entry node first.
324 ScheduleNodeTopDown(Entry, CurCycle);
326 // While Available queue is not empty, grab the node with the highest
327 // priority. If it is not ready put it back. Schedule the node.
328 std::vector<SUnit*> NotReady;
329 SUnit *CurNode = NULL;
330 while (!AvailableQueue->empty()) {
331 SUnit *CurNode = AvailableQueue->pop();
332 while (!isReady(CurNode, CurCycle)) {
333 NotReady.push_back(CurNode);
334 CurNode = AvailableQueue->pop();
337 // Add the nodes that aren't ready back onto the available list.
338 AvailableQueue->push_all(NotReady);
341 ScheduleNodeTopDown(CurNode, CurCycle);
346 // Verify that all SUnits were scheduled.
347 bool AnyNotSched = false;
348 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
349 if (!SUnits[i].isScheduled) {
351 std::cerr << "*** List scheduling failed! ***\n";
352 SUnits[i].dump(&DAG);
353 std::cerr << "has not been scheduled!\n";
357 assert(!AnyNotSched);
363 //===----------------------------------------------------------------------===//
364 // RegReductionPriorityQueue Implementation
365 //===----------------------------------------------------------------------===//
367 // This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
368 // to reduce register pressure.
372 class RegReductionPriorityQueue;
374 /// Sorting functions for the Available queue.
375 struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
376 RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ;
377 bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {}
378 bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
380 bool operator()(const SUnit* left, const SUnit* right) const;
383 struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
384 RegReductionPriorityQueue<td_ls_rr_sort> *SPQ;
385 td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {}
386 td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
388 bool operator()(const SUnit* left, const SUnit* right) const;
390 } // end anonymous namespace
394 class RegReductionPriorityQueue : public SchedulingPriorityQueue {
395 std::priority_queue<SUnit*, std::vector<SUnit*>, SF> Queue;
398 RegReductionPriorityQueue() :
401 virtual void initNodes(const std::vector<SUnit> &sunits) {}
402 virtual void releaseState() {}
404 virtual int getSethiUllmanNumber(unsigned NodeNum) const {
408 bool empty() const { return Queue.empty(); }
410 void push(SUnit *U) {
413 void push_all(const std::vector<SUnit *> &Nodes) {
414 for (unsigned i = 0, e = Nodes.size(); i != e; ++i)
415 Queue.push(Nodes[i]);
419 SUnit *V = Queue.top();
426 class BURegReductionPriorityQueue : public RegReductionPriorityQueue<SF> {
427 // SUnits - The SUnits for the current graph.
428 const std::vector<SUnit> *SUnits;
430 // SethiUllmanNumbers - The SethiUllman number for each node.
431 std::vector<int> SethiUllmanNumbers;
434 BURegReductionPriorityQueue() {}
436 void initNodes(const std::vector<SUnit> &sunits) {
438 // Add pseudo dependency edges for two-address nodes.
439 if (SchedLowerDefNUse)
440 AddPseudoTwoAddrDeps();
441 // Calculate node priorities.
442 CalculatePriorities();
445 void releaseState() {
447 SethiUllmanNumbers.clear();
450 int getSethiUllmanNumber(unsigned NodeNum) const {
451 assert(NodeNum < SethiUllmanNumbers.size());
452 return SethiUllmanNumbers[NodeNum];
456 void AddPseudoTwoAddrDeps();
457 void CalculatePriorities();
458 int CalcNodePriority(const SUnit *SU);
463 class TDRegReductionPriorityQueue : public RegReductionPriorityQueue<SF> {
464 // SUnits - The SUnits for the current graph.
465 const std::vector<SUnit> *SUnits;
467 // SethiUllmanNumbers - The SethiUllman number for each node.
468 std::vector<int> SethiUllmanNumbers;
471 TDRegReductionPriorityQueue() {}
473 void initNodes(const std::vector<SUnit> &sunits) {
475 // Calculate node priorities.
476 CalculatePriorities();
479 void releaseState() {
481 SethiUllmanNumbers.clear();
484 int getSethiUllmanNumber(unsigned NodeNum) const {
485 assert(NodeNum < SethiUllmanNumbers.size());
486 return SethiUllmanNumbers[NodeNum];
490 void CalculatePriorities();
491 int CalcNodePriority(const SUnit *SU);
496 bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
497 unsigned LeftNum = left->NodeNum;
498 unsigned RightNum = right->NodeNum;
499 bool LIsTarget = left->Node->isTargetOpcode();
500 bool RIsTarget = right->Node->isTargetOpcode();
501 int LPriority = SPQ->getSethiUllmanNumber(LeftNum);
502 int RPriority = SPQ->getSethiUllmanNumber(RightNum);
503 bool LIsFloater = LIsTarget && (LPriority == 1 || LPriority == 0);
504 bool RIsFloater = RIsTarget && (RPriority == 1 || RPriority == 0);
508 // Schedule floaters (e.g. load from some constant address) and those nodes
509 // with a single predecessor each first. They maintain / reduce register
516 if (!SchedLowerDefNUse) {
517 // Special tie breaker: if two nodes share a operand, the one that use it
518 // as a def&use operand is preferred.
519 if (LIsTarget && RIsTarget) {
520 if (left->isTwoAddress && !right->isTwoAddress) {
521 SDNode *DUNode = left->Node->getOperand(0).Val;
522 if (DUNode->isOperand(right->Node))
525 if (!left->isTwoAddress && right->isTwoAddress) {
526 SDNode *DUNode = right->Node->getOperand(0).Val;
527 if (DUNode->isOperand(left->Node))
533 if (LPriority+LBonus < RPriority+RBonus)
535 else if (LPriority+LBonus == RPriority+RBonus)
536 if (left->NumPredsLeft > right->NumPredsLeft)
538 else if (left->NumPredsLeft+LBonus == right->NumPredsLeft+RBonus)
539 if (left->CycleBound > right->CycleBound)
544 static inline bool isCopyFromLiveIn(const SUnit *SU) {
545 SDNode *N = SU->Node;
546 return N->getOpcode() == ISD::CopyFromReg &&
547 N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag;
550 // FIXME: This is probably too slow!
551 static void isReachable(SUnit *SU, SUnit *TargetSU,
552 std::set<SUnit *> &Visited, bool &Reached) {
554 if (SU == TargetSU) {
558 if (!Visited.insert(SU).second) return;
560 for (std::set<std::pair<SUnit*, bool> >::iterator I = SU->Preds.begin(),
561 E = SU->Preds.end(); I != E; ++I)
562 isReachable(I->first, TargetSU, Visited, Reached);
565 static bool isReachable(SUnit *SU, SUnit *TargetSU) {
566 std::set<SUnit *> Visited;
567 bool Reached = false;
568 isReachable(SU, TargetSU, Visited, Reached);
572 static SUnit *getDefUsePredecessor(SUnit *SU) {
573 SDNode *DU = SU->Node->getOperand(0).Val;
574 for (std::set<std::pair<SUnit*, bool> >::iterator
575 I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) {
576 if (I->second) continue; // ignore chain preds
577 SUnit *PredSU = I->first;
578 if (PredSU->Node == DU)
586 static bool canClobber(SUnit *SU, SUnit *Op) {
587 if (SU->isTwoAddress)
588 return Op == getDefUsePredecessor(SU);
592 /// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
593 /// it as a def&use operand. Add a pseudo control edge from it to the other
594 /// node (if it won't create a cycle) so the two-address one will be scheduled
595 /// first (lower in the schedule).
597 void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
598 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
599 SUnit *SU = (SUnit *)&((*SUnits)[i]);
600 SDNode *Node = SU->Node;
601 if (!Node->isTargetOpcode())
604 if (SU->isTwoAddress) {
605 unsigned Depth = SU->Node->getNodeDepth();
606 SUnit *DUSU = getDefUsePredecessor(SU);
609 for (std::set<std::pair<SUnit*, bool> >::iterator I = DUSU->Succs.begin(),
610 E = DUSU->Succs.end(); I != E; ++I) {
611 SUnit *SuccSU = I->first;
612 if (SuccSU != SU && !canClobber(SuccSU, DUSU)) {
613 if (SuccSU->Node->getNodeDepth() <= Depth+2 &&
614 !isReachable(SuccSU, SU)) {
615 DEBUG(std::cerr << "Adding an edge from SU # " << SU->NodeNum
616 << " to SU #" << SuccSU->NodeNum << "\n");
617 if (SU->Preds.insert(std::make_pair(SuccSU, true)).second)
618 SU->NumChainPredsLeft++;
619 if (SuccSU->Succs.insert(std::make_pair(SU, true)).second)
620 SuccSU->NumChainSuccsLeft++;
628 /// CalcNodePriority - Priority is the Sethi Ullman number.
629 /// Smaller number is the higher priority.
631 int BURegReductionPriorityQueue<SF>::CalcNodePriority(const SUnit *SU) {
632 int &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
633 if (SethiUllmanNumber != 0)
634 return SethiUllmanNumber;
636 unsigned Opc = SU->Node->getOpcode();
637 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
638 SethiUllmanNumber = INT_MAX - 10;
639 else if (SU->NumSuccsLeft == 0)
640 // If SU does not have a use, i.e. it doesn't produce a value that would
641 // be consumed (e.g. store), then it terminates a chain of computation.
642 // Give it a small SethiUllman number so it will be scheduled right before its
643 // predecessors that it doesn't lengthen their live ranges.
644 SethiUllmanNumber = INT_MIN + 10;
645 else if (SU->NumPredsLeft == 0 &&
646 (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
647 SethiUllmanNumber = 1;
650 for (std::set<std::pair<SUnit*, bool> >::const_iterator
651 I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) {
652 if (I->second) continue; // ignore chain preds
653 SUnit *PredSU = I->first;
654 int PredSethiUllman = CalcNodePriority(PredSU);
655 if (PredSethiUllman > SethiUllmanNumber) {
656 SethiUllmanNumber = PredSethiUllman;
658 } else if (PredSethiUllman == SethiUllmanNumber && !I->second)
662 SethiUllmanNumber += Extra;
665 return SethiUllmanNumber;
668 /// CalculatePriorities - Calculate priorities of all scheduling units.
670 void BURegReductionPriorityQueue<SF>::CalculatePriorities() {
671 SethiUllmanNumbers.assign(SUnits->size(), 0);
673 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
674 CalcNodePriority(&(*SUnits)[i]);
677 static unsigned SumOfUnscheduledPredsOfSuccs(const SUnit *SU) {
679 for (std::set<std::pair<SUnit*, bool> >::const_iterator
680 I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) {
681 SUnit *SuccSU = I->first;
682 for (std::set<std::pair<SUnit*, bool> >::const_iterator
683 II = SuccSU->Preds.begin(), EE = SuccSU->Preds.end(); II != EE; ++II) {
684 SUnit *PredSU = II->first;
685 if (!PredSU->isScheduled)
695 bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
696 unsigned LeftNum = left->NodeNum;
697 unsigned RightNum = right->NodeNum;
698 int LPriority = SPQ->getSethiUllmanNumber(LeftNum);
699 int RPriority = SPQ->getSethiUllmanNumber(RightNum);
700 bool LIsTarget = left->Node->isTargetOpcode();
701 bool RIsTarget = right->Node->isTargetOpcode();
702 bool LIsFloater = LIsTarget && left->NumPreds == 0;
703 bool RIsFloater = RIsTarget && right->NumPreds == 0;
704 unsigned LBonus = (SumOfUnscheduledPredsOfSuccs(left) == 1) ? 2 : 0;
705 unsigned RBonus = (SumOfUnscheduledPredsOfSuccs(right) == 1) ? 2 : 0;
707 if (left->NumSuccs == 0 && right->NumSuccs != 0)
709 else if (left->NumSuccs != 0 && right->NumSuccs == 0)
712 // Special tie breaker: if two nodes share a operand, the one that use it
713 // as a def&use operand is preferred.
714 if (LIsTarget && RIsTarget) {
715 if (left->isTwoAddress && !right->isTwoAddress) {
716 SDNode *DUNode = left->Node->getOperand(0).Val;
717 if (DUNode->isOperand(right->Node))
720 if (!left->isTwoAddress && right->isTwoAddress) {
721 SDNode *DUNode = right->Node->getOperand(0).Val;
722 if (DUNode->isOperand(left->Node))
730 if (left->NumSuccs == 1)
732 if (right->NumSuccs == 1)
735 if (LPriority+LBonus < RPriority+RBonus)
737 else if (LPriority == RPriority)
738 if (left->Depth < right->Depth)
740 else if (left->Depth == right->Depth)
741 if (left->NumSuccsLeft > right->NumSuccsLeft)
743 else if (left->NumSuccsLeft == right->NumSuccsLeft)
744 if (left->CycleBound > right->CycleBound)
749 /// CalcNodePriority - Priority is the Sethi Ullman number.
750 /// Smaller number is the higher priority.
752 int TDRegReductionPriorityQueue<SF>::CalcNodePriority(const SUnit *SU) {
753 int &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
754 if (SethiUllmanNumber != 0)
755 return SethiUllmanNumber;
757 unsigned Opc = SU->Node->getOpcode();
758 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
759 SethiUllmanNumber = INT_MAX - 10;
760 else if (SU->NumSuccsLeft == 0)
761 // If SU does not have a use, i.e. it doesn't produce a value that would
762 // be consumed (e.g. store), then it terminates a chain of computation.
763 // Give it a small SethiUllman number so it will be scheduled right before its
764 // predecessors that it doesn't lengthen their live ranges.
765 SethiUllmanNumber = INT_MIN + 10;
766 else if (SU->NumPredsLeft == 0 &&
767 (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
768 SethiUllmanNumber = 1;
771 for (std::set<std::pair<SUnit*, bool> >::const_iterator
772 I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) {
773 if (I->second) continue; // ignore chain preds
774 SUnit *PredSU = I->first;
775 int PredSethiUllman = CalcNodePriority(PredSU);
776 if (PredSethiUllman > SethiUllmanNumber) {
777 SethiUllmanNumber = PredSethiUllman;
779 } else if (PredSethiUllman == SethiUllmanNumber && !I->second)
783 SethiUllmanNumber += Extra;
786 return SethiUllmanNumber;
789 /// CalculatePriorities - Calculate priorities of all scheduling units.
791 void TDRegReductionPriorityQueue<SF>::CalculatePriorities() {
792 SethiUllmanNumbers.assign(SUnits->size(), 0);
794 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
795 CalcNodePriority(&(*SUnits)[i]);
798 //===----------------------------------------------------------------------===//
799 // Public Constructor Functions
800 //===----------------------------------------------------------------------===//
802 llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG &DAG,
803 MachineBasicBlock *BB) {
804 return new ScheduleDAGRRList(DAG, BB, DAG.getTarget(), true,
805 new BURegReductionPriorityQueue<bu_ls_rr_sort>());
808 llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAG &DAG,
809 MachineBasicBlock *BB) {
810 return new ScheduleDAGRRList(DAG, BB, DAG.getTarget(), false,
811 new TDRegReductionPriorityQueue<td_ls_rr_sort>());