1 //===----- ScheduleDAGList.cpp - Reg pressure reduction list scheduler ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements bottom-up and top-down register pressure reduction list
11 // schedulers, using standard algorithms. The basic approach uses a priority
12 // queue of available nodes to schedule. One at a time, nodes are taken from
13 // the priority queue (thus in priority order), checked for legality to
14 // schedule, and emitted if legal.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "pre-RA-sched"
19 #include "llvm/CodeGen/ScheduleDAG.h"
20 #include "llvm/CodeGen/SchedulerRegistry.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/Compiler.h"
27 #include "llvm/ADT/SmallPtrSet.h"
28 #include "llvm/ADT/SmallSet.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/ADT/STLExtras.h"
33 #include "llvm/Support/CommandLine.h"
36 STATISTIC(NumBacktracks, "Number of times scheduler backtracked");
37 STATISTIC(NumUnfolds, "Number of nodes unfolded");
38 STATISTIC(NumDups, "Number of duplicated nodes");
39 STATISTIC(NumCCCopies, "Number of cross class copies");
41 static RegisterScheduler
42 burrListDAGScheduler("list-burr",
43 " Bottom-up register reduction list scheduling",
44 createBURRListDAGScheduler);
45 static RegisterScheduler
46 tdrListrDAGScheduler("list-tdrr",
47 " Top-down register reduction list scheduling",
48 createTDRRListDAGScheduler);
51 //===----------------------------------------------------------------------===//
52 /// ScheduleDAGRRList - The actual register reduction list scheduler
53 /// implementation. This supports both top-down and bottom-up scheduling.
55 class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAG {
57 /// isBottomUp - This is true if the scheduling problem is bottom-up, false if
61 /// AvailableQueue - The priority queue to use for the available SUnits.
62 SchedulingPriorityQueue *AvailableQueue;
64 /// LiveRegs / LiveRegDefs - A set of physical registers and their definition
65 /// that are "live". These nodes must be scheduled before any other nodes that
66 /// modifies the registers can be scheduled.
67 SmallSet<unsigned, 4> LiveRegs;
68 std::vector<SUnit*> LiveRegDefs;
69 std::vector<unsigned> LiveRegCycles;
72 ScheduleDAGRRList(SelectionDAG &dag, MachineBasicBlock *bb,
73 const TargetMachine &tm, bool isbottomup,
74 SchedulingPriorityQueue *availqueue)
75 : ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup),
76 AvailableQueue(availqueue) {
79 ~ScheduleDAGRRList() {
80 delete AvailableQueue;
85 /// IsReachable - Checks if SU is reachable from TargetSU.
86 bool IsReachable(SUnit *SU, SUnit *TargetSU);
88 /// willCreateCycle - Returns true if adding an edge from SU to TargetSU will
90 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
92 /// AddPred - This adds the specified node X as a predecessor of
93 /// the current node Y if not already.
94 /// This returns true if this is a new predecessor.
95 /// Updates the topological ordering if required.
96 bool AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial,
97 unsigned PhyReg = 0, int Cost = 1);
99 /// RemovePred - This removes the specified node N from the predecessors of
100 /// the current node M. Updates the topological ordering if required.
101 bool RemovePred(SUnit *M, SUnit *N, bool isCtrl, bool isSpecial);
104 void ReleasePred(SUnit*, bool, unsigned);
105 void ReleaseSucc(SUnit*, bool isChain, unsigned);
106 void CapturePred(SUnit*, SUnit*, bool);
107 void ScheduleNodeBottomUp(SUnit*, unsigned);
108 void ScheduleNodeTopDown(SUnit*, unsigned);
109 void UnscheduleNodeBottomUp(SUnit*);
110 void BacktrackBottomUp(SUnit*, unsigned, unsigned&);
111 SUnit *CopyAndMoveSuccessors(SUnit*);
112 void InsertCCCopiesAndMoveSuccs(SUnit*, unsigned,
113 const TargetRegisterClass*,
114 const TargetRegisterClass*,
115 SmallVector<SUnit*, 2>&);
116 bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&);
117 void ListScheduleTopDown();
118 void ListScheduleBottomUp();
119 void CommuteNodesToReducePressure();
122 /// CreateNewSUnit - Creates a new SUnit and returns a pointer to it.
123 /// Updates the topological ordering if required.
124 SUnit *CreateNewSUnit(SDNode *N) {
125 SUnit *NewNode = NewSUnit(N);
126 // Update the topological ordering.
127 if (NewNode->NodeNum >= Node2Index.size())
128 InitDAGTopologicalSorting();
132 /// CreateClone - Creates a new SUnit from an existing one.
133 /// Updates the topological ordering if required.
134 SUnit *CreateClone(SUnit *N) {
135 SUnit *NewNode = Clone(N);
136 // Update the topological ordering.
137 if (NewNode->NodeNum >= Node2Index.size())
138 InitDAGTopologicalSorting();
142 /// Functions for preserving the topological ordering
143 /// even after dynamic insertions of new edges.
144 /// This allows a very fast implementation of IsReachable.
148 The idea of the algorithm is taken from
149 "Online algorithms for managing the topological order of
150 a directed acyclic graph" by David J. Pearce and Paul H.J. Kelly
151 This is the MNR algorithm, which was first introduced by
152 A. Marchetti-Spaccamela, U. Nanni and H. Rohnert in
153 "Maintaining a topological order under edge insertions".
155 Short description of the algorithm:
157 Topological ordering, ord, of a DAG maps each node to a topological
158 index so that for all edges X->Y it is the case that ord(X) < ord(Y).
160 This means that if there is a path from the node X to the node Z,
161 then ord(X) < ord(Z).
163 This property can be used to check for reachability of nodes:
164 if Z is reachable from X, then an insertion of the edge Z->X would
167 The algorithm first computes a topological ordering for the DAG by initializing
168 the Index2Node and Node2Index arrays and then tries to keep the ordering
169 up-to-date after edge insertions by reordering the DAG.
171 On insertion of the edge X->Y, the algorithm first marks by calling DFS the
172 nodes reachable from Y, and then shifts them using Shift to lie immediately
173 after X in Index2Node.
176 /// InitDAGTopologicalSorting - create the initial topological
177 /// ordering from the DAG to be scheduled.
178 void InitDAGTopologicalSorting();
180 /// DFS - make a DFS traversal and mark all nodes affected by the
181 /// edge insertion. These nodes will later get new topological indexes
182 /// by means of the Shift method.
183 void DFS(SUnit *SU, int UpperBound, bool& HasLoop);
185 /// Shift - reassign topological indexes for the nodes in the DAG
186 /// to preserve the topological ordering.
187 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
189 /// Allocate - assign the topological index to the node n.
190 void Allocate(int n, int index);
192 /// Index2Node - Maps topological index to the node number.
193 std::vector<int> Index2Node;
194 /// Node2Index - Maps the node number to its topological index.
195 std::vector<int> Node2Index;
196 /// Visited - a set of nodes visited during a DFS traversal.
199 } // end anonymous namespace
202 /// Schedule - Schedule the DAG using list scheduling.
203 void ScheduleDAGRRList::Schedule() {
204 DOUT << "********** List Scheduling **********\n";
206 LiveRegDefs.resize(TRI->getNumRegs(), NULL);
207 LiveRegCycles.resize(TRI->getNumRegs(), 0);
209 // Build scheduling units.
212 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
213 SUnits[su].dumpAll(&DAG));
216 InitDAGTopologicalSorting();
218 AvailableQueue->initNodes(SUnitMap, SUnits);
220 // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
222 ListScheduleBottomUp();
224 ListScheduleTopDown();
226 AvailableQueue->releaseState();
228 CommuteNodesToReducePressure();
230 DOUT << "*** Final schedule ***\n";
231 DEBUG(dumpSchedule());
234 // Emit in scheduled order
238 /// CommuteNodesToReducePressure - If a node is two-address and commutable, and
239 /// it is not the last use of its first operand, add it to the CommuteSet if
240 /// possible. It will be commuted when it is translated to a MI.
241 void ScheduleDAGRRList::CommuteNodesToReducePressure() {
242 SmallPtrSet<SUnit*, 4> OperandSeen;
243 for (unsigned i = Sequence.size(); i != 0; ) {
245 SUnit *SU = Sequence[i];
246 if (!SU || !SU->Node) continue;
247 if (SU->isCommutable) {
248 unsigned Opc = SU->Node->getTargetOpcode();
249 const TargetInstrDesc &TID = TII->get(Opc);
250 unsigned NumRes = TID.getNumDefs();
251 unsigned NumOps = TID.getNumOperands() - NumRes;
252 for (unsigned j = 0; j != NumOps; ++j) {
253 if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
256 SDNode *OpN = SU->Node->getOperand(j).Val;
257 SUnit *OpSU = isPassiveNode(OpN) ? NULL : SUnitMap[OpN];
258 if (OpSU && OperandSeen.count(OpSU) == 1) {
259 // Ok, so SU is not the last use of OpSU, but SU is two-address so
260 // it will clobber OpSU. Try to commute SU if no other source operands
262 bool DoCommute = true;
263 for (unsigned k = 0; k < NumOps; ++k) {
265 OpN = SU->Node->getOperand(k).Val;
266 OpSU = isPassiveNode(OpN) ? NULL : SUnitMap[OpN];
267 if (OpSU && OperandSeen.count(OpSU) == 1) {
274 CommuteSet.insert(SU->Node);
277 // Only look at the first use&def node for now.
282 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
285 OperandSeen.insert(I->Dep->OrigNode);
290 //===----------------------------------------------------------------------===//
291 // Bottom-Up Scheduling
292 //===----------------------------------------------------------------------===//
294 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
295 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
296 void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
298 // FIXME: the distance between two nodes is not always == the predecessor's
299 // latency. For example, the reader can very well read the register written
300 // by the predecessor later than the issue cycle. It also depends on the
301 // interrupt model (drain vs. freeze).
302 PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency);
304 --PredSU->NumSuccsLeft;
307 if (PredSU->NumSuccsLeft < 0) {
308 cerr << "*** List scheduling failed! ***\n";
310 cerr << " has been released too many times!\n";
315 if (PredSU->NumSuccsLeft == 0) {
316 PredSU->isAvailable = true;
317 AvailableQueue->push(PredSU);
321 /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
322 /// count of its predecessors. If a predecessor pending count is zero, add it to
323 /// the Available queue.
324 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
325 DOUT << "*** Scheduling [" << CurCycle << "]: ";
326 DEBUG(SU->dump(&DAG));
327 SU->Cycle = CurCycle;
329 AvailableQueue->ScheduledNode(SU);
331 // Bottom up: release predecessors
332 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
334 ReleasePred(I->Dep, I->isCtrl, CurCycle);
336 // This is a physical register dependency and it's impossible or
337 // expensive to copy the register. Make sure nothing that can
338 // clobber the register is scheduled between the predecessor and
340 if (LiveRegs.insert(I->Reg)) {
341 LiveRegDefs[I->Reg] = I->Dep;
342 LiveRegCycles[I->Reg] = CurCycle;
347 // Release all the implicit physical register defs that are live.
348 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
351 if (LiveRegCycles[I->Reg] == I->Dep->Cycle) {
352 LiveRegs.erase(I->Reg);
353 assert(LiveRegDefs[I->Reg] == SU &&
354 "Physical register dependency violated?");
355 LiveRegDefs[I->Reg] = NULL;
356 LiveRegCycles[I->Reg] = 0;
361 SU->isScheduled = true;
364 /// CapturePred - This does the opposite of ReleasePred. Since SU is being
365 /// unscheduled, incrcease the succ left count of its predecessors. Remove
366 /// them from AvailableQueue if necessary.
367 void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) {
368 unsigned CycleBound = 0;
369 for (SUnit::succ_iterator I = PredSU->Succs.begin(), E = PredSU->Succs.end();
373 CycleBound = std::max(CycleBound,
374 I->Dep->Cycle + PredSU->Latency);
377 if (PredSU->isAvailable) {
378 PredSU->isAvailable = false;
379 if (!PredSU->isPending)
380 AvailableQueue->remove(PredSU);
383 PredSU->CycleBound = CycleBound;
384 ++PredSU->NumSuccsLeft;
387 /// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and
388 /// its predecessor states to reflect the change.
389 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
390 DOUT << "*** Unscheduling [" << SU->Cycle << "]: ";
391 DEBUG(SU->dump(&DAG));
393 AvailableQueue->UnscheduledNode(SU);
395 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
397 CapturePred(I->Dep, SU, I->isCtrl);
398 if (I->Cost < 0 && SU->Cycle == LiveRegCycles[I->Reg]) {
399 LiveRegs.erase(I->Reg);
400 assert(LiveRegDefs[I->Reg] == I->Dep &&
401 "Physical register dependency violated?");
402 LiveRegDefs[I->Reg] = NULL;
403 LiveRegCycles[I->Reg] = 0;
407 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
410 if (LiveRegs.insert(I->Reg)) {
411 assert(!LiveRegDefs[I->Reg] &&
412 "Physical register dependency violated?");
413 LiveRegDefs[I->Reg] = SU;
415 if (I->Dep->Cycle < LiveRegCycles[I->Reg])
416 LiveRegCycles[I->Reg] = I->Dep->Cycle;
421 SU->isScheduled = false;
422 SU->isAvailable = true;
423 AvailableQueue->push(SU);
426 /// IsReachable - Checks if SU is reachable from TargetSU.
427 bool ScheduleDAGRRList::IsReachable(SUnit *SU, SUnit *TargetSU) {
428 // If insertion of the edge SU->TargetSU would create a cycle
429 // then there is a path from TargetSU to SU.
430 int UpperBound, LowerBound;
431 LowerBound = Node2Index[TargetSU->NodeNum];
432 UpperBound = Node2Index[SU->NodeNum];
433 bool HasLoop = false;
434 // Is Ord(TargetSU) < Ord(SU) ?
435 if (LowerBound < UpperBound) {
437 // There may be a path from TargetSU to SU. Check for it.
438 DFS(TargetSU, UpperBound, HasLoop);
443 /// Allocate - assign the topological index to the node n.
444 inline void ScheduleDAGRRList::Allocate(int n, int index) {
445 Node2Index[n] = index;
446 Index2Node[index] = n;
449 /// InitDAGTopologicalSorting - create the initial topological
450 /// ordering from the DAG to be scheduled.
451 void ScheduleDAGRRList::InitDAGTopologicalSorting() {
452 unsigned DAGSize = SUnits.size();
453 std::vector<unsigned> InDegree(DAGSize);
454 std::vector<SUnit*> WorkList;
455 WorkList.reserve(DAGSize);
456 std::vector<SUnit*> TopOrder;
457 TopOrder.reserve(DAGSize);
459 // Initialize the data structures.
460 for (unsigned i = 0, e = DAGSize; i != e; ++i) {
461 SUnit *SU = &SUnits[i];
462 int NodeNum = SU->NodeNum;
463 unsigned Degree = SU->Succs.size();
464 InDegree[NodeNum] = Degree;
466 // Is it a node without dependencies?
468 assert(SU->Succs.empty() && "SUnit should have no successors");
469 // Collect leaf nodes.
470 WorkList.push_back(SU);
474 while (!WorkList.empty()) {
475 SUnit *SU = WorkList.back();
477 TopOrder.push_back(SU);
478 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
481 if (!--InDegree[SU->NodeNum])
482 // If all dependencies of the node are processed already,
483 // then the node can be computed now.
484 WorkList.push_back(SU);
488 // Second pass, assign the actual topological order as node ids.
493 Index2Node.resize(DAGSize);
494 Node2Index.resize(DAGSize);
495 Visited.resize(DAGSize);
497 for (std::vector<SUnit*>::reverse_iterator TI = TopOrder.rbegin(),
498 TE = TopOrder.rend();TI != TE; ++TI) {
499 Allocate((*TI)->NodeNum, Id);
504 // Check correctness of the ordering
505 for (unsigned i = 0, e = DAGSize; i != e; ++i) {
506 SUnit *SU = &SUnits[i];
507 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
509 assert(Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] &&
510 "Wrong topological sorting");
516 /// AddPred - adds an edge from SUnit X to SUnit Y.
517 /// Updates the topological ordering if required.
518 bool ScheduleDAGRRList::AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial,
519 unsigned PhyReg, int Cost) {
520 int UpperBound, LowerBound;
521 LowerBound = Node2Index[Y->NodeNum];
522 UpperBound = Node2Index[X->NodeNum];
523 bool HasLoop = false;
524 // Is Ord(X) < Ord(Y) ?
525 if (LowerBound < UpperBound) {
526 // Update the topological order.
528 DFS(Y, UpperBound, HasLoop);
529 assert(!HasLoop && "Inserted edge creates a loop!");
530 // Recompute topological indexes.
531 Shift(Visited, LowerBound, UpperBound);
533 // Now really insert the edge.
534 return Y->addPred(X, isCtrl, isSpecial, PhyReg, Cost);
537 /// RemovePred - This removes the specified node N from the predecessors of
538 /// the current node M. Updates the topological ordering if required.
539 bool ScheduleDAGRRList::RemovePred(SUnit *M, SUnit *N,
540 bool isCtrl, bool isSpecial) {
541 // InitDAGTopologicalSorting();
542 return M->removePred(N, isCtrl, isSpecial);
545 /// DFS - Make a DFS traversal to mark all nodes reachable from SU and mark
546 /// all nodes affected by the edge insertion. These nodes will later get new
547 /// topological indexes by means of the Shift method.
548 void ScheduleDAGRRList::DFS(SUnit *SU, int UpperBound, bool& HasLoop) {
549 std::vector<SUnit*> WorkList;
550 WorkList.reserve(SUnits.size());
552 WorkList.push_back(SU);
553 while (!WorkList.empty()) {
554 SU = WorkList.back();
556 Visited.set(SU->NodeNum);
557 for (int I = SU->Succs.size()-1; I >= 0; --I) {
558 int s = SU->Succs[I].Dep->NodeNum;
559 if (Node2Index[s] == UpperBound) {
563 // Visit successors if not already and in affected region.
564 if (!Visited.test(s) && Node2Index[s] < UpperBound) {
565 WorkList.push_back(SU->Succs[I].Dep);
571 /// Shift - Renumber the nodes so that the topological ordering is
573 void ScheduleDAGRRList::Shift(BitVector& Visited, int LowerBound,
579 for (i = LowerBound; i <= UpperBound; ++i) {
580 // w is node at topological index i.
581 int w = Index2Node[i];
582 if (Visited.test(w)) {
588 Allocate(w, i - shift);
592 for (unsigned j = 0; j < L.size(); ++j) {
593 Allocate(L[j], i - shift);
599 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
601 bool ScheduleDAGRRList::WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
602 if (IsReachable(TargetSU, SU))
604 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
606 if (I->Cost < 0 && IsReachable(TargetSU, I->Dep))
611 /// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in
612 /// BTCycle in order to schedule a specific node. Returns the last unscheduled
613 /// SUnit. Also returns if a successor is unscheduled in the process.
614 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, unsigned BtCycle,
615 unsigned &CurCycle) {
617 while (CurCycle > BtCycle) {
618 OldSU = Sequence.back();
620 if (SU->isSucc(OldSU))
621 // Don't try to remove SU from AvailableQueue.
622 SU->isAvailable = false;
623 UnscheduleNodeBottomUp(OldSU);
628 if (SU->isSucc(OldSU)) {
629 assert(false && "Something is wrong!");
636 /// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
637 /// successors to the newly created node.
638 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
639 if (SU->FlaggedNodes.size())
642 SDNode *N = SU->Node;
647 bool TryUnfold = false;
648 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
649 MVT VT = N->getValueType(i);
652 else if (VT == MVT::Other)
655 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
656 const SDOperand &Op = N->getOperand(i);
657 MVT VT = Op.Val->getValueType(Op.ResNo);
663 SmallVector<SDNode*, 2> NewNodes;
664 if (!TII->unfoldMemoryOperand(DAG, N, NewNodes))
667 DOUT << "Unfolding SU # " << SU->NodeNum << "\n";
668 assert(NewNodes.size() == 2 && "Expected a load folding node!");
671 SDNode *LoadNode = NewNodes[0];
672 unsigned NumVals = N->getNumValues();
673 unsigned OldNumVals = SU->Node->getNumValues();
674 for (unsigned i = 0; i != NumVals; ++i)
675 DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, i), SDOperand(N, i));
676 DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, OldNumVals-1),
677 SDOperand(LoadNode, 1));
679 SUnit *NewSU = CreateNewSUnit(N);
680 bool isNew = SUnitMap.insert(std::make_pair(N, NewSU));
682 assert(isNew && "Node already inserted!");
684 const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
685 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
686 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
687 NewSU->isTwoAddress = true;
691 if (TID.isCommutable())
692 NewSU->isCommutable = true;
693 // FIXME: Calculate height / depth and propagate the changes?
694 NewSU->Depth = SU->Depth;
695 NewSU->Height = SU->Height;
696 ComputeLatency(NewSU);
698 // LoadNode may already exist. This can happen when there is another
699 // load from the same location and producing the same type of value
700 // but it has different alignment or volatileness.
701 bool isNewLoad = true;
703 DenseMap<SDNode*, SUnit*>::iterator SMI = SUnitMap.find(LoadNode);
704 if (SMI != SUnitMap.end()) {
705 LoadSU = SMI->second;
708 LoadSU = CreateNewSUnit(LoadNode);
709 bool isNew = SUnitMap.insert(std::make_pair(LoadNode, LoadSU));
711 assert(isNew && "Node already inserted!");
713 LoadSU->Depth = SU->Depth;
714 LoadSU->Height = SU->Height;
715 ComputeLatency(LoadSU);
718 SUnit *ChainPred = NULL;
719 SmallVector<SDep, 4> ChainSuccs;
720 SmallVector<SDep, 4> LoadPreds;
721 SmallVector<SDep, 4> NodePreds;
722 SmallVector<SDep, 4> NodeSuccs;
723 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
727 else if (I->Dep->Node && I->Dep->Node->isOperandOf(LoadNode))
728 LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false));
730 NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false));
732 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
735 ChainSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost,
736 I->isCtrl, I->isSpecial));
738 NodeSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost,
739 I->isCtrl, I->isSpecial));
743 RemovePred(SU, ChainPred, true, false);
745 AddPred(LoadSU, ChainPred, true, false);
747 for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
748 SDep *Pred = &LoadPreds[i];
749 RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial);
751 AddPred(LoadSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial,
752 Pred->Reg, Pred->Cost);
755 for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
756 SDep *Pred = &NodePreds[i];
757 RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial);
758 AddPred(NewSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial,
759 Pred->Reg, Pred->Cost);
761 for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) {
762 SDep *Succ = &NodeSuccs[i];
763 RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial);
764 AddPred(Succ->Dep, NewSU, Succ->isCtrl, Succ->isSpecial,
765 Succ->Reg, Succ->Cost);
767 for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
768 SDep *Succ = &ChainSuccs[i];
769 RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial);
771 AddPred(Succ->Dep, LoadSU, Succ->isCtrl, Succ->isSpecial,
772 Succ->Reg, Succ->Cost);
776 AddPred(NewSU, LoadSU, false, false);
780 AvailableQueue->addNode(LoadSU);
781 AvailableQueue->addNode(NewSU);
785 if (NewSU->NumSuccsLeft == 0) {
786 NewSU->isAvailable = true;
792 DOUT << "Duplicating SU # " << SU->NodeNum << "\n";
793 NewSU = CreateClone(SU);
795 // New SUnit has the exact same predecessors.
796 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
799 AddPred(NewSU, I->Dep, I->isCtrl, false, I->Reg, I->Cost);
800 NewSU->Depth = std::max(NewSU->Depth, I->Dep->Depth+1);
803 // Only copy scheduled successors. Cut them from old node's successor
804 // list and move them over.
805 SmallVector<std::pair<SUnit*, bool>, 4> DelDeps;
806 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
810 if (I->Dep->isScheduled) {
811 NewSU->Height = std::max(NewSU->Height, I->Dep->Height+1);
812 AddPred(I->Dep, NewSU, I->isCtrl, false, I->Reg, I->Cost);
813 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
816 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
817 SUnit *Succ = DelDeps[i].first;
818 bool isCtrl = DelDeps[i].second;
819 RemovePred(Succ, SU, isCtrl, false);
822 AvailableQueue->updateNode(SU);
823 AvailableQueue->addNode(NewSU);
829 /// InsertCCCopiesAndMoveSuccs - Insert expensive cross register class copies
830 /// and move all scheduled successors of the given SUnit to the last copy.
831 void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
832 const TargetRegisterClass *DestRC,
833 const TargetRegisterClass *SrcRC,
834 SmallVector<SUnit*, 2> &Copies) {
835 SUnit *CopyFromSU = CreateNewSUnit(NULL);
836 CopyFromSU->CopySrcRC = SrcRC;
837 CopyFromSU->CopyDstRC = DestRC;
838 CopyFromSU->Depth = SU->Depth;
839 CopyFromSU->Height = SU->Height;
841 SUnit *CopyToSU = CreateNewSUnit(NULL);
842 CopyToSU->CopySrcRC = DestRC;
843 CopyToSU->CopyDstRC = SrcRC;
845 // Only copy scheduled successors. Cut them from old node's successor
846 // list and move them over.
847 SmallVector<std::pair<SUnit*, bool>, 4> DelDeps;
848 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
852 if (I->Dep->isScheduled) {
853 CopyToSU->Height = std::max(CopyToSU->Height, I->Dep->Height+1);
854 AddPred(I->Dep, CopyToSU, I->isCtrl, false, I->Reg, I->Cost);
855 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
858 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
859 SUnit *Succ = DelDeps[i].first;
860 bool isCtrl = DelDeps[i].second;
861 RemovePred(Succ, SU, isCtrl, false);
864 AddPred(CopyFromSU, SU, false, false, Reg, -1);
865 AddPred(CopyToSU, CopyFromSU, false, false, Reg, 1);
867 AvailableQueue->updateNode(SU);
868 AvailableQueue->addNode(CopyFromSU);
869 AvailableQueue->addNode(CopyToSU);
870 Copies.push_back(CopyFromSU);
871 Copies.push_back(CopyToSU);
876 /// getPhysicalRegisterVT - Returns the ValueType of the physical register
877 /// definition of the specified node.
878 /// FIXME: Move to SelectionDAG?
879 static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
880 const TargetInstrInfo *TII) {
881 const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
882 assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
883 unsigned NumRes = TID.getNumDefs();
884 for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
889 return N->getValueType(NumRes);
892 /// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
893 /// scheduling of the given node to satisfy live physical register dependencies.
894 /// If the specific node is the last one that's available to schedule, do
895 /// whatever is necessary (i.e. backtracking or cloning) to make it possible.
896 bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
897 SmallVector<unsigned, 4> &LRegs){
898 if (LiveRegs.empty())
901 SmallSet<unsigned, 4> RegAdded;
902 // If this node would clobber any "live" register, then it's not ready.
903 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
906 unsigned Reg = I->Reg;
907 if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) {
908 if (RegAdded.insert(Reg))
909 LRegs.push_back(Reg);
911 for (const unsigned *Alias = TRI->getAliasSet(Reg);
913 if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
914 if (RegAdded.insert(*Alias))
915 LRegs.push_back(*Alias);
920 for (unsigned i = 0, e = SU->FlaggedNodes.size()+1; i != e; ++i) {
921 SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
922 if (!Node || !Node->isTargetOpcode())
924 const TargetInstrDesc &TID = TII->get(Node->getTargetOpcode());
925 if (!TID.ImplicitDefs)
927 for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
928 if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) {
929 if (RegAdded.insert(*Reg))
930 LRegs.push_back(*Reg);
932 for (const unsigned *Alias = TRI->getAliasSet(*Reg);
934 if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
935 if (RegAdded.insert(*Alias))
936 LRegs.push_back(*Alias);
940 return !LRegs.empty();
944 /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
946 void ScheduleDAGRRList::ListScheduleBottomUp() {
947 unsigned CurCycle = 0;
948 // Add root to Available queue.
949 if (!SUnits.empty()) {
950 SUnit *RootSU = SUnitMap[DAG.getRoot().Val];
951 assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
952 RootSU->isAvailable = true;
953 AvailableQueue->push(RootSU);
956 // While Available queue is not empty, grab the node with the highest
957 // priority. If it is not ready put it back. Schedule the node.
958 SmallVector<SUnit*, 4> NotReady;
959 Sequence.reserve(SUnits.size());
960 while (!AvailableQueue->empty()) {
961 bool Delayed = false;
962 DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap;
963 SUnit *CurSU = AvailableQueue->pop();
965 if (CurSU->CycleBound <= CurCycle) {
966 SmallVector<unsigned, 4> LRegs;
967 if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
970 LRegsMap.insert(std::make_pair(CurSU, LRegs));
973 CurSU->isPending = true; // This SU is not in AvailableQueue right now.
974 NotReady.push_back(CurSU);
975 CurSU = AvailableQueue->pop();
978 // All candidates are delayed due to live physical reg dependencies.
979 // Try backtracking, code duplication, or inserting cross class copies
981 if (Delayed && !CurSU) {
982 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
983 SUnit *TrySU = NotReady[i];
984 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
986 // Try unscheduling up to the point where it's safe to schedule
988 unsigned LiveCycle = CurCycle;
989 for (unsigned j = 0, ee = LRegs.size(); j != ee; ++j) {
990 unsigned Reg = LRegs[j];
991 unsigned LCycle = LiveRegCycles[Reg];
992 LiveCycle = std::min(LiveCycle, LCycle);
994 SUnit *OldSU = Sequence[LiveCycle];
995 if (!WillCreateCycle(TrySU, OldSU)) {
996 BacktrackBottomUp(TrySU, LiveCycle, CurCycle);
997 // Force the current node to be scheduled before the node that
998 // requires the physical reg dep.
999 if (OldSU->isAvailable) {
1000 OldSU->isAvailable = false;
1001 AvailableQueue->remove(OldSU);
1003 AddPred(TrySU, OldSU, true, true);
1004 // If one or more successors has been unscheduled, then the current
1005 // node is no longer avaialable. Schedule a successor that's now
1006 // available instead.
1007 if (!TrySU->isAvailable)
1008 CurSU = AvailableQueue->pop();
1011 TrySU->isPending = false;
1012 NotReady.erase(NotReady.begin()+i);
1019 // Can't backtrack. Try duplicating the nodes that produces these
1020 // "expensive to copy" values to break the dependency. In case even
1021 // that doesn't work, insert cross class copies.
1022 SUnit *TrySU = NotReady[0];
1023 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
1024 assert(LRegs.size() == 1 && "Can't handle this yet!");
1025 unsigned Reg = LRegs[0];
1026 SUnit *LRDef = LiveRegDefs[Reg];
1027 SUnit *NewDef = CopyAndMoveSuccessors(LRDef);
1029 // Issue expensive cross register class copies.
1030 MVT VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII);
1031 const TargetRegisterClass *RC =
1032 TRI->getPhysicalRegisterRegClass(Reg, VT);
1033 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
1035 assert(false && "Don't know how to copy this physical register!");
1038 SmallVector<SUnit*, 2> Copies;
1039 InsertCCCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
1040 DOUT << "Adding an edge from SU # " << TrySU->NodeNum
1041 << " to SU #" << Copies.front()->NodeNum << "\n";
1042 AddPred(TrySU, Copies.front(), true, true);
1043 NewDef = Copies.back();
1046 DOUT << "Adding an edge from SU # " << NewDef->NodeNum
1047 << " to SU #" << TrySU->NodeNum << "\n";
1048 LiveRegDefs[Reg] = NewDef;
1049 AddPred(NewDef, TrySU, true, true);
1050 TrySU->isAvailable = false;
1055 assert(false && "Unable to resolve live physical register dependencies!");
1060 // Add the nodes that aren't ready back onto the available list.
1061 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
1062 NotReady[i]->isPending = false;
1063 // May no longer be available due to backtracking.
1064 if (NotReady[i]->isAvailable)
1065 AvailableQueue->push(NotReady[i]);
1070 Sequence.push_back(0);
1072 ScheduleNodeBottomUp(CurSU, CurCycle);
1073 Sequence.push_back(CurSU);
1078 // Reverse the order if it is bottom up.
1079 std::reverse(Sequence.begin(), Sequence.end());
1083 // Verify that all SUnits were scheduled.
1084 bool AnyNotSched = false;
1085 unsigned DeadNodes = 0;
1087 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
1088 if (!SUnits[i].isScheduled) {
1089 if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) {
1094 cerr << "*** List scheduling failed! ***\n";
1095 SUnits[i].dump(&DAG);
1096 cerr << "has not been scheduled!\n";
1099 if (SUnits[i].NumSuccsLeft != 0) {
1101 cerr << "*** List scheduling failed! ***\n";
1102 SUnits[i].dump(&DAG);
1103 cerr << "has successors left!\n";
1107 for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
1110 assert(!AnyNotSched);
1111 assert(Sequence.size() + DeadNodes - Noops == SUnits.size() &&
1112 "The number of nodes scheduled doesn't match the expected number!");
1116 //===----------------------------------------------------------------------===//
1117 // Top-Down Scheduling
1118 //===----------------------------------------------------------------------===//
1120 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
1121 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
1122 void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain,
1123 unsigned CurCycle) {
1124 // FIXME: the distance between two nodes is not always == the predecessor's
1125 // latency. For example, the reader can very well read the register written
1126 // by the predecessor later than the issue cycle. It also depends on the
1127 // interrupt model (drain vs. freeze).
1128 SuccSU->CycleBound = std::max(SuccSU->CycleBound, CurCycle + SuccSU->Latency);
1130 --SuccSU->NumPredsLeft;
1133 if (SuccSU->NumPredsLeft < 0) {
1134 cerr << "*** List scheduling failed! ***\n";
1136 cerr << " has been released too many times!\n";
1141 if (SuccSU->NumPredsLeft == 0) {
1142 SuccSU->isAvailable = true;
1143 AvailableQueue->push(SuccSU);
1148 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
1149 /// count of its successors. If a successor pending count is zero, add it to
1150 /// the Available queue.
1151 void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
1152 DOUT << "*** Scheduling [" << CurCycle << "]: ";
1153 DEBUG(SU->dump(&DAG));
1154 SU->Cycle = CurCycle;
1156 AvailableQueue->ScheduledNode(SU);
1158 // Top down: release successors
1159 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1161 ReleaseSucc(I->Dep, I->isCtrl, CurCycle);
1162 SU->isScheduled = true;
1165 /// ListScheduleTopDown - The main loop of list scheduling for top-down
1167 void ScheduleDAGRRList::ListScheduleTopDown() {
1168 unsigned CurCycle = 0;
1170 // All leaves to Available queue.
1171 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
1172 // It is available if it has no predecessors.
1173 if (SUnits[i].Preds.empty()) {
1174 AvailableQueue->push(&SUnits[i]);
1175 SUnits[i].isAvailable = true;
1179 // While Available queue is not empty, grab the node with the highest
1180 // priority. If it is not ready put it back. Schedule the node.
1181 std::vector<SUnit*> NotReady;
1182 Sequence.reserve(SUnits.size());
1183 while (!AvailableQueue->empty()) {
1184 SUnit *CurSU = AvailableQueue->pop();
1185 while (CurSU && CurSU->CycleBound > CurCycle) {
1186 NotReady.push_back(CurSU);
1187 CurSU = AvailableQueue->pop();
1190 // Add the nodes that aren't ready back onto the available list.
1191 AvailableQueue->push_all(NotReady);
1195 Sequence.push_back(0);
1197 ScheduleNodeTopDown(CurSU, CurCycle);
1198 Sequence.push_back(CurSU);
1205 // Verify that all SUnits were scheduled.
1206 bool AnyNotSched = false;
1207 unsigned DeadNodes = 0;
1209 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
1210 if (!SUnits[i].isScheduled) {
1211 if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) {
1216 cerr << "*** List scheduling failed! ***\n";
1217 SUnits[i].dump(&DAG);
1218 cerr << "has not been scheduled!\n";
1221 if (SUnits[i].NumPredsLeft != 0) {
1223 cerr << "*** List scheduling failed! ***\n";
1224 SUnits[i].dump(&DAG);
1225 cerr << "has predecessors left!\n";
1229 for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
1232 assert(!AnyNotSched);
1233 assert(Sequence.size() + DeadNodes - Noops == SUnits.size() &&
1234 "The number of nodes scheduled doesn't match the expected number!");
1240 //===----------------------------------------------------------------------===//
1241 // RegReductionPriorityQueue Implementation
1242 //===----------------------------------------------------------------------===//
1244 // This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
1245 // to reduce register pressure.
1249 class RegReductionPriorityQueue;
1251 /// Sorting functions for the Available queue.
1252 struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
1253 RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ;
1254 bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {}
1255 bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
1257 bool operator()(const SUnit* left, const SUnit* right) const;
1260 struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
1261 RegReductionPriorityQueue<td_ls_rr_sort> *SPQ;
1262 td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {}
1263 td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
1265 bool operator()(const SUnit* left, const SUnit* right) const;
1267 } // end anonymous namespace
1269 static inline bool isCopyFromLiveIn(const SUnit *SU) {
1270 SDNode *N = SU->Node;
1271 return N && N->getOpcode() == ISD::CopyFromReg &&
1272 N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag;
1277 class VISIBILITY_HIDDEN RegReductionPriorityQueue
1278 : public SchedulingPriorityQueue {
1279 std::set<SUnit*, SF> Queue;
1280 unsigned currentQueueId;
1283 RegReductionPriorityQueue() :
1284 Queue(SF(this)), currentQueueId(0) {}
1286 virtual void initNodes(DenseMap<SDNode*, SUnit*> &sumap,
1287 std::vector<SUnit> &sunits) {}
1289 virtual void addNode(const SUnit *SU) {}
1291 virtual void updateNode(const SUnit *SU) {}
1293 virtual void releaseState() {}
1295 virtual unsigned getNodePriority(const SUnit *SU) const {
1299 unsigned size() const { return Queue.size(); }
1301 bool empty() const { return Queue.empty(); }
1303 void push(SUnit *U) {
1304 assert(!U->NodeQueueId && "Node in the queue already");
1305 U->NodeQueueId = ++currentQueueId;
1309 void push_all(const std::vector<SUnit *> &Nodes) {
1310 for (unsigned i = 0, e = Nodes.size(); i != e; ++i)
1315 if (empty()) return NULL;
1316 typename std::set<SUnit*, SF>::iterator i = prior(Queue.end());
1323 void remove(SUnit *SU) {
1324 assert(!Queue.empty() && "Queue is empty!");
1325 size_t RemovedNum = Queue.erase(SU);
1326 RemovedNum = RemovedNum; // Silence compiler warning.
1327 assert(RemovedNum > 0 && "Not in queue!");
1328 assert(RemovedNum == 1 && "Multiple times in the queue!");
1329 SU->NodeQueueId = 0;
1333 class VISIBILITY_HIDDEN BURegReductionPriorityQueue
1334 : public RegReductionPriorityQueue<bu_ls_rr_sort> {
1335 // SUnitMap SDNode to SUnit mapping (n -> n).
1336 DenseMap<SDNode*, SUnit*> *SUnitMap;
1338 // SUnits - The SUnits for the current graph.
1339 const std::vector<SUnit> *SUnits;
1341 // SethiUllmanNumbers - The SethiUllman number for each node.
1342 std::vector<unsigned> SethiUllmanNumbers;
1344 const TargetInstrInfo *TII;
1345 const TargetRegisterInfo *TRI;
1346 ScheduleDAGRRList *scheduleDAG;
1348 explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii,
1349 const TargetRegisterInfo *tri)
1350 : TII(tii), TRI(tri), scheduleDAG(NULL) {}
1352 void initNodes(DenseMap<SDNode*, SUnit*> &sumap,
1353 std::vector<SUnit> &sunits) {
1356 // Add pseudo dependency edges for two-address nodes.
1357 AddPseudoTwoAddrDeps();
1358 // Calculate node priorities.
1359 CalculateSethiUllmanNumbers();
1362 void addNode(const SUnit *SU) {
1363 SethiUllmanNumbers.resize(SUnits->size(), 0);
1364 CalcNodeSethiUllmanNumber(SU);
1367 void updateNode(const SUnit *SU) {
1368 SethiUllmanNumbers[SU->NodeNum] = 0;
1369 CalcNodeSethiUllmanNumber(SU);
1372 void releaseState() {
1374 SethiUllmanNumbers.clear();
1377 unsigned getNodePriority(const SUnit *SU) const {
1378 assert(SU->NodeNum < SethiUllmanNumbers.size());
1379 unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0;
1380 if (Opc == ISD::CopyFromReg && !isCopyFromLiveIn(SU))
1381 // CopyFromReg should be close to its def because it restricts
1382 // allocation choices. But if it is a livein then perhaps we want it
1383 // closer to its uses so it can be coalesced.
1385 else if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
1386 // CopyToReg should be close to its uses to facilitate coalescing and
1389 else if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
1390 Opc == TargetInstrInfo::INSERT_SUBREG)
1391 // EXTRACT_SUBREG / INSERT_SUBREG should be close to its use to
1392 // facilitate coalescing.
1394 else if (SU->NumSuccs == 0)
1395 // If SU does not have a use, i.e. it doesn't produce a value that would
1396 // be consumed (e.g. store), then it terminates a chain of computation.
1397 // Give it a large SethiUllman number so it will be scheduled right
1398 // before its predecessors that it doesn't lengthen their live ranges.
1400 else if (SU->NumPreds == 0)
1401 // If SU does not have a def, schedule it close to its uses because it
1402 // does not lengthen any live ranges.
1405 return SethiUllmanNumbers[SU->NodeNum];
1408 void setScheduleDAG(ScheduleDAGRRList *scheduleDag) {
1409 scheduleDAG = scheduleDag;
1413 bool canClobber(const SUnit *SU, const SUnit *Op);
1414 void AddPseudoTwoAddrDeps();
1415 void CalculateSethiUllmanNumbers();
1416 unsigned CalcNodeSethiUllmanNumber(const SUnit *SU);
1420 class VISIBILITY_HIDDEN TDRegReductionPriorityQueue
1421 : public RegReductionPriorityQueue<td_ls_rr_sort> {
1422 // SUnitMap SDNode to SUnit mapping (n -> n).
1423 DenseMap<SDNode*, SUnit*> *SUnitMap;
1425 // SUnits - The SUnits for the current graph.
1426 const std::vector<SUnit> *SUnits;
1428 // SethiUllmanNumbers - The SethiUllman number for each node.
1429 std::vector<unsigned> SethiUllmanNumbers;
1432 TDRegReductionPriorityQueue() {}
1434 void initNodes(DenseMap<SDNode*, SUnit*> &sumap,
1435 std::vector<SUnit> &sunits) {
1438 // Calculate node priorities.
1439 CalculateSethiUllmanNumbers();
1442 void addNode(const SUnit *SU) {
1443 SethiUllmanNumbers.resize(SUnits->size(), 0);
1444 CalcNodeSethiUllmanNumber(SU);
1447 void updateNode(const SUnit *SU) {
1448 SethiUllmanNumbers[SU->NodeNum] = 0;
1449 CalcNodeSethiUllmanNumber(SU);
1452 void releaseState() {
1454 SethiUllmanNumbers.clear();
1457 unsigned getNodePriority(const SUnit *SU) const {
1458 assert(SU->NodeNum < SethiUllmanNumbers.size());
1459 return SethiUllmanNumbers[SU->NodeNum];
1463 void CalculateSethiUllmanNumbers();
1464 unsigned CalcNodeSethiUllmanNumber(const SUnit *SU);
1468 /// closestSucc - Returns the scheduled cycle of the successor which is
1469 /// closet to the current cycle.
1470 static unsigned closestSucc(const SUnit *SU) {
1471 unsigned MaxCycle = 0;
1472 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1474 unsigned Cycle = I->Dep->Cycle;
1475 // If there are bunch of CopyToRegs stacked up, they should be considered
1476 // to be at the same position.
1477 if (I->Dep->Node && I->Dep->Node->getOpcode() == ISD::CopyToReg)
1478 Cycle = closestSucc(I->Dep)+1;
1479 if (Cycle > MaxCycle)
1485 /// calcMaxScratches - Returns an cost estimate of the worse case requirement
1486 /// for scratch registers. Live-in operands and live-out results don't count
1487 /// since they are "fixed".
1488 static unsigned calcMaxScratches(const SUnit *SU) {
1489 unsigned Scratches = 0;
1490 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1492 if (I->isCtrl) continue; // ignore chain preds
1493 if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyFromReg)
1496 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1498 if (I->isCtrl) continue; // ignore chain succs
1499 if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyToReg)
1506 bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
1508 unsigned LPriority = SPQ->getNodePriority(left);
1509 unsigned RPriority = SPQ->getNodePriority(right);
1510 if (LPriority != RPriority)
1511 return LPriority > RPriority;
1513 // Try schedule def + use closer when Sethi-Ullman numbers are the same.
1518 // and the following instructions are both ready.
1522 // Then schedule t2 = op first.
1529 // This creates more short live intervals.
1530 unsigned LDist = closestSucc(left);
1531 unsigned RDist = closestSucc(right);
1533 return LDist < RDist;
1535 // Intuitively, it's good to push down instructions whose results are
1536 // liveout so their long live ranges won't conflict with other values
1537 // which are needed inside the BB. Further prioritize liveout instructions
1538 // by the number of operands which are calculated within the BB.
1539 unsigned LScratch = calcMaxScratches(left);
1540 unsigned RScratch = calcMaxScratches(right);
1541 if (LScratch != RScratch)
1542 return LScratch > RScratch;
1544 if (left->Height != right->Height)
1545 return left->Height > right->Height;
1547 if (left->Depth != right->Depth)
1548 return left->Depth < right->Depth;
1550 if (left->CycleBound != right->CycleBound)
1551 return left->CycleBound > right->CycleBound;
1553 assert(left->NodeQueueId && right->NodeQueueId &&
1554 "NodeQueueId cannot be zero");
1555 return (left->NodeQueueId > right->NodeQueueId);
1559 BURegReductionPriorityQueue::canClobber(const SUnit *SU, const SUnit *Op) {
1560 if (SU->isTwoAddress) {
1561 unsigned Opc = SU->Node->getTargetOpcode();
1562 const TargetInstrDesc &TID = TII->get(Opc);
1563 unsigned NumRes = TID.getNumDefs();
1564 unsigned NumOps = TID.getNumOperands() - NumRes;
1565 for (unsigned i = 0; i != NumOps; ++i) {
1566 if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
1567 SDNode *DU = SU->Node->getOperand(i).Val;
1568 if ((*SUnitMap).find(DU) != (*SUnitMap).end() &&
1569 Op->OrigNode == (*SUnitMap)[DU])
1578 /// hasCopyToRegUse - Return true if SU has a value successor that is a
1580 static bool hasCopyToRegUse(SUnit *SU) {
1581 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1583 if (I->isCtrl) continue;
1584 SUnit *SuccSU = I->Dep;
1585 if (SuccSU->Node && SuccSU->Node->getOpcode() == ISD::CopyToReg)
1591 /// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's
1592 /// physical register def.
1593 static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU,
1594 const TargetInstrInfo *TII,
1595 const TargetRegisterInfo *TRI) {
1596 SDNode *N = SuccSU->Node;
1597 unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs();
1598 const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs();
1601 const unsigned *SUImpDefs =
1602 TII->get(SU->Node->getTargetOpcode()).getImplicitDefs();
1605 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
1606 MVT VT = N->getValueType(i);
1607 if (VT == MVT::Flag || VT == MVT::Other)
1609 unsigned Reg = ImpDefs[i - NumDefs];
1610 for (;*SUImpDefs; ++SUImpDefs) {
1611 unsigned SUReg = *SUImpDefs;
1612 if (TRI->regsOverlap(Reg, SUReg))
1619 /// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
1620 /// it as a def&use operand. Add a pseudo control edge from it to the other
1621 /// node (if it won't create a cycle) so the two-address one will be scheduled
1622 /// first (lower in the schedule). If both nodes are two-address, favor the
1623 /// one that has a CopyToReg use (more likely to be a loop induction update).
1624 /// If both are two-address, but one is commutable while the other is not
1625 /// commutable, favor the one that's not commutable.
1626 void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() {
1627 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
1628 SUnit *SU = (SUnit *)&((*SUnits)[i]);
1629 if (!SU->isTwoAddress)
1632 SDNode *Node = SU->Node;
1633 if (!Node || !Node->isTargetOpcode() || SU->FlaggedNodes.size() > 0)
1636 unsigned Opc = Node->getTargetOpcode();
1637 const TargetInstrDesc &TID = TII->get(Opc);
1638 unsigned NumRes = TID.getNumDefs();
1639 unsigned NumOps = TID.getNumOperands() - NumRes;
1640 for (unsigned j = 0; j != NumOps; ++j) {
1641 if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) {
1642 SDNode *DU = SU->Node->getOperand(j).Val;
1643 if ((*SUnitMap).find(DU) == (*SUnitMap).end())
1645 SUnit *DUSU = (*SUnitMap)[DU];
1646 if (!DUSU) continue;
1647 for (SUnit::succ_iterator I = DUSU->Succs.begin(),E = DUSU->Succs.end();
1649 if (I->isCtrl) continue;
1650 SUnit *SuccSU = I->Dep;
1653 // Be conservative. Ignore if nodes aren't at roughly the same
1654 // depth and height.
1655 if (SuccSU->Height < SU->Height && (SU->Height - SuccSU->Height) > 1)
1657 if (!SuccSU->Node || !SuccSU->Node->isTargetOpcode())
1659 // Don't constrain nodes with physical register defs if the
1660 // predecessor can clobber them.
1661 if (SuccSU->hasPhysRegDefs) {
1662 if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
1665 // Don't constraint extract_subreg / insert_subreg these may be
1666 // coalesced away. We don't them close to their uses.
1667 unsigned SuccOpc = SuccSU->Node->getTargetOpcode();
1668 if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG ||
1669 SuccOpc == TargetInstrInfo::INSERT_SUBREG)
1671 if ((!canClobber(SuccSU, DUSU) ||
1672 (hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) ||
1673 (!SU->isCommutable && SuccSU->isCommutable)) &&
1674 !scheduleDAG->IsReachable(SuccSU, SU)) {
1675 DOUT << "Adding an edge from SU # " << SU->NodeNum
1676 << " to SU #" << SuccSU->NodeNum << "\n";
1677 scheduleDAG->AddPred(SU, SuccSU, true, true);
1685 /// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
1686 /// Smaller number is the higher priority.
1687 unsigned BURegReductionPriorityQueue::
1688 CalcNodeSethiUllmanNumber(const SUnit *SU) {
1689 unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
1690 if (SethiUllmanNumber != 0)
1691 return SethiUllmanNumber;
1694 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1696 if (I->isCtrl) continue; // ignore chain preds
1697 SUnit *PredSU = I->Dep;
1698 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU);
1699 if (PredSethiUllman > SethiUllmanNumber) {
1700 SethiUllmanNumber = PredSethiUllman;
1702 } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl)
1706 SethiUllmanNumber += Extra;
1708 if (SethiUllmanNumber == 0)
1709 SethiUllmanNumber = 1;
1711 return SethiUllmanNumber;
1714 /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
1715 /// scheduling units.
1716 void BURegReductionPriorityQueue::CalculateSethiUllmanNumbers() {
1717 SethiUllmanNumbers.assign(SUnits->size(), 0);
1719 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
1720 CalcNodeSethiUllmanNumber(&(*SUnits)[i]);
1723 /// LimitedSumOfUnscheduledPredsOfSuccs - Compute the sum of the unscheduled
1724 /// predecessors of the successors of the SUnit SU. Stop when the provided
1725 /// limit is exceeded.
1726 static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU,
1729 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1731 SUnit *SuccSU = I->Dep;
1732 for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(),
1733 EE = SuccSU->Preds.end(); II != EE; ++II) {
1734 SUnit *PredSU = II->Dep;
1735 if (!PredSU->isScheduled)
1745 bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
1746 unsigned LPriority = SPQ->getNodePriority(left);
1747 unsigned RPriority = SPQ->getNodePriority(right);
1748 bool LIsTarget = left->Node && left->Node->isTargetOpcode();
1749 bool RIsTarget = right->Node && right->Node->isTargetOpcode();
1750 bool LIsFloater = LIsTarget && left->NumPreds == 0;
1751 bool RIsFloater = RIsTarget && right->NumPreds == 0;
1752 unsigned LBonus = (LimitedSumOfUnscheduledPredsOfSuccs(left,1) == 1) ? 2 : 0;
1753 unsigned RBonus = (LimitedSumOfUnscheduledPredsOfSuccs(right,1) == 1) ? 2 : 0;
1755 if (left->NumSuccs == 0 && right->NumSuccs != 0)
1757 else if (left->NumSuccs != 0 && right->NumSuccs == 0)
1764 if (left->NumSuccs == 1)
1766 if (right->NumSuccs == 1)
1769 if (LPriority+LBonus != RPriority+RBonus)
1770 return LPriority+LBonus < RPriority+RBonus;
1772 if (left->Depth != right->Depth)
1773 return left->Depth < right->Depth;
1775 if (left->NumSuccsLeft != right->NumSuccsLeft)
1776 return left->NumSuccsLeft > right->NumSuccsLeft;
1778 if (left->CycleBound != right->CycleBound)
1779 return left->CycleBound > right->CycleBound;
1781 assert(left->NodeQueueId && right->NodeQueueId &&
1782 "NodeQueueId cannot be zero");
1783 return (left->NodeQueueId > right->NodeQueueId);
1786 /// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
1787 /// Smaller number is the higher priority.
1788 unsigned TDRegReductionPriorityQueue::
1789 CalcNodeSethiUllmanNumber(const SUnit *SU) {
1790 unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
1791 if (SethiUllmanNumber != 0)
1792 return SethiUllmanNumber;
1794 unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0;
1795 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
1796 SethiUllmanNumber = 0xffff;
1797 else if (SU->NumSuccsLeft == 0)
1798 // If SU does not have a use, i.e. it doesn't produce a value that would
1799 // be consumed (e.g. store), then it terminates a chain of computation.
1800 // Give it a small SethiUllman number so it will be scheduled right before
1801 // its predecessors that it doesn't lengthen their live ranges.
1802 SethiUllmanNumber = 0;
1803 else if (SU->NumPredsLeft == 0 &&
1804 (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
1805 SethiUllmanNumber = 0xffff;
1808 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1810 if (I->isCtrl) continue; // ignore chain preds
1811 SUnit *PredSU = I->Dep;
1812 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU);
1813 if (PredSethiUllman > SethiUllmanNumber) {
1814 SethiUllmanNumber = PredSethiUllman;
1816 } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl)
1820 SethiUllmanNumber += Extra;
1823 return SethiUllmanNumber;
1826 /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
1827 /// scheduling units.
1828 void TDRegReductionPriorityQueue::CalculateSethiUllmanNumbers() {
1829 SethiUllmanNumbers.assign(SUnits->size(), 0);
1831 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
1832 CalcNodeSethiUllmanNumber(&(*SUnits)[i]);
1835 //===----------------------------------------------------------------------===//
1836 // Public Constructor Functions
1837 //===----------------------------------------------------------------------===//
1839 llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
1841 MachineBasicBlock *BB) {
1842 const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo();
1843 const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo();
1845 BURegReductionPriorityQueue *priorityQueue =
1846 new BURegReductionPriorityQueue(TII, TRI);
1848 ScheduleDAGRRList * scheduleDAG =
1849 new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, priorityQueue);
1850 priorityQueue->setScheduleDAG(scheduleDAG);
1854 llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
1856 MachineBasicBlock *BB) {
1857 return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false,
1858 new TDRegReductionPriorityQueue());