1 //===----- ScheduleDAGList.cpp - Reg pressure reduction list scheduler ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements bottom-up and top-down register pressure reduction list
11 // schedulers, using standard algorithms. The basic approach uses a priority
12 // queue of available nodes to schedule. One at a time, nodes are taken from
13 // the priority queue (thus in priority order), checked for legality to
14 // schedule, and emitted if legal.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "pre-RA-sched"
19 #include "llvm/CodeGen/ScheduleDAG.h"
20 #include "llvm/CodeGen/SchedulerRegistry.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/Compiler.h"
27 #include "llvm/ADT/BitVector.h"
28 #include "llvm/ADT/PriorityQueue.h"
29 #include "llvm/ADT/SmallPtrSet.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/Support/CommandLine.h"
37 STATISTIC(NumBacktracks, "Number of times scheduler backtracked");
38 STATISTIC(NumUnfolds, "Number of nodes unfolded");
39 STATISTIC(NumDups, "Number of duplicated nodes");
40 STATISTIC(NumCCCopies, "Number of cross class copies");
42 static RegisterScheduler
43 burrListDAGScheduler("list-burr",
44 " Bottom-up register reduction list scheduling",
45 createBURRListDAGScheduler);
46 static RegisterScheduler
47 tdrListrDAGScheduler("list-tdrr",
48 " Top-down register reduction list scheduling",
49 createTDRRListDAGScheduler);
52 //===----------------------------------------------------------------------===//
53 /// ScheduleDAGRRList - The actual register reduction list scheduler
54 /// implementation. This supports both top-down and bottom-up scheduling.
56 class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAG {
58 /// isBottomUp - This is true if the scheduling problem is bottom-up, false if
62 /// AvailableQueue - The priority queue to use for the available SUnits.
63 SchedulingPriorityQueue *AvailableQueue;
65 /// LiveRegs / LiveRegDefs - A set of physical registers and their definition
66 /// that are "live". These nodes must be scheduled before any other nodes that
67 /// modifies the registers can be scheduled.
68 SmallSet<unsigned, 4> LiveRegs;
69 std::vector<SUnit*> LiveRegDefs;
70 std::vector<unsigned> LiveRegCycles;
73 ScheduleDAGRRList(SelectionDAG &dag, MachineBasicBlock *bb,
74 const TargetMachine &tm, bool isbottomup,
75 SchedulingPriorityQueue *availqueue)
76 : ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup),
77 AvailableQueue(availqueue) {
80 ~ScheduleDAGRRList() {
81 delete AvailableQueue;
86 /// IsReachable - Checks if SU is reachable from TargetSU.
87 bool IsReachable(SUnit *SU, SUnit *TargetSU);
89 /// willCreateCycle - Returns true if adding an edge from SU to TargetSU will
91 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
93 /// AddPred - This adds the specified node X as a predecessor of
94 /// the current node Y if not already.
95 /// This returns true if this is a new predecessor.
96 /// Updates the topological ordering if required.
97 bool AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial,
98 unsigned PhyReg = 0, int Cost = 1);
100 /// RemovePred - This removes the specified node N from the predecessors of
101 /// the current node M. Updates the topological ordering if required.
102 bool RemovePred(SUnit *M, SUnit *N, bool isCtrl, bool isSpecial);
105 void ReleasePred(SUnit*, bool, unsigned);
106 void ReleaseSucc(SUnit*, bool isChain, unsigned);
107 void CapturePred(SUnit*, SUnit*, bool);
108 void ScheduleNodeBottomUp(SUnit*, unsigned);
109 void ScheduleNodeTopDown(SUnit*, unsigned);
110 void UnscheduleNodeBottomUp(SUnit*);
111 void BacktrackBottomUp(SUnit*, unsigned, unsigned&);
112 SUnit *CopyAndMoveSuccessors(SUnit*);
113 void InsertCCCopiesAndMoveSuccs(SUnit*, unsigned,
114 const TargetRegisterClass*,
115 const TargetRegisterClass*,
116 SmallVector<SUnit*, 2>&);
117 bool DelayForLiveRegsBottomUp(SUnit*, SmallVector<unsigned, 4>&);
118 void ListScheduleTopDown();
119 void ListScheduleBottomUp();
120 void CommuteNodesToReducePressure();
123 /// CreateNewSUnit - Creates a new SUnit and returns a pointer to it.
124 /// Updates the topological ordering if required.
125 SUnit *CreateNewSUnit(SDNode *N) {
126 SUnit *NewNode = NewSUnit(N);
127 // Update the topological ordering.
128 if (NewNode->NodeNum >= Node2Index.size())
129 InitDAGTopologicalSorting();
133 /// CreateClone - Creates a new SUnit from an existing one.
134 /// Updates the topological ordering if required.
135 SUnit *CreateClone(SUnit *N) {
136 SUnit *NewNode = Clone(N);
137 // Update the topological ordering.
138 if (NewNode->NodeNum >= Node2Index.size())
139 InitDAGTopologicalSorting();
143 /// Functions for preserving the topological ordering
144 /// even after dynamic insertions of new edges.
145 /// This allows a very fast implementation of IsReachable.
149 The idea of the algorithm is taken from
150 "Online algorithms for managing the topological order of
151 a directed acyclic graph" by David J. Pearce and Paul H.J. Kelly
152 This is the MNR algorithm, which was first introduced by
153 A. Marchetti-Spaccamela, U. Nanni and H. Rohnert in
154 "Maintaining a topological order under edge insertions".
156 Short description of the algorithm:
158 Topological ordering, ord, of a DAG maps each node to a topological
159 index so that for all edges X->Y it is the case that ord(X) < ord(Y).
161 This means that if there is a path from the node X to the node Z,
162 then ord(X) < ord(Z).
164 This property can be used to check for reachability of nodes:
165 if Z is reachable from X, then an insertion of the edge Z->X would
168 The algorithm first computes a topological ordering for the DAG by initializing
169 the Index2Node and Node2Index arrays and then tries to keep the ordering
170 up-to-date after edge insertions by reordering the DAG.
172 On insertion of the edge X->Y, the algorithm first marks by calling DFS the
173 nodes reachable from Y, and then shifts them using Shift to lie immediately
174 after X in Index2Node.
177 /// InitDAGTopologicalSorting - create the initial topological
178 /// ordering from the DAG to be scheduled.
179 void InitDAGTopologicalSorting();
181 /// DFS - make a DFS traversal and mark all nodes affected by the
182 /// edge insertion. These nodes will later get new topological indexes
183 /// by means of the Shift method.
184 void DFS(SUnit *SU, int UpperBound, bool& HasLoop);
186 /// Shift - reassign topological indexes for the nodes in the DAG
187 /// to preserve the topological ordering.
188 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
190 /// Allocate - assign the topological index to the node n.
191 void Allocate(int n, int index);
193 /// Index2Node - Maps topological index to the node number.
194 std::vector<int> Index2Node;
195 /// Node2Index - Maps the node number to its topological index.
196 std::vector<int> Node2Index;
197 /// Visited - a set of nodes visited during a DFS traversal.
200 } // end anonymous namespace
203 /// Schedule - Schedule the DAG using list scheduling.
204 void ScheduleDAGRRList::Schedule() {
205 DOUT << "********** List Scheduling **********\n";
207 LiveRegDefs.resize(TRI->getNumRegs(), NULL);
208 LiveRegCycles.resize(TRI->getNumRegs(), 0);
210 // Build scheduling units.
213 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
214 SUnits[su].dumpAll(&DAG));
217 InitDAGTopologicalSorting();
219 AvailableQueue->initNodes(SUnits);
221 // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
223 ListScheduleBottomUp();
225 ListScheduleTopDown();
227 AvailableQueue->releaseState();
229 CommuteNodesToReducePressure();
231 DOUT << "*** Final schedule ***\n";
232 DEBUG(dumpSchedule());
235 // Emit in scheduled order
239 /// CommuteNodesToReducePressure - If a node is two-address and commutable, and
240 /// it is not the last use of its first operand, add it to the CommuteSet if
241 /// possible. It will be commuted when it is translated to a MI.
242 void ScheduleDAGRRList::CommuteNodesToReducePressure() {
243 SmallPtrSet<SUnit*, 4> OperandSeen;
244 for (unsigned i = Sequence.size(); i != 0; ) {
246 SUnit *SU = Sequence[i];
247 if (!SU || !SU->Node) continue;
248 if (SU->isCommutable) {
249 unsigned Opc = SU->Node->getTargetOpcode();
250 const TargetInstrDesc &TID = TII->get(Opc);
251 unsigned NumRes = TID.getNumDefs();
252 unsigned NumOps = TID.getNumOperands() - NumRes;
253 for (unsigned j = 0; j != NumOps; ++j) {
254 if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1)
257 SDNode *OpN = SU->Node->getOperand(j).Val;
258 SUnit *OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()];
259 if (OpSU && OperandSeen.count(OpSU) == 1) {
260 // Ok, so SU is not the last use of OpSU, but SU is two-address so
261 // it will clobber OpSU. Try to commute SU if no other source operands
263 bool DoCommute = true;
264 for (unsigned k = 0; k < NumOps; ++k) {
266 OpN = SU->Node->getOperand(k).Val;
267 OpSU = isPassiveNode(OpN) ? NULL : &SUnits[OpN->getNodeId()];
268 if (OpSU && OperandSeen.count(OpSU) == 1) {
275 CommuteSet.insert(SU->Node);
278 // Only look at the first use&def node for now.
283 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
286 OperandSeen.insert(I->Dep->OrigNode);
291 //===----------------------------------------------------------------------===//
292 // Bottom-Up Scheduling
293 //===----------------------------------------------------------------------===//
295 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
296 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
297 void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
299 // FIXME: the distance between two nodes is not always == the predecessor's
300 // latency. For example, the reader can very well read the register written
301 // by the predecessor later than the issue cycle. It also depends on the
302 // interrupt model (drain vs. freeze).
303 PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency);
305 --PredSU->NumSuccsLeft;
308 if (PredSU->NumSuccsLeft < 0) {
309 cerr << "*** List scheduling failed! ***\n";
311 cerr << " has been released too many times!\n";
316 if (PredSU->NumSuccsLeft == 0) {
317 PredSU->isAvailable = true;
318 AvailableQueue->push(PredSU);
322 /// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
323 /// count of its predecessors. If a predecessor pending count is zero, add it to
324 /// the Available queue.
325 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
326 DOUT << "*** Scheduling [" << CurCycle << "]: ";
327 DEBUG(SU->dump(&DAG));
328 SU->Cycle = CurCycle;
330 AvailableQueue->ScheduledNode(SU);
332 // Bottom up: release predecessors
333 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
335 ReleasePred(I->Dep, I->isCtrl, CurCycle);
337 // This is a physical register dependency and it's impossible or
338 // expensive to copy the register. Make sure nothing that can
339 // clobber the register is scheduled between the predecessor and
341 if (LiveRegs.insert(I->Reg)) {
342 LiveRegDefs[I->Reg] = I->Dep;
343 LiveRegCycles[I->Reg] = CurCycle;
348 // Release all the implicit physical register defs that are live.
349 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
352 if (LiveRegCycles[I->Reg] == I->Dep->Cycle) {
353 LiveRegs.erase(I->Reg);
354 assert(LiveRegDefs[I->Reg] == SU &&
355 "Physical register dependency violated?");
356 LiveRegDefs[I->Reg] = NULL;
357 LiveRegCycles[I->Reg] = 0;
362 SU->isScheduled = true;
365 /// CapturePred - This does the opposite of ReleasePred. Since SU is being
366 /// unscheduled, incrcease the succ left count of its predecessors. Remove
367 /// them from AvailableQueue if necessary.
368 void ScheduleDAGRRList::CapturePred(SUnit *PredSU, SUnit *SU, bool isChain) {
369 unsigned CycleBound = 0;
370 for (SUnit::succ_iterator I = PredSU->Succs.begin(), E = PredSU->Succs.end();
374 CycleBound = std::max(CycleBound,
375 I->Dep->Cycle + PredSU->Latency);
378 if (PredSU->isAvailable) {
379 PredSU->isAvailable = false;
380 if (!PredSU->isPending)
381 AvailableQueue->remove(PredSU);
384 PredSU->CycleBound = CycleBound;
385 ++PredSU->NumSuccsLeft;
388 /// UnscheduleNodeBottomUp - Remove the node from the schedule, update its and
389 /// its predecessor states to reflect the change.
390 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) {
391 DOUT << "*** Unscheduling [" << SU->Cycle << "]: ";
392 DEBUG(SU->dump(&DAG));
394 AvailableQueue->UnscheduledNode(SU);
396 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
398 CapturePred(I->Dep, SU, I->isCtrl);
399 if (I->Cost < 0 && SU->Cycle == LiveRegCycles[I->Reg]) {
400 LiveRegs.erase(I->Reg);
401 assert(LiveRegDefs[I->Reg] == I->Dep &&
402 "Physical register dependency violated?");
403 LiveRegDefs[I->Reg] = NULL;
404 LiveRegCycles[I->Reg] = 0;
408 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
411 if (LiveRegs.insert(I->Reg)) {
412 assert(!LiveRegDefs[I->Reg] &&
413 "Physical register dependency violated?");
414 LiveRegDefs[I->Reg] = SU;
416 if (I->Dep->Cycle < LiveRegCycles[I->Reg])
417 LiveRegCycles[I->Reg] = I->Dep->Cycle;
422 SU->isScheduled = false;
423 SU->isAvailable = true;
424 AvailableQueue->push(SU);
427 /// IsReachable - Checks if SU is reachable from TargetSU.
428 bool ScheduleDAGRRList::IsReachable(SUnit *SU, SUnit *TargetSU) {
429 // If insertion of the edge SU->TargetSU would create a cycle
430 // then there is a path from TargetSU to SU.
431 int UpperBound, LowerBound;
432 LowerBound = Node2Index[TargetSU->NodeNum];
433 UpperBound = Node2Index[SU->NodeNum];
434 bool HasLoop = false;
435 // Is Ord(TargetSU) < Ord(SU) ?
436 if (LowerBound < UpperBound) {
438 // There may be a path from TargetSU to SU. Check for it.
439 DFS(TargetSU, UpperBound, HasLoop);
444 /// Allocate - assign the topological index to the node n.
445 inline void ScheduleDAGRRList::Allocate(int n, int index) {
446 Node2Index[n] = index;
447 Index2Node[index] = n;
450 /// InitDAGTopologicalSorting - create the initial topological
451 /// ordering from the DAG to be scheduled.
452 void ScheduleDAGRRList::InitDAGTopologicalSorting() {
453 unsigned DAGSize = SUnits.size();
454 std::vector<unsigned> InDegree(DAGSize);
455 std::vector<SUnit*> WorkList;
456 WorkList.reserve(DAGSize);
457 std::vector<SUnit*> TopOrder;
458 TopOrder.reserve(DAGSize);
460 // Initialize the data structures.
461 for (unsigned i = 0, e = DAGSize; i != e; ++i) {
462 SUnit *SU = &SUnits[i];
463 int NodeNum = SU->NodeNum;
464 unsigned Degree = SU->Succs.size();
465 InDegree[NodeNum] = Degree;
467 // Is it a node without dependencies?
469 assert(SU->Succs.empty() && "SUnit should have no successors");
470 // Collect leaf nodes.
471 WorkList.push_back(SU);
475 while (!WorkList.empty()) {
476 SUnit *SU = WorkList.back();
478 TopOrder.push_back(SU);
479 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
482 if (!--InDegree[SU->NodeNum])
483 // If all dependencies of the node are processed already,
484 // then the node can be computed now.
485 WorkList.push_back(SU);
489 // Second pass, assign the actual topological order as node ids.
494 Index2Node.resize(DAGSize);
495 Node2Index.resize(DAGSize);
496 Visited.resize(DAGSize);
498 for (std::vector<SUnit*>::reverse_iterator TI = TopOrder.rbegin(),
499 TE = TopOrder.rend();TI != TE; ++TI) {
500 Allocate((*TI)->NodeNum, Id);
505 // Check correctness of the ordering
506 for (unsigned i = 0, e = DAGSize; i != e; ++i) {
507 SUnit *SU = &SUnits[i];
508 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
510 assert(Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] &&
511 "Wrong topological sorting");
517 /// AddPred - adds an edge from SUnit X to SUnit Y.
518 /// Updates the topological ordering if required.
519 bool ScheduleDAGRRList::AddPred(SUnit *Y, SUnit *X, bool isCtrl, bool isSpecial,
520 unsigned PhyReg, int Cost) {
521 int UpperBound, LowerBound;
522 LowerBound = Node2Index[Y->NodeNum];
523 UpperBound = Node2Index[X->NodeNum];
524 bool HasLoop = false;
525 // Is Ord(X) < Ord(Y) ?
526 if (LowerBound < UpperBound) {
527 // Update the topological order.
529 DFS(Y, UpperBound, HasLoop);
530 assert(!HasLoop && "Inserted edge creates a loop!");
531 // Recompute topological indexes.
532 Shift(Visited, LowerBound, UpperBound);
534 // Now really insert the edge.
535 return Y->addPred(X, isCtrl, isSpecial, PhyReg, Cost);
538 /// RemovePred - This removes the specified node N from the predecessors of
539 /// the current node M. Updates the topological ordering if required.
540 bool ScheduleDAGRRList::RemovePred(SUnit *M, SUnit *N,
541 bool isCtrl, bool isSpecial) {
542 // InitDAGTopologicalSorting();
543 return M->removePred(N, isCtrl, isSpecial);
546 /// DFS - Make a DFS traversal to mark all nodes reachable from SU and mark
547 /// all nodes affected by the edge insertion. These nodes will later get new
548 /// topological indexes by means of the Shift method.
549 void ScheduleDAGRRList::DFS(SUnit *SU, int UpperBound, bool& HasLoop) {
550 std::vector<SUnit*> WorkList;
551 WorkList.reserve(SUnits.size());
553 WorkList.push_back(SU);
554 while (!WorkList.empty()) {
555 SU = WorkList.back();
557 Visited.set(SU->NodeNum);
558 for (int I = SU->Succs.size()-1; I >= 0; --I) {
559 int s = SU->Succs[I].Dep->NodeNum;
560 if (Node2Index[s] == UpperBound) {
564 // Visit successors if not already and in affected region.
565 if (!Visited.test(s) && Node2Index[s] < UpperBound) {
566 WorkList.push_back(SU->Succs[I].Dep);
572 /// Shift - Renumber the nodes so that the topological ordering is
574 void ScheduleDAGRRList::Shift(BitVector& Visited, int LowerBound,
580 for (i = LowerBound; i <= UpperBound; ++i) {
581 // w is node at topological index i.
582 int w = Index2Node[i];
583 if (Visited.test(w)) {
589 Allocate(w, i - shift);
593 for (unsigned j = 0; j < L.size(); ++j) {
594 Allocate(L[j], i - shift);
600 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
602 bool ScheduleDAGRRList::WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
603 if (IsReachable(TargetSU, SU))
605 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
607 if (I->Cost < 0 && IsReachable(TargetSU, I->Dep))
612 /// BacktrackBottomUp - Backtrack scheduling to a previous cycle specified in
613 /// BTCycle in order to schedule a specific node. Returns the last unscheduled
614 /// SUnit. Also returns if a successor is unscheduled in the process.
615 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, unsigned BtCycle,
616 unsigned &CurCycle) {
618 while (CurCycle > BtCycle) {
619 OldSU = Sequence.back();
621 if (SU->isSucc(OldSU))
622 // Don't try to remove SU from AvailableQueue.
623 SU->isAvailable = false;
624 UnscheduleNodeBottomUp(OldSU);
629 if (SU->isSucc(OldSU)) {
630 assert(false && "Something is wrong!");
637 /// CopyAndMoveSuccessors - Clone the specified node and move its scheduled
638 /// successors to the newly created node.
639 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) {
640 if (SU->FlaggedNodes.size())
643 SDNode *N = SU->Node;
648 bool TryUnfold = false;
649 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
650 MVT VT = N->getValueType(i);
653 else if (VT == MVT::Other)
656 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
657 const SDOperand &Op = N->getOperand(i);
658 MVT VT = Op.Val->getValueType(Op.ResNo);
664 SmallVector<SDNode*, 2> NewNodes;
665 if (!TII->unfoldMemoryOperand(DAG, N, NewNodes))
668 DOUT << "Unfolding SU # " << SU->NodeNum << "\n";
669 assert(NewNodes.size() == 2 && "Expected a load folding node!");
672 SDNode *LoadNode = NewNodes[0];
673 unsigned NumVals = N->getNumValues();
674 unsigned OldNumVals = SU->Node->getNumValues();
675 for (unsigned i = 0; i != NumVals; ++i)
676 DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, i), SDOperand(N, i));
677 DAG.ReplaceAllUsesOfValueWith(SDOperand(SU->Node, OldNumVals-1),
678 SDOperand(LoadNode, 1));
680 SUnit *NewSU = CreateNewSUnit(N);
681 assert(N->getNodeId() == -1 && "Node already inserted!");
682 N->setNodeId(NewSU->NodeNum);
684 const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
685 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
686 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
687 NewSU->isTwoAddress = true;
691 if (TID.isCommutable())
692 NewSU->isCommutable = true;
693 // FIXME: Calculate height / depth and propagate the changes?
694 NewSU->Depth = SU->Depth;
695 NewSU->Height = SU->Height;
696 ComputeLatency(NewSU);
698 // LoadNode may already exist. This can happen when there is another
699 // load from the same location and producing the same type of value
700 // but it has different alignment or volatileness.
701 bool isNewLoad = true;
703 if (LoadNode->getNodeId() != -1) {
704 LoadSU = &SUnits[LoadNode->getNodeId()];
707 LoadSU = CreateNewSUnit(LoadNode);
708 LoadNode->setNodeId(LoadSU->NodeNum);
710 LoadSU->Depth = SU->Depth;
711 LoadSU->Height = SU->Height;
712 ComputeLatency(LoadSU);
715 SUnit *ChainPred = NULL;
716 SmallVector<SDep, 4> ChainSuccs;
717 SmallVector<SDep, 4> LoadPreds;
718 SmallVector<SDep, 4> NodePreds;
719 SmallVector<SDep, 4> NodeSuccs;
720 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
724 else if (I->Dep->Node && I->Dep->Node->isOperandOf(LoadNode))
725 LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false));
727 NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false));
729 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
732 ChainSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost,
733 I->isCtrl, I->isSpecial));
735 NodeSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost,
736 I->isCtrl, I->isSpecial));
740 RemovePred(SU, ChainPred, true, false);
742 AddPred(LoadSU, ChainPred, true, false);
744 for (unsigned i = 0, e = LoadPreds.size(); i != e; ++i) {
745 SDep *Pred = &LoadPreds[i];
746 RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial);
748 AddPred(LoadSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial,
749 Pred->Reg, Pred->Cost);
752 for (unsigned i = 0, e = NodePreds.size(); i != e; ++i) {
753 SDep *Pred = &NodePreds[i];
754 RemovePred(SU, Pred->Dep, Pred->isCtrl, Pred->isSpecial);
755 AddPred(NewSU, Pred->Dep, Pred->isCtrl, Pred->isSpecial,
756 Pred->Reg, Pred->Cost);
758 for (unsigned i = 0, e = NodeSuccs.size(); i != e; ++i) {
759 SDep *Succ = &NodeSuccs[i];
760 RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial);
761 AddPred(Succ->Dep, NewSU, Succ->isCtrl, Succ->isSpecial,
762 Succ->Reg, Succ->Cost);
764 for (unsigned i = 0, e = ChainSuccs.size(); i != e; ++i) {
765 SDep *Succ = &ChainSuccs[i];
766 RemovePred(Succ->Dep, SU, Succ->isCtrl, Succ->isSpecial);
768 AddPred(Succ->Dep, LoadSU, Succ->isCtrl, Succ->isSpecial,
769 Succ->Reg, Succ->Cost);
773 AddPred(NewSU, LoadSU, false, false);
777 AvailableQueue->addNode(LoadSU);
778 AvailableQueue->addNode(NewSU);
782 if (NewSU->NumSuccsLeft == 0) {
783 NewSU->isAvailable = true;
789 DOUT << "Duplicating SU # " << SU->NodeNum << "\n";
790 NewSU = CreateClone(SU);
792 // New SUnit has the exact same predecessors.
793 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
796 AddPred(NewSU, I->Dep, I->isCtrl, false, I->Reg, I->Cost);
797 NewSU->Depth = std::max(NewSU->Depth, I->Dep->Depth+1);
800 // Only copy scheduled successors. Cut them from old node's successor
801 // list and move them over.
802 SmallVector<std::pair<SUnit*, bool>, 4> DelDeps;
803 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
807 if (I->Dep->isScheduled) {
808 NewSU->Height = std::max(NewSU->Height, I->Dep->Height+1);
809 AddPred(I->Dep, NewSU, I->isCtrl, false, I->Reg, I->Cost);
810 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
813 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
814 SUnit *Succ = DelDeps[i].first;
815 bool isCtrl = DelDeps[i].second;
816 RemovePred(Succ, SU, isCtrl, false);
819 AvailableQueue->updateNode(SU);
820 AvailableQueue->addNode(NewSU);
826 /// InsertCCCopiesAndMoveSuccs - Insert expensive cross register class copies
827 /// and move all scheduled successors of the given SUnit to the last copy.
828 void ScheduleDAGRRList::InsertCCCopiesAndMoveSuccs(SUnit *SU, unsigned Reg,
829 const TargetRegisterClass *DestRC,
830 const TargetRegisterClass *SrcRC,
831 SmallVector<SUnit*, 2> &Copies) {
832 SUnit *CopyFromSU = CreateNewSUnit(NULL);
833 CopyFromSU->CopySrcRC = SrcRC;
834 CopyFromSU->CopyDstRC = DestRC;
835 CopyFromSU->Depth = SU->Depth;
836 CopyFromSU->Height = SU->Height;
838 SUnit *CopyToSU = CreateNewSUnit(NULL);
839 CopyToSU->CopySrcRC = DestRC;
840 CopyToSU->CopyDstRC = SrcRC;
842 // Only copy scheduled successors. Cut them from old node's successor
843 // list and move them over.
844 SmallVector<std::pair<SUnit*, bool>, 4> DelDeps;
845 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
849 if (I->Dep->isScheduled) {
850 CopyToSU->Height = std::max(CopyToSU->Height, I->Dep->Height+1);
851 AddPred(I->Dep, CopyToSU, I->isCtrl, false, I->Reg, I->Cost);
852 DelDeps.push_back(std::make_pair(I->Dep, I->isCtrl));
855 for (unsigned i = 0, e = DelDeps.size(); i != e; ++i) {
856 SUnit *Succ = DelDeps[i].first;
857 bool isCtrl = DelDeps[i].second;
858 RemovePred(Succ, SU, isCtrl, false);
861 AddPred(CopyFromSU, SU, false, false, Reg, -1);
862 AddPred(CopyToSU, CopyFromSU, false, false, Reg, 1);
864 AvailableQueue->updateNode(SU);
865 AvailableQueue->addNode(CopyFromSU);
866 AvailableQueue->addNode(CopyToSU);
867 Copies.push_back(CopyFromSU);
868 Copies.push_back(CopyToSU);
873 /// getPhysicalRegisterVT - Returns the ValueType of the physical register
874 /// definition of the specified node.
875 /// FIXME: Move to SelectionDAG?
876 static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
877 const TargetInstrInfo *TII) {
878 const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
879 assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
880 unsigned NumRes = TID.getNumDefs();
881 for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
886 return N->getValueType(NumRes);
889 /// DelayForLiveRegsBottomUp - Returns true if it is necessary to delay
890 /// scheduling of the given node to satisfy live physical register dependencies.
891 /// If the specific node is the last one that's available to schedule, do
892 /// whatever is necessary (i.e. backtracking or cloning) to make it possible.
893 bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU,
894 SmallVector<unsigned, 4> &LRegs){
895 if (LiveRegs.empty())
898 SmallSet<unsigned, 4> RegAdded;
899 // If this node would clobber any "live" register, then it's not ready.
900 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
903 unsigned Reg = I->Reg;
904 if (LiveRegs.count(Reg) && LiveRegDefs[Reg] != I->Dep) {
905 if (RegAdded.insert(Reg))
906 LRegs.push_back(Reg);
908 for (const unsigned *Alias = TRI->getAliasSet(Reg);
910 if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) {
911 if (RegAdded.insert(*Alias))
912 LRegs.push_back(*Alias);
917 for (unsigned i = 0, e = SU->FlaggedNodes.size()+1; i != e; ++i) {
918 SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
919 if (!Node || !Node->isTargetOpcode())
921 const TargetInstrDesc &TID = TII->get(Node->getTargetOpcode());
922 if (!TID.ImplicitDefs)
924 for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
925 if (LiveRegs.count(*Reg) && LiveRegDefs[*Reg] != SU) {
926 if (RegAdded.insert(*Reg))
927 LRegs.push_back(*Reg);
929 for (const unsigned *Alias = TRI->getAliasSet(*Reg);
931 if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) {
932 if (RegAdded.insert(*Alias))
933 LRegs.push_back(*Alias);
937 return !LRegs.empty();
941 /// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
943 void ScheduleDAGRRList::ListScheduleBottomUp() {
944 unsigned CurCycle = 0;
945 // Add root to Available queue.
946 if (!SUnits.empty()) {
947 SUnit *RootSU = &SUnits[DAG.getRoot().Val->getNodeId()];
948 assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
949 RootSU->isAvailable = true;
950 AvailableQueue->push(RootSU);
953 // While Available queue is not empty, grab the node with the highest
954 // priority. If it is not ready put it back. Schedule the node.
955 SmallVector<SUnit*, 4> NotReady;
956 DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMap;
957 Sequence.reserve(SUnits.size());
958 while (!AvailableQueue->empty()) {
959 bool Delayed = false;
961 SUnit *CurSU = AvailableQueue->pop();
963 if (CurSU->CycleBound <= CurCycle) {
964 SmallVector<unsigned, 4> LRegs;
965 if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
968 LRegsMap.insert(std::make_pair(CurSU, LRegs));
971 CurSU->isPending = true; // This SU is not in AvailableQueue right now.
972 NotReady.push_back(CurSU);
973 CurSU = AvailableQueue->pop();
976 // All candidates are delayed due to live physical reg dependencies.
977 // Try backtracking, code duplication, or inserting cross class copies
979 if (Delayed && !CurSU) {
980 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
981 SUnit *TrySU = NotReady[i];
982 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
984 // Try unscheduling up to the point where it's safe to schedule
986 unsigned LiveCycle = CurCycle;
987 for (unsigned j = 0, ee = LRegs.size(); j != ee; ++j) {
988 unsigned Reg = LRegs[j];
989 unsigned LCycle = LiveRegCycles[Reg];
990 LiveCycle = std::min(LiveCycle, LCycle);
992 SUnit *OldSU = Sequence[LiveCycle];
993 if (!WillCreateCycle(TrySU, OldSU)) {
994 BacktrackBottomUp(TrySU, LiveCycle, CurCycle);
995 // Force the current node to be scheduled before the node that
996 // requires the physical reg dep.
997 if (OldSU->isAvailable) {
998 OldSU->isAvailable = false;
999 AvailableQueue->remove(OldSU);
1001 AddPred(TrySU, OldSU, true, true);
1002 // If one or more successors has been unscheduled, then the current
1003 // node is no longer avaialable. Schedule a successor that's now
1004 // available instead.
1005 if (!TrySU->isAvailable)
1006 CurSU = AvailableQueue->pop();
1009 TrySU->isPending = false;
1010 NotReady.erase(NotReady.begin()+i);
1017 // Can't backtrack. Try duplicating the nodes that produces these
1018 // "expensive to copy" values to break the dependency. In case even
1019 // that doesn't work, insert cross class copies.
1020 SUnit *TrySU = NotReady[0];
1021 SmallVector<unsigned, 4> &LRegs = LRegsMap[TrySU];
1022 assert(LRegs.size() == 1 && "Can't handle this yet!");
1023 unsigned Reg = LRegs[0];
1024 SUnit *LRDef = LiveRegDefs[Reg];
1025 SUnit *NewDef = CopyAndMoveSuccessors(LRDef);
1027 // Issue expensive cross register class copies.
1028 MVT VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII);
1029 const TargetRegisterClass *RC =
1030 TRI->getPhysicalRegisterRegClass(Reg, VT);
1031 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
1033 assert(false && "Don't know how to copy this physical register!");
1036 SmallVector<SUnit*, 2> Copies;
1037 InsertCCCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
1038 DOUT << "Adding an edge from SU # " << TrySU->NodeNum
1039 << " to SU #" << Copies.front()->NodeNum << "\n";
1040 AddPred(TrySU, Copies.front(), true, true);
1041 NewDef = Copies.back();
1044 DOUT << "Adding an edge from SU # " << NewDef->NodeNum
1045 << " to SU #" << TrySU->NodeNum << "\n";
1046 LiveRegDefs[Reg] = NewDef;
1047 AddPred(NewDef, TrySU, true, true);
1048 TrySU->isAvailable = false;
1053 assert(false && "Unable to resolve live physical register dependencies!");
1058 // Add the nodes that aren't ready back onto the available list.
1059 for (unsigned i = 0, e = NotReady.size(); i != e; ++i) {
1060 NotReady[i]->isPending = false;
1061 // May no longer be available due to backtracking.
1062 if (NotReady[i]->isAvailable)
1063 AvailableQueue->push(NotReady[i]);
1068 Sequence.push_back(0);
1070 ScheduleNodeBottomUp(CurSU, CurCycle);
1071 Sequence.push_back(CurSU);
1076 // Reverse the order if it is bottom up.
1077 std::reverse(Sequence.begin(), Sequence.end());
1081 // Verify that all SUnits were scheduled.
1082 bool AnyNotSched = false;
1083 unsigned DeadNodes = 0;
1085 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
1086 if (!SUnits[i].isScheduled) {
1087 if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) {
1092 cerr << "*** List scheduling failed! ***\n";
1093 SUnits[i].dump(&DAG);
1094 cerr << "has not been scheduled!\n";
1097 if (SUnits[i].NumSuccsLeft != 0) {
1099 cerr << "*** List scheduling failed! ***\n";
1100 SUnits[i].dump(&DAG);
1101 cerr << "has successors left!\n";
1105 for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
1108 assert(!AnyNotSched);
1109 assert(Sequence.size() + DeadNodes - Noops == SUnits.size() &&
1110 "The number of nodes scheduled doesn't match the expected number!");
1114 //===----------------------------------------------------------------------===//
1115 // Top-Down Scheduling
1116 //===----------------------------------------------------------------------===//
1118 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
1119 /// the AvailableQueue if the count reaches zero. Also update its cycle bound.
1120 void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain,
1121 unsigned CurCycle) {
1122 // FIXME: the distance between two nodes is not always == the predecessor's
1123 // latency. For example, the reader can very well read the register written
1124 // by the predecessor later than the issue cycle. It also depends on the
1125 // interrupt model (drain vs. freeze).
1126 SuccSU->CycleBound = std::max(SuccSU->CycleBound, CurCycle + SuccSU->Latency);
1128 --SuccSU->NumPredsLeft;
1131 if (SuccSU->NumPredsLeft < 0) {
1132 cerr << "*** List scheduling failed! ***\n";
1134 cerr << " has been released too many times!\n";
1139 if (SuccSU->NumPredsLeft == 0) {
1140 SuccSU->isAvailable = true;
1141 AvailableQueue->push(SuccSU);
1146 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
1147 /// count of its successors. If a successor pending count is zero, add it to
1148 /// the Available queue.
1149 void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
1150 DOUT << "*** Scheduling [" << CurCycle << "]: ";
1151 DEBUG(SU->dump(&DAG));
1152 SU->Cycle = CurCycle;
1154 AvailableQueue->ScheduledNode(SU);
1156 // Top down: release successors
1157 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1159 ReleaseSucc(I->Dep, I->isCtrl, CurCycle);
1160 SU->isScheduled = true;
1163 /// ListScheduleTopDown - The main loop of list scheduling for top-down
1165 void ScheduleDAGRRList::ListScheduleTopDown() {
1166 unsigned CurCycle = 0;
1168 // All leaves to Available queue.
1169 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
1170 // It is available if it has no predecessors.
1171 if (SUnits[i].Preds.empty()) {
1172 AvailableQueue->push(&SUnits[i]);
1173 SUnits[i].isAvailable = true;
1177 // While Available queue is not empty, grab the node with the highest
1178 // priority. If it is not ready put it back. Schedule the node.
1179 std::vector<SUnit*> NotReady;
1180 Sequence.reserve(SUnits.size());
1181 while (!AvailableQueue->empty()) {
1182 SUnit *CurSU = AvailableQueue->pop();
1183 while (CurSU && CurSU->CycleBound > CurCycle) {
1184 NotReady.push_back(CurSU);
1185 CurSU = AvailableQueue->pop();
1188 // Add the nodes that aren't ready back onto the available list.
1189 AvailableQueue->push_all(NotReady);
1193 Sequence.push_back(0);
1195 ScheduleNodeTopDown(CurSU, CurCycle);
1196 Sequence.push_back(CurSU);
1203 // Verify that all SUnits were scheduled.
1204 bool AnyNotSched = false;
1205 unsigned DeadNodes = 0;
1207 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
1208 if (!SUnits[i].isScheduled) {
1209 if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) {
1214 cerr << "*** List scheduling failed! ***\n";
1215 SUnits[i].dump(&DAG);
1216 cerr << "has not been scheduled!\n";
1219 if (SUnits[i].NumPredsLeft != 0) {
1221 cerr << "*** List scheduling failed! ***\n";
1222 SUnits[i].dump(&DAG);
1223 cerr << "has predecessors left!\n";
1227 for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
1230 assert(!AnyNotSched);
1231 assert(Sequence.size() + DeadNodes - Noops == SUnits.size() &&
1232 "The number of nodes scheduled doesn't match the expected number!");
1238 //===----------------------------------------------------------------------===//
1239 // RegReductionPriorityQueue Implementation
1240 //===----------------------------------------------------------------------===//
1242 // This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
1243 // to reduce register pressure.
1247 class RegReductionPriorityQueue;
1249 /// Sorting functions for the Available queue.
1250 struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
1251 RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ;
1252 bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {}
1253 bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
1255 bool operator()(const SUnit* left, const SUnit* right) const;
1258 struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
1259 RegReductionPriorityQueue<td_ls_rr_sort> *SPQ;
1260 td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {}
1261 td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
1263 bool operator()(const SUnit* left, const SUnit* right) const;
1265 } // end anonymous namespace
1267 static inline bool isCopyFromLiveIn(const SUnit *SU) {
1268 SDNode *N = SU->Node;
1269 return N && N->getOpcode() == ISD::CopyFromReg &&
1270 N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag;
1275 class VISIBILITY_HIDDEN RegReductionPriorityQueue
1276 : public SchedulingPriorityQueue {
1277 PriorityQueue<SUnit*, std::vector<SUnit*>, SF> Queue;
1278 unsigned currentQueueId;
1281 RegReductionPriorityQueue() :
1282 Queue(SF(this)), currentQueueId(0) {}
1284 virtual void initNodes(std::vector<SUnit> &sunits) {}
1286 virtual void addNode(const SUnit *SU) {}
1288 virtual void updateNode(const SUnit *SU) {}
1290 virtual void releaseState() {}
1292 virtual unsigned getNodePriority(const SUnit *SU) const {
1296 unsigned size() const { return Queue.size(); }
1298 bool empty() const { return Queue.empty(); }
1300 void push(SUnit *U) {
1301 assert(!U->NodeQueueId && "Node in the queue already");
1302 U->NodeQueueId = ++currentQueueId;
1306 void push_all(const std::vector<SUnit *> &Nodes) {
1307 for (unsigned i = 0, e = Nodes.size(); i != e; ++i)
1312 if (empty()) return NULL;
1313 SUnit *V = Queue.top();
1319 void remove(SUnit *SU) {
1320 assert(!Queue.empty() && "Queue is empty!");
1321 assert(SU->NodeQueueId != 0 && "Not in queue!");
1322 Queue.erase_one(SU);
1323 SU->NodeQueueId = 0;
1327 class VISIBILITY_HIDDEN BURegReductionPriorityQueue
1328 : public RegReductionPriorityQueue<bu_ls_rr_sort> {
1329 // SUnits - The SUnits for the current graph.
1330 const std::vector<SUnit> *SUnits;
1332 // SethiUllmanNumbers - The SethiUllman number for each node.
1333 std::vector<unsigned> SethiUllmanNumbers;
1335 const TargetInstrInfo *TII;
1336 const TargetRegisterInfo *TRI;
1337 ScheduleDAGRRList *scheduleDAG;
1339 explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii,
1340 const TargetRegisterInfo *tri)
1341 : TII(tii), TRI(tri), scheduleDAG(NULL) {}
1343 void initNodes(std::vector<SUnit> &sunits) {
1345 // Add pseudo dependency edges for two-address nodes.
1346 AddPseudoTwoAddrDeps();
1347 // Calculate node priorities.
1348 CalculateSethiUllmanNumbers();
1351 void addNode(const SUnit *SU) {
1352 SethiUllmanNumbers.resize(SUnits->size(), 0);
1353 CalcNodeSethiUllmanNumber(SU);
1356 void updateNode(const SUnit *SU) {
1357 SethiUllmanNumbers[SU->NodeNum] = 0;
1358 CalcNodeSethiUllmanNumber(SU);
1361 void releaseState() {
1363 SethiUllmanNumbers.clear();
1366 unsigned getNodePriority(const SUnit *SU) const {
1367 assert(SU->NodeNum < SethiUllmanNumbers.size());
1368 unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0;
1369 if (Opc == ISD::CopyFromReg && !isCopyFromLiveIn(SU))
1370 // CopyFromReg should be close to its def because it restricts
1371 // allocation choices. But if it is a livein then perhaps we want it
1372 // closer to its uses so it can be coalesced.
1374 else if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
1375 // CopyToReg should be close to its uses to facilitate coalescing and
1378 else if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
1379 Opc == TargetInstrInfo::INSERT_SUBREG)
1380 // EXTRACT_SUBREG / INSERT_SUBREG should be close to its use to
1381 // facilitate coalescing.
1383 else if (SU->NumSuccs == 0)
1384 // If SU does not have a use, i.e. it doesn't produce a value that would
1385 // be consumed (e.g. store), then it terminates a chain of computation.
1386 // Give it a large SethiUllman number so it will be scheduled right
1387 // before its predecessors that it doesn't lengthen their live ranges.
1389 else if (SU->NumPreds == 0)
1390 // If SU does not have a def, schedule it close to its uses because it
1391 // does not lengthen any live ranges.
1394 return SethiUllmanNumbers[SU->NodeNum];
1397 void setScheduleDAG(ScheduleDAGRRList *scheduleDag) {
1398 scheduleDAG = scheduleDag;
1402 bool canClobber(const SUnit *SU, const SUnit *Op);
1403 void AddPseudoTwoAddrDeps();
1404 void CalculateSethiUllmanNumbers();
1405 unsigned CalcNodeSethiUllmanNumber(const SUnit *SU);
1409 class VISIBILITY_HIDDEN TDRegReductionPriorityQueue
1410 : public RegReductionPriorityQueue<td_ls_rr_sort> {
1411 // SUnits - The SUnits for the current graph.
1412 const std::vector<SUnit> *SUnits;
1414 // SethiUllmanNumbers - The SethiUllman number for each node.
1415 std::vector<unsigned> SethiUllmanNumbers;
1418 TDRegReductionPriorityQueue() {}
1420 void initNodes(std::vector<SUnit> &sunits) {
1422 // Calculate node priorities.
1423 CalculateSethiUllmanNumbers();
1426 void addNode(const SUnit *SU) {
1427 SethiUllmanNumbers.resize(SUnits->size(), 0);
1428 CalcNodeSethiUllmanNumber(SU);
1431 void updateNode(const SUnit *SU) {
1432 SethiUllmanNumbers[SU->NodeNum] = 0;
1433 CalcNodeSethiUllmanNumber(SU);
1436 void releaseState() {
1438 SethiUllmanNumbers.clear();
1441 unsigned getNodePriority(const SUnit *SU) const {
1442 assert(SU->NodeNum < SethiUllmanNumbers.size());
1443 return SethiUllmanNumbers[SU->NodeNum];
1447 void CalculateSethiUllmanNumbers();
1448 unsigned CalcNodeSethiUllmanNumber(const SUnit *SU);
1452 /// closestSucc - Returns the scheduled cycle of the successor which is
1453 /// closet to the current cycle.
1454 static unsigned closestSucc(const SUnit *SU) {
1455 unsigned MaxCycle = 0;
1456 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1458 unsigned Cycle = I->Dep->Cycle;
1459 // If there are bunch of CopyToRegs stacked up, they should be considered
1460 // to be at the same position.
1461 if (I->Dep->Node && I->Dep->Node->getOpcode() == ISD::CopyToReg)
1462 Cycle = closestSucc(I->Dep)+1;
1463 if (Cycle > MaxCycle)
1469 /// calcMaxScratches - Returns an cost estimate of the worse case requirement
1470 /// for scratch registers. Live-in operands and live-out results don't count
1471 /// since they are "fixed".
1472 static unsigned calcMaxScratches(const SUnit *SU) {
1473 unsigned Scratches = 0;
1474 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1476 if (I->isCtrl) continue; // ignore chain preds
1477 if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyFromReg)
1480 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1482 if (I->isCtrl) continue; // ignore chain succs
1483 if (!I->Dep->Node || I->Dep->Node->getOpcode() != ISD::CopyToReg)
1490 bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
1492 unsigned LPriority = SPQ->getNodePriority(left);
1493 unsigned RPriority = SPQ->getNodePriority(right);
1494 if (LPriority != RPriority)
1495 return LPriority > RPriority;
1497 // Try schedule def + use closer when Sethi-Ullman numbers are the same.
1502 // and the following instructions are both ready.
1506 // Then schedule t2 = op first.
1513 // This creates more short live intervals.
1514 unsigned LDist = closestSucc(left);
1515 unsigned RDist = closestSucc(right);
1517 return LDist < RDist;
1519 // Intuitively, it's good to push down instructions whose results are
1520 // liveout so their long live ranges won't conflict with other values
1521 // which are needed inside the BB. Further prioritize liveout instructions
1522 // by the number of operands which are calculated within the BB.
1523 unsigned LScratch = calcMaxScratches(left);
1524 unsigned RScratch = calcMaxScratches(right);
1525 if (LScratch != RScratch)
1526 return LScratch > RScratch;
1528 if (left->Height != right->Height)
1529 return left->Height > right->Height;
1531 if (left->Depth != right->Depth)
1532 return left->Depth < right->Depth;
1534 if (left->CycleBound != right->CycleBound)
1535 return left->CycleBound > right->CycleBound;
1537 assert(left->NodeQueueId && right->NodeQueueId &&
1538 "NodeQueueId cannot be zero");
1539 return (left->NodeQueueId > right->NodeQueueId);
1543 BURegReductionPriorityQueue::canClobber(const SUnit *SU, const SUnit *Op) {
1544 if (SU->isTwoAddress) {
1545 unsigned Opc = SU->Node->getTargetOpcode();
1546 const TargetInstrDesc &TID = TII->get(Opc);
1547 unsigned NumRes = TID.getNumDefs();
1548 unsigned NumOps = TID.getNumOperands() - NumRes;
1549 for (unsigned i = 0; i != NumOps; ++i) {
1550 if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) {
1551 SDNode *DU = SU->Node->getOperand(i).Val;
1552 if (DU->getNodeId() != -1 &&
1553 Op->OrigNode == &(*SUnits)[DU->getNodeId()])
1562 /// hasCopyToRegUse - Return true if SU has a value successor that is a
1564 static bool hasCopyToRegUse(SUnit *SU) {
1565 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1567 if (I->isCtrl) continue;
1568 SUnit *SuccSU = I->Dep;
1569 if (SuccSU->Node && SuccSU->Node->getOpcode() == ISD::CopyToReg)
1575 /// canClobberPhysRegDefs - True if SU would clobber one of SuccSU's
1576 /// physical register defs.
1577 static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU,
1578 const TargetInstrInfo *TII,
1579 const TargetRegisterInfo *TRI) {
1580 SDNode *N = SuccSU->Node;
1581 unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs();
1582 const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs();
1583 assert(ImpDefs && "Caller should check hasPhysRegDefs");
1584 const unsigned *SUImpDefs =
1585 TII->get(SU->Node->getTargetOpcode()).getImplicitDefs();
1588 for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
1589 MVT VT = N->getValueType(i);
1590 if (VT == MVT::Flag || VT == MVT::Other)
1592 unsigned Reg = ImpDefs[i - NumDefs];
1593 for (;*SUImpDefs; ++SUImpDefs) {
1594 unsigned SUReg = *SUImpDefs;
1595 if (TRI->regsOverlap(Reg, SUReg))
1602 /// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
1603 /// it as a def&use operand. Add a pseudo control edge from it to the other
1604 /// node (if it won't create a cycle) so the two-address one will be scheduled
1605 /// first (lower in the schedule). If both nodes are two-address, favor the
1606 /// one that has a CopyToReg use (more likely to be a loop induction update).
1607 /// If both are two-address, but one is commutable while the other is not
1608 /// commutable, favor the one that's not commutable.
1609 void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() {
1610 for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
1611 SUnit *SU = (SUnit *)&((*SUnits)[i]);
1612 if (!SU->isTwoAddress)
1615 SDNode *Node = SU->Node;
1616 if (!Node || !Node->isTargetOpcode() || SU->FlaggedNodes.size() > 0)
1619 unsigned Opc = Node->getTargetOpcode();
1620 const TargetInstrDesc &TID = TII->get(Opc);
1621 unsigned NumRes = TID.getNumDefs();
1622 unsigned NumOps = TID.getNumOperands() - NumRes;
1623 for (unsigned j = 0; j != NumOps; ++j) {
1624 if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) != -1) {
1625 SDNode *DU = SU->Node->getOperand(j).Val;
1626 if (DU->getNodeId() == -1)
1628 const SUnit *DUSU = &(*SUnits)[DU->getNodeId()];
1629 if (!DUSU) continue;
1630 for (SUnit::const_succ_iterator I = DUSU->Succs.begin(),
1631 E = DUSU->Succs.end(); I != E; ++I) {
1632 if (I->isCtrl) continue;
1633 SUnit *SuccSU = I->Dep;
1636 // Be conservative. Ignore if nodes aren't at roughly the same
1637 // depth and height.
1638 if (SuccSU->Height < SU->Height && (SU->Height - SuccSU->Height) > 1)
1640 if (!SuccSU->Node || !SuccSU->Node->isTargetOpcode())
1642 // Don't constrain nodes with physical register defs if the
1643 // predecessor can clobber them.
1644 if (SuccSU->hasPhysRegDefs) {
1645 if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
1648 // Don't constraint extract_subreg / insert_subreg these may be
1649 // coalesced away. We don't them close to their uses.
1650 unsigned SuccOpc = SuccSU->Node->getTargetOpcode();
1651 if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG ||
1652 SuccOpc == TargetInstrInfo::INSERT_SUBREG)
1654 if ((!canClobber(SuccSU, DUSU) ||
1655 (hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) ||
1656 (!SU->isCommutable && SuccSU->isCommutable)) &&
1657 !scheduleDAG->IsReachable(SuccSU, SU)) {
1658 DOUT << "Adding an edge from SU # " << SU->NodeNum
1659 << " to SU #" << SuccSU->NodeNum << "\n";
1660 scheduleDAG->AddPred(SU, SuccSU, true, true);
1668 /// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
1669 /// Smaller number is the higher priority.
1670 unsigned BURegReductionPriorityQueue::
1671 CalcNodeSethiUllmanNumber(const SUnit *SU) {
1672 unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
1673 if (SethiUllmanNumber != 0)
1674 return SethiUllmanNumber;
1677 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1679 if (I->isCtrl) continue; // ignore chain preds
1680 SUnit *PredSU = I->Dep;
1681 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU);
1682 if (PredSethiUllman > SethiUllmanNumber) {
1683 SethiUllmanNumber = PredSethiUllman;
1685 } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl)
1689 SethiUllmanNumber += Extra;
1691 if (SethiUllmanNumber == 0)
1692 SethiUllmanNumber = 1;
1694 return SethiUllmanNumber;
1697 /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
1698 /// scheduling units.
1699 void BURegReductionPriorityQueue::CalculateSethiUllmanNumbers() {
1700 SethiUllmanNumbers.assign(SUnits->size(), 0);
1702 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
1703 CalcNodeSethiUllmanNumber(&(*SUnits)[i]);
1706 /// LimitedSumOfUnscheduledPredsOfSuccs - Compute the sum of the unscheduled
1707 /// predecessors of the successors of the SUnit SU. Stop when the provided
1708 /// limit is exceeded.
1709 static unsigned LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU,
1712 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1714 SUnit *SuccSU = I->Dep;
1715 for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(),
1716 EE = SuccSU->Preds.end(); II != EE; ++II) {
1717 SUnit *PredSU = II->Dep;
1718 if (!PredSU->isScheduled)
1728 bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
1729 unsigned LPriority = SPQ->getNodePriority(left);
1730 unsigned RPriority = SPQ->getNodePriority(right);
1731 bool LIsTarget = left->Node && left->Node->isTargetOpcode();
1732 bool RIsTarget = right->Node && right->Node->isTargetOpcode();
1733 bool LIsFloater = LIsTarget && left->NumPreds == 0;
1734 bool RIsFloater = RIsTarget && right->NumPreds == 0;
1735 unsigned LBonus = (LimitedSumOfUnscheduledPredsOfSuccs(left,1) == 1) ? 2 : 0;
1736 unsigned RBonus = (LimitedSumOfUnscheduledPredsOfSuccs(right,1) == 1) ? 2 : 0;
1738 if (left->NumSuccs == 0 && right->NumSuccs != 0)
1740 else if (left->NumSuccs != 0 && right->NumSuccs == 0)
1747 if (left->NumSuccs == 1)
1749 if (right->NumSuccs == 1)
1752 if (LPriority+LBonus != RPriority+RBonus)
1753 return LPriority+LBonus < RPriority+RBonus;
1755 if (left->Depth != right->Depth)
1756 return left->Depth < right->Depth;
1758 if (left->NumSuccsLeft != right->NumSuccsLeft)
1759 return left->NumSuccsLeft > right->NumSuccsLeft;
1761 if (left->CycleBound != right->CycleBound)
1762 return left->CycleBound > right->CycleBound;
1764 assert(left->NodeQueueId && right->NodeQueueId &&
1765 "NodeQueueId cannot be zero");
1766 return (left->NodeQueueId > right->NodeQueueId);
1769 /// CalcNodeSethiUllmanNumber - Priority is the Sethi Ullman number.
1770 /// Smaller number is the higher priority.
1771 unsigned TDRegReductionPriorityQueue::
1772 CalcNodeSethiUllmanNumber(const SUnit *SU) {
1773 unsigned &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
1774 if (SethiUllmanNumber != 0)
1775 return SethiUllmanNumber;
1777 unsigned Opc = SU->Node ? SU->Node->getOpcode() : 0;
1778 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
1779 SethiUllmanNumber = 0xffff;
1780 else if (SU->NumSuccsLeft == 0)
1781 // If SU does not have a use, i.e. it doesn't produce a value that would
1782 // be consumed (e.g. store), then it terminates a chain of computation.
1783 // Give it a small SethiUllman number so it will be scheduled right before
1784 // its predecessors that it doesn't lengthen their live ranges.
1785 SethiUllmanNumber = 0;
1786 else if (SU->NumPredsLeft == 0 &&
1787 (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
1788 SethiUllmanNumber = 0xffff;
1791 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1793 if (I->isCtrl) continue; // ignore chain preds
1794 SUnit *PredSU = I->Dep;
1795 unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU);
1796 if (PredSethiUllman > SethiUllmanNumber) {
1797 SethiUllmanNumber = PredSethiUllman;
1799 } else if (PredSethiUllman == SethiUllmanNumber && !I->isCtrl)
1803 SethiUllmanNumber += Extra;
1806 return SethiUllmanNumber;
1809 /// CalculateSethiUllmanNumbers - Calculate Sethi-Ullman numbers of all
1810 /// scheduling units.
1811 void TDRegReductionPriorityQueue::CalculateSethiUllmanNumbers() {
1812 SethiUllmanNumbers.assign(SUnits->size(), 0);
1814 for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
1815 CalcNodeSethiUllmanNumber(&(*SUnits)[i]);
1818 //===----------------------------------------------------------------------===//
1819 // Public Constructor Functions
1820 //===----------------------------------------------------------------------===//
1822 llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
1824 MachineBasicBlock *BB) {
1825 const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo();
1826 const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo();
1828 BURegReductionPriorityQueue *priorityQueue =
1829 new BURegReductionPriorityQueue(TII, TRI);
1831 ScheduleDAGRRList * scheduleDAG =
1832 new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, priorityQueue);
1833 priorityQueue->setScheduleDAG(scheduleDAG);
1837 llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
1839 MachineBasicBlock *BB) {
1840 return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false,
1841 new TDRegReductionPriorityQueue());