1 //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAG class, which is a base class used by
11 // scheduling implementation classes.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pre-RA-sched"
16 #include "SDNodeDbgValue.h"
17 #include "ScheduleDAGSDNodes.h"
18 #include "InstrEmitter.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Target/TargetSubtarget.h"
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/ADT/SmallPtrSet.h"
27 #include "llvm/ADT/SmallSet.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/raw_ostream.h"
35 STATISTIC(LoadsClustered, "Number of loads clustered together");
37 // This allows latency based scheduler to notice high latency instructions
38 // without a target itinerary. The choise if number here has more to do with
39 // balancing scheduler heursitics than with the actual machine latency.
40 static cl::opt<int> HighLatencyCycles(
41 "sched-high-latency-cycles", cl::Hidden, cl::init(10),
42 cl::desc("Roughly estimate the number of cycles that 'long latency'"
43 "instructions take for targets with no itinerary"));
45 ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
47 InstrItins(mf.getTarget().getInstrItineraryData()) {}
49 /// Run - perform scheduling.
51 void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb,
52 MachineBasicBlock::iterator insertPos) {
54 ScheduleDAG::Run(bb, insertPos);
57 /// NewSUnit - Creates a new SUnit and return a ptr to it.
59 SUnit *ScheduleDAGSDNodes::NewSUnit(SDNode *N) {
61 const SUnit *Addr = 0;
65 SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
66 assert((Addr == 0 || Addr == &SUnits[0]) &&
67 "SUnits std::vector reallocated on the fly!");
68 SUnits.back().OrigNode = &SUnits.back();
69 SUnit *SU = &SUnits.back();
70 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
72 (N->isMachineOpcode() &&
73 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
74 SU->SchedulingPref = Sched::None;
76 SU->SchedulingPref = TLI.getSchedulingPreference(N);
80 SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
81 SUnit *SU = NewSUnit(Old->getNode());
82 SU->OrigNode = Old->OrigNode;
83 SU->Latency = Old->Latency;
84 SU->isCall = Old->isCall;
85 SU->isTwoAddress = Old->isTwoAddress;
86 SU->isCommutable = Old->isCommutable;
87 SU->hasPhysRegDefs = Old->hasPhysRegDefs;
88 SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
89 SU->SchedulingPref = Old->SchedulingPref;
94 /// CheckForPhysRegDependency - Check if the dependency between def and use of
95 /// a specified operand is a physical register dependency. If so, returns the
96 /// register and the cost of copying the register.
97 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
98 const TargetRegisterInfo *TRI,
99 const TargetInstrInfo *TII,
100 unsigned &PhysReg, int &Cost) {
101 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
104 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
105 if (TargetRegisterInfo::isVirtualRegister(Reg))
108 unsigned ResNo = User->getOperand(2).getResNo();
109 if (Def->isMachineOpcode()) {
110 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
111 if (ResNo >= II.getNumDefs() &&
112 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
114 const TargetRegisterClass *RC =
115 TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo));
116 Cost = RC->getCopyCost();
121 static void AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
122 SmallVector<EVT, 4> VTs;
123 SDNode *GlueDestNode = Glue.getNode();
125 // Don't add glue from a node to itself.
126 if (GlueDestNode == N) return;
128 // Don't add glue to something which already has glue.
129 if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return;
131 for (unsigned I = 0, E = N->getNumValues(); I != E; ++I)
132 VTs.push_back(N->getValueType(I));
135 VTs.push_back(MVT::Glue);
137 SmallVector<SDValue, 4> Ops;
138 for (unsigned I = 0, E = N->getNumOperands(); I != E; ++I)
139 Ops.push_back(N->getOperand(I));
144 SDVTList VTList = DAG->getVTList(&VTs[0], VTs.size());
145 MachineSDNode::mmo_iterator Begin = 0, End = 0;
146 MachineSDNode *MN = dyn_cast<MachineSDNode>(N);
148 // Store memory references.
150 Begin = MN->memoperands_begin();
151 End = MN->memoperands_end();
154 DAG->MorphNodeTo(N, N->getOpcode(), VTList, &Ops[0], Ops.size());
156 // Reset the memory references
158 MN->setMemRefs(Begin, End);
161 /// ClusterNeighboringLoads - Force nearby loads together by "gluing" them.
162 /// This function finds loads of the same base and different offsets. If the
163 /// offsets are not far apart (target specific), it add MVT::Glue inputs and
164 /// outputs to ensure they are scheduled together and in order. This
165 /// optimization may benefit some targets by improving cache locality.
166 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
168 unsigned NumOps = Node->getNumOperands();
169 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
170 Chain = Node->getOperand(NumOps-1).getNode();
174 // Look for other loads of the same chain. Find loads that are loading from
175 // the same base pointer and different offsets.
176 SmallPtrSet<SDNode*, 16> Visited;
177 SmallVector<int64_t, 4> Offsets;
178 DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
179 bool Cluster = false;
181 for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
184 if (User == Node || !Visited.insert(User))
186 int64_t Offset1, Offset2;
187 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
189 // FIXME: Should be ok if they addresses are identical. But earlier
190 // optimizations really should have eliminated one of the loads.
192 if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
193 Offsets.push_back(Offset1);
194 O2SMap.insert(std::make_pair(Offset2, User));
195 Offsets.push_back(Offset2);
196 if (Offset2 < Offset1)
204 // Sort them in increasing order.
205 std::sort(Offsets.begin(), Offsets.end());
207 // Check if the loads are close enough.
208 SmallVector<SDNode*, 4> Loads;
209 unsigned NumLoads = 0;
210 int64_t BaseOff = Offsets[0];
211 SDNode *BaseLoad = O2SMap[BaseOff];
212 Loads.push_back(BaseLoad);
213 for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
214 int64_t Offset = Offsets[i];
215 SDNode *Load = O2SMap[Offset];
216 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
217 break; // Stop right here. Ignore loads that are further away.
218 Loads.push_back(Load);
225 // Cluster loads by adding MVT::Glue outputs and inputs. This also
226 // ensure they are scheduled in order of increasing addresses.
227 SDNode *Lead = Loads[0];
228 AddGlue(Lead, SDValue(0, 0), true, DAG);
230 SDValue InGlue = SDValue(Lead, Lead->getNumValues() - 1);
231 for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
232 bool OutGlue = I < E - 1;
233 SDNode *Load = Loads[I];
235 AddGlue(Load, InGlue, OutGlue, DAG);
238 InGlue = SDValue(Load, Load->getNumValues() - 1);
244 /// ClusterNodes - Cluster certain nodes which should be scheduled together.
246 void ScheduleDAGSDNodes::ClusterNodes() {
247 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
248 E = DAG->allnodes_end(); NI != E; ++NI) {
250 if (!Node || !Node->isMachineOpcode())
253 unsigned Opc = Node->getMachineOpcode();
254 const TargetInstrDesc &TID = TII->get(Opc);
256 // Cluster loads from "near" addresses into combined SUnits.
257 ClusterNeighboringLoads(Node);
261 void ScheduleDAGSDNodes::BuildSchedUnits() {
262 // During scheduling, the NodeId field of SDNode is used to map SDNodes
263 // to their associated SUnits by holding SUnits table indices. A value
264 // of -1 means the SDNode does not yet have an associated SUnit.
265 unsigned NumNodes = 0;
266 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
267 E = DAG->allnodes_end(); NI != E; ++NI) {
272 // Reserve entries in the vector for each of the SUnits we are creating. This
273 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
275 // FIXME: Multiply by 2 because we may clone nodes during scheduling.
276 // This is a temporary workaround.
277 SUnits.reserve(NumNodes * 2);
279 // Add all nodes in depth first order.
280 SmallVector<SDNode*, 64> Worklist;
281 SmallPtrSet<SDNode*, 64> Visited;
282 Worklist.push_back(DAG->getRoot().getNode());
283 Visited.insert(DAG->getRoot().getNode());
285 while (!Worklist.empty()) {
286 SDNode *NI = Worklist.pop_back_val();
288 // Add all operands to the worklist unless they've already been added.
289 for (unsigned i = 0, e = NI->getNumOperands(); i != e; ++i)
290 if (Visited.insert(NI->getOperand(i).getNode()))
291 Worklist.push_back(NI->getOperand(i).getNode());
293 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
296 // If this node has already been processed, stop now.
297 if (NI->getNodeId() != -1) continue;
299 SUnit *NodeSUnit = NewSUnit(NI);
301 // See if anything is glued to this node, if so, add them to glued
302 // nodes. Nodes can have at most one glue input and one glue output. Glue
303 // is required to be the last operand and result of a node.
305 // Scan up to find glued preds.
307 while (N->getNumOperands() &&
308 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
309 N = N->getOperand(N->getNumOperands()-1).getNode();
310 assert(N->getNodeId() == -1 && "Node already inserted!");
311 N->setNodeId(NodeSUnit->NodeNum);
312 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
313 NodeSUnit->isCall = true;
316 // Scan down to find any glued succs.
318 while (N->getValueType(N->getNumValues()-1) == MVT::Glue) {
319 SDValue GlueVal(N, N->getNumValues()-1);
321 // There are either zero or one users of the Glue result.
322 bool HasGlueUse = false;
323 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
325 if (GlueVal.isOperandOf(*UI)) {
327 assert(N->getNodeId() == -1 && "Node already inserted!");
328 N->setNodeId(NodeSUnit->NodeNum);
330 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
331 NodeSUnit->isCall = true;
334 if (!HasGlueUse) break;
337 // If there are glue operands involved, N is now the bottom-most node
338 // of the sequence of nodes that are glued together.
340 NodeSUnit->setNode(N);
341 assert(N->getNodeId() == -1 && "Node already inserted!");
342 N->setNodeId(NodeSUnit->NodeNum);
344 // Compute NumRegDefsLeft. This must be done before AddSchedEdges.
345 InitNumRegDefsLeft(NodeSUnit);
347 // Assign the Latency field of NodeSUnit using target-provided information.
348 ComputeLatency(NodeSUnit);
352 void ScheduleDAGSDNodes::AddSchedEdges() {
353 const TargetSubtarget &ST = TM.getSubtarget<TargetSubtarget>();
355 // Check to see if the scheduler cares about latencies.
356 bool UnitLatencies = ForceUnitLatencies();
358 // Pass 2: add the preds, succs, etc.
359 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
360 SUnit *SU = &SUnits[su];
361 SDNode *MainNode = SU->getNode();
363 if (MainNode->isMachineOpcode()) {
364 unsigned Opc = MainNode->getMachineOpcode();
365 const TargetInstrDesc &TID = TII->get(Opc);
366 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
367 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
368 SU->isTwoAddress = true;
372 if (TID.isCommutable())
373 SU->isCommutable = true;
376 // Find all predecessors and successors of the group.
377 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) {
378 if (N->isMachineOpcode() &&
379 TII->get(N->getMachineOpcode()).getImplicitDefs()) {
380 SU->hasPhysRegClobbers = true;
381 unsigned NumUsed = InstrEmitter::CountResults(N);
382 while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
383 --NumUsed; // Skip over unused values at the end.
384 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
385 SU->hasPhysRegDefs = true;
388 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
389 SDNode *OpN = N->getOperand(i).getNode();
390 if (isPassiveNode(OpN)) continue; // Not scheduled.
391 SUnit *OpSU = &SUnits[OpN->getNodeId()];
392 assert(OpSU && "Node has no SUnit!");
393 if (OpSU == SU) continue; // In the same group.
395 EVT OpVT = N->getOperand(i).getValueType();
396 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
397 bool isChain = OpVT == MVT::Other;
399 unsigned PhysReg = 0;
401 // Determine if this is a physical register dependency.
402 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
403 assert((PhysReg == 0 || !isChain) &&
404 "Chain dependence via physreg data?");
405 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
406 // emits a copy from the physical register to a virtual register unless
407 // it requires a cross class copy (cost < 0). That means we are only
408 // treating "expensive to copy" register dependency as physical register
409 // dependency. This may change in the future though.
413 // If this is a ctrl dep, latency is 1.
414 unsigned OpLatency = isChain ? 1 : OpSU->Latency;
415 const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
417 if (!isChain && !UnitLatencies) {
418 ComputeOperandLatency(OpN, N, i, const_cast<SDep &>(dep));
419 ST.adjustSchedDependency(OpSU, SU, const_cast<SDep &>(dep));
422 if (!SU->addPred(dep) && !dep.isCtrl() && OpSU->NumRegDefsLeft > 0) {
423 // Multiple register uses are combined in the same SUnit. For example,
424 // we could have a set of glued nodes with all their defs consumed by
425 // another set of glued nodes. Register pressure tracking sees this as
426 // a single use, so to keep pressure balanced we reduce the defs.
427 --OpSU->NumRegDefsLeft;
434 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
435 /// are input. This SUnit graph is similar to the SelectionDAG, but
436 /// excludes nodes that aren't interesting to scheduling, and represents
437 /// glued together nodes with a single SUnit.
438 void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) {
439 // Cluster certain nodes which should be scheduled together.
441 // Populate the SUnits array.
443 // Compute all the scheduling dependencies between nodes.
447 // Initialize NumNodeDefs for the current Node's opcode.
448 void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
449 if (!Node->isMachineOpcode()) {
450 if (Node->getOpcode() == ISD::CopyFromReg)
456 unsigned POpc = Node->getMachineOpcode();
457 if (POpc == TargetOpcode::IMPLICIT_DEF) {
458 // No register need be allocated for this.
462 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
463 // Some instructions define regs that are not represented in the selection DAG
464 // (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues.
465 NodeNumDefs = std::min(Node->getNumValues(), NRegDefs);
469 // Construct a RegDefIter for this SUnit and find the first valid value.
470 ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU,
471 const ScheduleDAGSDNodes *SD)
472 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
477 // Advance to the next valid value defined by the SUnit.
478 void ScheduleDAGSDNodes::RegDefIter::Advance() {
479 for (;Node;) { // Visit all glued nodes.
480 for (;DefIdx < NodeNumDefs; ++DefIdx) {
481 if (!Node->hasAnyUseOfValue(DefIdx))
483 if (Node->isMachineOpcode() &&
484 Node->getMachineOpcode() == TargetOpcode::EXTRACT_SUBREG) {
485 // Propagate the incoming (full-register) type. I doubt it's needed.
486 ValueType = Node->getOperand(0).getValueType();
489 ValueType = Node->getValueType(DefIdx);
492 return; // Found a normal regdef.
494 Node = Node->getGluedNode();
496 return; // No values left to visit.
502 void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
503 assert(SU->NumRegDefsLeft == 0 && "expect a new node");
504 for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
505 assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected");
506 ++SU->NumRegDefsLeft;
510 void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
511 // Check to see if the scheduler cares about latencies.
512 if (ForceUnitLatencies()) {
517 if (!InstrItins || InstrItins->isEmpty()) {
518 if (SU->getNode() && TII->isHighLatencyDef(SU->getNode()->getOpcode()))
519 SU->Latency = HighLatencyCycles;
525 // Compute the latency for the node. We use the sum of the latencies for
526 // all nodes glued together into this SUnit.
528 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
529 if (N->isMachineOpcode())
530 SU->Latency += TII->getInstrLatency(InstrItins, N);
533 void ScheduleDAGSDNodes::ComputeOperandLatency(SDNode *Def, SDNode *Use,
534 unsigned OpIdx, SDep& dep) const{
535 // Check to see if the scheduler cares about latencies.
536 if (ForceUnitLatencies())
539 if (dep.getKind() != SDep::Data)
542 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
543 if (Use->isMachineOpcode())
544 // Adjust the use operand index by num of defs.
545 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
546 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
547 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
549 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
550 if (TargetRegisterInfo::isVirtualRegister(Reg))
551 // This copy is a liveout value. It is likely coalesced, so reduce the
552 // latency so not to penalize the def.
553 // FIXME: need target specific adjustment here?
554 Latency = (Latency > 1) ? Latency - 1 : 1;
557 dep.setLatency(Latency);
560 void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
561 if (!SU->getNode()) {
562 dbgs() << "PHYS REG COPY\n";
566 SU->getNode()->dump(DAG);
568 SmallVector<SDNode *, 4> GluedNodes;
569 for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
570 GluedNodes.push_back(N);
571 while (!GluedNodes.empty()) {
573 GluedNodes.back()->dump(DAG);
575 GluedNodes.pop_back();
581 bool operator()(const std::pair<unsigned, MachineInstr*> &A,
582 const std::pair<unsigned, MachineInstr*> &B) {
583 return A.first < B.first;
588 /// ProcessSDDbgValues - Process SDDbgValues assoicated with this node.
589 static void ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG,
590 InstrEmitter &Emitter,
591 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
592 DenseMap<SDValue, unsigned> &VRBaseMap,
594 if (!N->getHasDebugValue())
597 // Opportunistically insert immediate dbg_value uses, i.e. those with source
598 // order number right after the N.
599 MachineBasicBlock *BB = Emitter.getBlock();
600 MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
601 SmallVector<SDDbgValue*,2> &DVs = DAG->GetDbgValues(N);
602 for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
603 if (DVs[i]->isInvalidated())
605 unsigned DVOrder = DVs[i]->getOrder();
606 if (!Order || DVOrder == ++Order) {
607 MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap);
609 Orders.push_back(std::make_pair(DVOrder, DbgMI));
610 BB->insert(InsertPos, DbgMI);
612 DVs[i]->setIsInvalidated();
617 // ProcessSourceNode - Process nodes with source order numbers. These are added
618 // to a vector which EmitSchedule uses to determine how to insert dbg_value
619 // instructions in the right order.
620 static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
621 InstrEmitter &Emitter,
622 DenseMap<SDValue, unsigned> &VRBaseMap,
623 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
624 SmallSet<unsigned, 8> &Seen) {
625 unsigned Order = DAG->GetOrdering(N);
626 if (!Order || !Seen.insert(Order)) {
627 // Process any valid SDDbgValues even if node does not have any order
629 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
633 MachineBasicBlock *BB = Emitter.getBlock();
634 if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI()) {
635 // Did not insert any instruction.
636 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
640 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
641 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
645 /// EmitSchedule - Emit the machine code in scheduled order.
646 MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
647 InstrEmitter Emitter(BB, InsertPos);
648 DenseMap<SDValue, unsigned> VRBaseMap;
649 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
650 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
651 SmallSet<unsigned, 8> Seen;
652 bool HasDbg = DAG->hasDebugValues();
654 // If this is the first BB, emit byval parameter dbg_value's.
655 if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
656 SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();
657 SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd();
658 for (; PDI != PDE; ++PDI) {
659 MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
661 BB->insert(InsertPos, DbgMI);
665 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
666 SUnit *SU = Sequence[i];
668 // Null SUnit* is a noop.
673 // For pre-regalloc scheduling, create instructions corresponding to the
674 // SDNode and any glued SDNodes and append them to the block.
675 if (!SU->getNode()) {
677 EmitPhysRegCopy(SU, CopyVRBaseMap);
681 SmallVector<SDNode *, 4> GluedNodes;
682 for (SDNode *N = SU->getNode()->getGluedNode(); N;
683 N = N->getGluedNode())
684 GluedNodes.push_back(N);
685 while (!GluedNodes.empty()) {
686 SDNode *N = GluedNodes.back();
687 Emitter.EmitNode(GluedNodes.back(), SU->OrigNode != SU, SU->isCloned,
689 // Remember the source order of the inserted instruction.
691 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
692 GluedNodes.pop_back();
694 Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
696 // Remember the source order of the inserted instruction.
698 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
702 // Insert all the dbg_values which have not already been inserted in source
705 MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI();
707 // Sort the source order instructions and use the order to insert debug
709 std::sort(Orders.begin(), Orders.end(), OrderSorter());
711 SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
712 SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
713 // Now emit the rest according to source order.
714 unsigned LastOrder = 0;
715 for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
716 unsigned Order = Orders[i].first;
717 MachineInstr *MI = Orders[i].second;
718 // Insert all SDDbgValue's whose order(s) are before "Order".
722 (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
723 if ((*DI)->isInvalidated())
725 MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap);
728 // Insert to start of the BB (after PHIs).
729 BB->insert(BBBegin, DbgMI);
731 // Insert at the instruction, which may be in a different
732 // block, if the block was split by a custom inserter.
733 MachineBasicBlock::iterator Pos = MI;
734 MI->getParent()->insert(llvm::next(Pos), DbgMI);
740 // Add trailing DbgValue's before the terminator. FIXME: May want to add
741 // some of them before one or more conditional branches?
743 MachineBasicBlock *InsertBB = Emitter.getBlock();
744 MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator();
745 if (!(*DI)->isInvalidated()) {
746 MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, VRBaseMap);
748 InsertBB->insert(Pos, DbgMI);
754 BB = Emitter.getBlock();
755 InsertPos = Emitter.getInsertPos();