1 //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAG class, which is a base class used by
11 // scheduling implementation classes.
13 //===----------------------------------------------------------------------===//
15 #include "ScheduleDAGSDNodes.h"
16 #include "InstrEmitter.h"
17 #include "SDNodeDbgValue.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/MC/MCInstrItineraries.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetLowering.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
37 #define DEBUG_TYPE "pre-RA-sched"
39 STATISTIC(LoadsClustered, "Number of loads clustered together");
41 // This allows latency based scheduler to notice high latency instructions
42 // without a target itinerary. The choise if number here has more to do with
43 // balancing scheduler heursitics than with the actual machine latency.
44 static cl::opt<int> HighLatencyCycles(
45 "sched-high-latency-cycles", cl::Hidden, cl::init(10),
46 cl::desc("Roughly estimate the number of cycles that 'long latency'"
47 "instructions take for targets with no itinerary"));
49 ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
50 : ScheduleDAG(mf), BB(nullptr), DAG(nullptr),
51 InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
53 /// Run - perform scheduling.
55 void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
59 // Clear the scheduler's SUnit DAG.
60 ScheduleDAG::clearDAG();
63 // Invoke the target's selection of scheduler.
67 /// NewSUnit - Creates a new SUnit and return a ptr to it.
69 SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) {
71 const SUnit *Addr = nullptr;
75 SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
76 assert((Addr == nullptr || Addr == &SUnits[0]) &&
77 "SUnits std::vector reallocated on the fly!");
78 SUnits.back().OrigNode = &SUnits.back();
79 SUnit *SU = &SUnits.back();
80 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
82 (N->isMachineOpcode() &&
83 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
84 SU->SchedulingPref = Sched::None;
86 SU->SchedulingPref = TLI.getSchedulingPreference(N);
90 SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
91 SUnit *SU = newSUnit(Old->getNode());
92 SU->OrigNode = Old->OrigNode;
93 SU->Latency = Old->Latency;
94 SU->isVRegCycle = Old->isVRegCycle;
95 SU->isCall = Old->isCall;
96 SU->isCallOp = Old->isCallOp;
97 SU->isTwoAddress = Old->isTwoAddress;
98 SU->isCommutable = Old->isCommutable;
99 SU->hasPhysRegDefs = Old->hasPhysRegDefs;
100 SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
101 SU->isScheduleHigh = Old->isScheduleHigh;
102 SU->isScheduleLow = Old->isScheduleLow;
103 SU->SchedulingPref = Old->SchedulingPref;
104 Old->isCloned = true;
108 /// CheckForPhysRegDependency - Check if the dependency between def and use of
109 /// a specified operand is a physical register dependency. If so, returns the
110 /// register and the cost of copying the register.
111 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
112 const TargetRegisterInfo *TRI,
113 const TargetInstrInfo *TII,
114 unsigned &PhysReg, int &Cost) {
115 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
118 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
119 if (TargetRegisterInfo::isVirtualRegister(Reg))
122 unsigned ResNo = User->getOperand(2).getResNo();
123 if (Def->isMachineOpcode()) {
124 const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
125 if (ResNo >= II.getNumDefs() &&
126 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
128 const TargetRegisterClass *RC =
129 TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo));
130 Cost = RC->getCopyCost();
135 // Helper for AddGlue to clone node operands.
136 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG,
137 SmallVectorImpl<EVT> &VTs,
138 SDValue ExtraOper = SDValue()) {
139 SmallVector<SDValue, 8> Ops;
140 for (unsigned I = 0, E = N->getNumOperands(); I != E; ++I)
141 Ops.push_back(N->getOperand(I));
143 if (ExtraOper.getNode())
144 Ops.push_back(ExtraOper);
146 SDVTList VTList = DAG->getVTList(VTs);
147 MachineSDNode::mmo_iterator Begin = nullptr, End = nullptr;
148 MachineSDNode *MN = dyn_cast<MachineSDNode>(N);
150 // Store memory references.
152 Begin = MN->memoperands_begin();
153 End = MN->memoperands_end();
156 DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops);
158 // Reset the memory references
160 MN->setMemRefs(Begin, End);
163 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
164 SmallVector<EVT, 4> VTs;
165 SDNode *GlueDestNode = Glue.getNode();
167 // Don't add glue from a node to itself.
168 if (GlueDestNode == N) return false;
170 // Don't add a glue operand to something that already uses glue.
172 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
175 // Don't add glue to something that already has a glue value.
176 if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return false;
178 for (unsigned I = 0, E = N->getNumValues(); I != E; ++I)
179 VTs.push_back(N->getValueType(I));
182 VTs.push_back(MVT::Glue);
184 CloneNodeWithValues(N, DAG, VTs, Glue);
189 // Cleanup after unsuccessful AddGlue. Use the standard method of morphing the
190 // node even though simply shrinking the value list is sufficient.
191 static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) {
192 assert((N->getValueType(N->getNumValues() - 1) == MVT::Glue &&
193 !N->hasAnyUseOfValue(N->getNumValues() - 1)) &&
194 "expected an unused glue value");
196 SmallVector<EVT, 4> VTs;
197 for (unsigned I = 0, E = N->getNumValues()-1; I != E; ++I)
198 VTs.push_back(N->getValueType(I));
200 CloneNodeWithValues(N, DAG, VTs);
203 /// ClusterNeighboringLoads - Force nearby loads together by "gluing" them.
204 /// This function finds loads of the same base and different offsets. If the
205 /// offsets are not far apart (target specific), it add MVT::Glue inputs and
206 /// outputs to ensure they are scheduled together and in order. This
207 /// optimization may benefit some targets by improving cache locality.
208 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
209 SDNode *Chain = nullptr;
210 unsigned NumOps = Node->getNumOperands();
211 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
212 Chain = Node->getOperand(NumOps-1).getNode();
216 // Look for other loads of the same chain. Find loads that are loading from
217 // the same base pointer and different offsets.
218 SmallPtrSet<SDNode*, 16> Visited;
219 SmallVector<int64_t, 4> Offsets;
220 DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
221 bool Cluster = false;
223 // This algorithm requires a reasonably low use count before finding a match
224 // to avoid uselessly blowing up compile time in large blocks.
225 unsigned UseCount = 0;
226 for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
227 I != E && UseCount < 100; ++I, ++UseCount) {
229 if (User == Node || !Visited.insert(User))
231 int64_t Offset1, Offset2;
232 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
234 // FIXME: Should be ok if they addresses are identical. But earlier
235 // optimizations really should have eliminated one of the loads.
237 if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
238 Offsets.push_back(Offset1);
239 O2SMap.insert(std::make_pair(Offset2, User));
240 Offsets.push_back(Offset2);
241 if (Offset2 < Offset1)
244 // Reset UseCount to allow more matches.
251 // Sort them in increasing order.
252 std::sort(Offsets.begin(), Offsets.end());
254 // Check if the loads are close enough.
255 SmallVector<SDNode*, 4> Loads;
256 unsigned NumLoads = 0;
257 int64_t BaseOff = Offsets[0];
258 SDNode *BaseLoad = O2SMap[BaseOff];
259 Loads.push_back(BaseLoad);
260 for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
261 int64_t Offset = Offsets[i];
262 SDNode *Load = O2SMap[Offset];
263 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
264 break; // Stop right here. Ignore loads that are further away.
265 Loads.push_back(Load);
272 // Cluster loads by adding MVT::Glue outputs and inputs. This also
273 // ensure they are scheduled in order of increasing addresses.
274 SDNode *Lead = Loads[0];
275 SDValue InGlue = SDValue(nullptr, 0);
276 if (AddGlue(Lead, InGlue, true, DAG))
277 InGlue = SDValue(Lead, Lead->getNumValues() - 1);
278 for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
279 bool OutGlue = I < E - 1;
280 SDNode *Load = Loads[I];
282 // If AddGlue fails, we could leave an unsused glue value. This should not
284 if (AddGlue(Load, InGlue, OutGlue, DAG)) {
286 InGlue = SDValue(Load, Load->getNumValues() - 1);
290 else if (!OutGlue && InGlue.getNode())
291 RemoveUnusedGlue(InGlue.getNode(), DAG);
295 /// ClusterNodes - Cluster certain nodes which should be scheduled together.
297 void ScheduleDAGSDNodes::ClusterNodes() {
298 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
299 E = DAG->allnodes_end(); NI != E; ++NI) {
301 if (!Node || !Node->isMachineOpcode())
304 unsigned Opc = Node->getMachineOpcode();
305 const MCInstrDesc &MCID = TII->get(Opc);
307 // Cluster loads from "near" addresses into combined SUnits.
308 ClusterNeighboringLoads(Node);
312 void ScheduleDAGSDNodes::BuildSchedUnits() {
313 // During scheduling, the NodeId field of SDNode is used to map SDNodes
314 // to their associated SUnits by holding SUnits table indices. A value
315 // of -1 means the SDNode does not yet have an associated SUnit.
316 unsigned NumNodes = 0;
317 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
318 E = DAG->allnodes_end(); NI != E; ++NI) {
323 // Reserve entries in the vector for each of the SUnits we are creating. This
324 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
326 // FIXME: Multiply by 2 because we may clone nodes during scheduling.
327 // This is a temporary workaround.
328 SUnits.reserve(NumNodes * 2);
330 // Add all nodes in depth first order.
331 SmallVector<SDNode*, 64> Worklist;
332 SmallPtrSet<SDNode*, 64> Visited;
333 Worklist.push_back(DAG->getRoot().getNode());
334 Visited.insert(DAG->getRoot().getNode());
336 SmallVector<SUnit*, 8> CallSUnits;
337 while (!Worklist.empty()) {
338 SDNode *NI = Worklist.pop_back_val();
340 // Add all operands to the worklist unless they've already been added.
341 for (unsigned i = 0, e = NI->getNumOperands(); i != e; ++i)
342 if (Visited.insert(NI->getOperand(i).getNode()))
343 Worklist.push_back(NI->getOperand(i).getNode());
345 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
348 // If this node has already been processed, stop now.
349 if (NI->getNodeId() != -1) continue;
351 SUnit *NodeSUnit = newSUnit(NI);
353 // See if anything is glued to this node, if so, add them to glued
354 // nodes. Nodes can have at most one glue input and one glue output. Glue
355 // is required to be the last operand and result of a node.
357 // Scan up to find glued preds.
359 while (N->getNumOperands() &&
360 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
361 N = N->getOperand(N->getNumOperands()-1).getNode();
362 assert(N->getNodeId() == -1 && "Node already inserted!");
363 N->setNodeId(NodeSUnit->NodeNum);
364 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
365 NodeSUnit->isCall = true;
368 // Scan down to find any glued succs.
370 while (N->getValueType(N->getNumValues()-1) == MVT::Glue) {
371 SDValue GlueVal(N, N->getNumValues()-1);
373 // There are either zero or one users of the Glue result.
374 bool HasGlueUse = false;
375 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
377 if (GlueVal.isOperandOf(*UI)) {
379 assert(N->getNodeId() == -1 && "Node already inserted!");
380 N->setNodeId(NodeSUnit->NodeNum);
382 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
383 NodeSUnit->isCall = true;
386 if (!HasGlueUse) break;
389 if (NodeSUnit->isCall)
390 CallSUnits.push_back(NodeSUnit);
392 // Schedule zero-latency TokenFactor below any nodes that may increase the
393 // schedule height. Otherwise, ancestors of the TokenFactor may appear to
394 // have false stalls.
395 if (NI->getOpcode() == ISD::TokenFactor)
396 NodeSUnit->isScheduleLow = true;
398 // If there are glue operands involved, N is now the bottom-most node
399 // of the sequence of nodes that are glued together.
401 NodeSUnit->setNode(N);
402 assert(N->getNodeId() == -1 && "Node already inserted!");
403 N->setNodeId(NodeSUnit->NodeNum);
405 // Compute NumRegDefsLeft. This must be done before AddSchedEdges.
406 InitNumRegDefsLeft(NodeSUnit);
408 // Assign the Latency field of NodeSUnit using target-provided information.
409 computeLatency(NodeSUnit);
412 // Find all call operands.
413 while (!CallSUnits.empty()) {
414 SUnit *SU = CallSUnits.pop_back_val();
415 for (const SDNode *SUNode = SU->getNode(); SUNode;
416 SUNode = SUNode->getGluedNode()) {
417 if (SUNode->getOpcode() != ISD::CopyToReg)
419 SDNode *SrcN = SUNode->getOperand(2).getNode();
420 if (isPassiveNode(SrcN)) continue; // Not scheduled.
421 SUnit *SrcSU = &SUnits[SrcN->getNodeId()];
422 SrcSU->isCallOp = true;
427 void ScheduleDAGSDNodes::AddSchedEdges() {
428 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
430 // Check to see if the scheduler cares about latencies.
431 bool UnitLatencies = forceUnitLatencies();
433 // Pass 2: add the preds, succs, etc.
434 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
435 SUnit *SU = &SUnits[su];
436 SDNode *MainNode = SU->getNode();
438 if (MainNode->isMachineOpcode()) {
439 unsigned Opc = MainNode->getMachineOpcode();
440 const MCInstrDesc &MCID = TII->get(Opc);
441 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
442 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
443 SU->isTwoAddress = true;
447 if (MCID.isCommutable())
448 SU->isCommutable = true;
451 // Find all predecessors and successors of the group.
452 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) {
453 if (N->isMachineOpcode() &&
454 TII->get(N->getMachineOpcode()).getImplicitDefs()) {
455 SU->hasPhysRegClobbers = true;
456 unsigned NumUsed = InstrEmitter::CountResults(N);
457 while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
458 --NumUsed; // Skip over unused values at the end.
459 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
460 SU->hasPhysRegDefs = true;
463 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
464 SDNode *OpN = N->getOperand(i).getNode();
465 if (isPassiveNode(OpN)) continue; // Not scheduled.
466 SUnit *OpSU = &SUnits[OpN->getNodeId()];
467 assert(OpSU && "Node has no SUnit!");
468 if (OpSU == SU) continue; // In the same group.
470 EVT OpVT = N->getOperand(i).getValueType();
471 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
472 bool isChain = OpVT == MVT::Other;
474 unsigned PhysReg = 0;
476 // Determine if this is a physical register dependency.
477 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
478 assert((PhysReg == 0 || !isChain) &&
479 "Chain dependence via physreg data?");
480 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
481 // emits a copy from the physical register to a virtual register unless
482 // it requires a cross class copy (cost < 0). That means we are only
483 // treating "expensive to copy" register dependency as physical register
484 // dependency. This may change in the future though.
485 if (Cost >= 0 && !StressSched)
488 // If this is a ctrl dep, latency is 1.
489 unsigned OpLatency = isChain ? 1 : OpSU->Latency;
490 // Special-case TokenFactor chains as zero-latency.
491 if(isChain && OpN->getOpcode() == ISD::TokenFactor)
494 SDep Dep = isChain ? SDep(OpSU, SDep::Barrier)
495 : SDep(OpSU, SDep::Data, PhysReg);
496 Dep.setLatency(OpLatency);
497 if (!isChain && !UnitLatencies) {
498 computeOperandLatency(OpN, N, i, Dep);
499 ST.adjustSchedDependency(OpSU, SU, Dep);
502 if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
503 // Multiple register uses are combined in the same SUnit. For example,
504 // we could have a set of glued nodes with all their defs consumed by
505 // another set of glued nodes. Register pressure tracking sees this as
506 // a single use, so to keep pressure balanced we reduce the defs.
508 // We can't tell (without more book-keeping) if this results from
509 // glued nodes or duplicate operands. As long as we don't reduce
510 // NumRegDefsLeft to zero, we handle the common cases well.
511 --OpSU->NumRegDefsLeft;
518 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
519 /// are input. This SUnit graph is similar to the SelectionDAG, but
520 /// excludes nodes that aren't interesting to scheduling, and represents
521 /// glued together nodes with a single SUnit.
522 void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) {
523 // Cluster certain nodes which should be scheduled together.
525 // Populate the SUnits array.
527 // Compute all the scheduling dependencies between nodes.
531 // Initialize NumNodeDefs for the current Node's opcode.
532 void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
533 // Check for phys reg copy.
537 if (!Node->isMachineOpcode()) {
538 if (Node->getOpcode() == ISD::CopyFromReg)
544 unsigned POpc = Node->getMachineOpcode();
545 if (POpc == TargetOpcode::IMPLICIT_DEF) {
546 // No register need be allocated for this.
550 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
551 // Some instructions define regs that are not represented in the selection DAG
552 // (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues.
553 NodeNumDefs = std::min(Node->getNumValues(), NRegDefs);
557 // Construct a RegDefIter for this SUnit and find the first valid value.
558 ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU,
559 const ScheduleDAGSDNodes *SD)
560 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
565 // Advance to the next valid value defined by the SUnit.
566 void ScheduleDAGSDNodes::RegDefIter::Advance() {
567 for (;Node;) { // Visit all glued nodes.
568 for (;DefIdx < NodeNumDefs; ++DefIdx) {
569 if (!Node->hasAnyUseOfValue(DefIdx))
571 ValueType = Node->getSimpleValueType(DefIdx);
573 return; // Found a normal regdef.
575 Node = Node->getGluedNode();
577 return; // No values left to visit.
583 void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
584 assert(SU->NumRegDefsLeft == 0 && "expect a new node");
585 for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
586 assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected");
587 ++SU->NumRegDefsLeft;
591 void ScheduleDAGSDNodes::computeLatency(SUnit *SU) {
592 SDNode *N = SU->getNode();
594 // TokenFactor operands are considered zero latency, and some schedulers
595 // (e.g. Top-Down list) may rely on the fact that operand latency is nonzero
596 // whenever node latency is nonzero.
597 if (N && N->getOpcode() == ISD::TokenFactor) {
602 // Check to see if the scheduler cares about latencies.
603 if (forceUnitLatencies()) {
608 if (!InstrItins || InstrItins->isEmpty()) {
609 if (N && N->isMachineOpcode() &&
610 TII->isHighLatencyDef(N->getMachineOpcode()))
611 SU->Latency = HighLatencyCycles;
617 // Compute the latency for the node. We use the sum of the latencies for
618 // all nodes glued together into this SUnit.
620 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
621 if (N->isMachineOpcode())
622 SU->Latency += TII->getInstrLatency(InstrItins, N);
625 void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use,
626 unsigned OpIdx, SDep& dep) const{
627 // Check to see if the scheduler cares about latencies.
628 if (forceUnitLatencies())
631 if (dep.getKind() != SDep::Data)
634 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
635 if (Use->isMachineOpcode())
636 // Adjust the use operand index by num of defs.
637 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
639 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
641 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
642 if (TargetRegisterInfo::isVirtualRegister(Reg))
643 // This copy is a liveout value. It is likely coalesced, so reduce the
644 // latency so not to penalize the def.
645 // FIXME: need target specific adjustment here?
646 Latency = (Latency > 1) ? Latency - 1 : 1;
649 dep.setLatency(Latency);
652 void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
653 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
654 if (!SU->getNode()) {
655 dbgs() << "PHYS REG COPY\n";
659 SU->getNode()->dump(DAG);
661 SmallVector<SDNode *, 4> GluedNodes;
662 for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
663 GluedNodes.push_back(N);
664 while (!GluedNodes.empty()) {
666 GluedNodes.back()->dump(DAG);
668 GluedNodes.pop_back();
673 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
674 void ScheduleDAGSDNodes::dumpSchedule() const {
675 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
676 if (SUnit *SU = Sequence[i])
679 dbgs() << "**** NOOP ****\n";
685 /// VerifyScheduledSequence - Verify that all SUnits were scheduled and that
686 /// their state is consistent with the nodes listed in Sequence.
688 void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) {
689 unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp);
691 for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
694 assert(Sequence.size() - Noops == ScheduledNodes &&
695 "The number of nodes scheduled doesn't match the expected number!");
699 /// ProcessSDDbgValues - Process SDDbgValues associated with this node.
701 ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
702 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
703 DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) {
704 if (!N->getHasDebugValue())
707 // Opportunistically insert immediate dbg_value uses, i.e. those with source
708 // order number right after the N.
709 MachineBasicBlock *BB = Emitter.getBlock();
710 MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
711 ArrayRef<SDDbgValue*> DVs = DAG->GetDbgValues(N);
712 for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
713 if (DVs[i]->isInvalidated())
715 unsigned DVOrder = DVs[i]->getOrder();
716 if (!Order || DVOrder == ++Order) {
717 MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap);
719 Orders.push_back(std::make_pair(DVOrder, DbgMI));
720 BB->insert(InsertPos, DbgMI);
722 DVs[i]->setIsInvalidated();
727 // ProcessSourceNode - Process nodes with source order numbers. These are added
728 // to a vector which EmitSchedule uses to determine how to insert dbg_value
729 // instructions in the right order.
731 ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
732 DenseMap<SDValue, unsigned> &VRBaseMap,
733 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
734 SmallSet<unsigned, 8> &Seen) {
735 unsigned Order = N->getIROrder();
736 if (!Order || !Seen.insert(Order)) {
737 // Process any valid SDDbgValues even if node does not have any order
739 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
743 MachineBasicBlock *BB = Emitter.getBlock();
744 if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI() ||
745 // Fast-isel may have inserted some instructions, in which case the
746 // BB->back().isPHI() test will not fire when we want it to.
747 std::prev(Emitter.getInsertPos())->isPHI()) {
748 // Did not insert any instruction.
749 Orders.push_back(std::make_pair(Order, (MachineInstr*)nullptr));
753 Orders.push_back(std::make_pair(Order, std::prev(Emitter.getInsertPos())));
754 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
757 void ScheduleDAGSDNodes::
758 EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
759 MachineBasicBlock::iterator InsertPos) {
760 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
762 if (I->isCtrl()) continue; // ignore chain preds
763 if (I->getSUnit()->CopyDstRC) {
764 // Copy to physical register.
765 DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit());
766 assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
767 // Find the destination physical register.
769 for (SUnit::const_succ_iterator II = SU->Succs.begin(),
770 EE = SU->Succs.end(); II != EE; ++II) {
771 if (II->isCtrl()) continue; // ignore chain preds
777 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
778 .addReg(VRI->second);
780 // Copy from physical register.
781 assert(I->getReg() && "Unknown physical register!");
782 unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
783 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
784 (void)isNew; // Silence compiler warning.
785 assert(isNew && "Node emitted out of order - early");
786 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
787 .addReg(I->getReg());
793 /// EmitSchedule - Emit the machine code in scheduled order. Return the new
794 /// InsertPos and MachineBasicBlock that contains this insertion
795 /// point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does
796 /// not necessarily refer to returned BB. The emitter may split blocks.
797 MachineBasicBlock *ScheduleDAGSDNodes::
798 EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
799 InstrEmitter Emitter(BB, InsertPos);
800 DenseMap<SDValue, unsigned> VRBaseMap;
801 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
802 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
803 SmallSet<unsigned, 8> Seen;
804 bool HasDbg = DAG->hasDebugValues();
806 // If this is the first BB, emit byval parameter dbg_value's.
807 if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
808 SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();
809 SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd();
810 for (; PDI != PDE; ++PDI) {
811 MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
813 BB->insert(InsertPos, DbgMI);
817 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
818 SUnit *SU = Sequence[i];
820 // Null SUnit* is a noop.
821 TII->insertNoop(*Emitter.getBlock(), InsertPos);
825 // For pre-regalloc scheduling, create instructions corresponding to the
826 // SDNode and any glued SDNodes and append them to the block.
827 if (!SU->getNode()) {
829 EmitPhysRegCopy(SU, CopyVRBaseMap, InsertPos);
833 SmallVector<SDNode *, 4> GluedNodes;
834 for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
835 GluedNodes.push_back(N);
836 while (!GluedNodes.empty()) {
837 SDNode *N = GluedNodes.back();
838 Emitter.EmitNode(GluedNodes.back(), SU->OrigNode != SU, SU->isCloned,
840 // Remember the source order of the inserted instruction.
842 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
843 GluedNodes.pop_back();
845 Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
847 // Remember the source order of the inserted instruction.
849 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
853 // Insert all the dbg_values which have not already been inserted in source
856 MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI();
858 // Sort the source order instructions and use the order to insert debug
860 std::sort(Orders.begin(), Orders.end(), less_first());
862 SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
863 SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
864 // Now emit the rest according to source order.
865 unsigned LastOrder = 0;
866 for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
867 unsigned Order = Orders[i].first;
868 MachineInstr *MI = Orders[i].second;
869 // Insert all SDDbgValue's whose order(s) are before "Order".
873 (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
874 if ((*DI)->isInvalidated())
876 MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap);
879 // Insert to start of the BB (after PHIs).
880 BB->insert(BBBegin, DbgMI);
882 // Insert at the instruction, which may be in a different
883 // block, if the block was split by a custom inserter.
884 MachineBasicBlock::iterator Pos = MI;
885 MI->getParent()->insert(Pos, DbgMI);
891 // Add trailing DbgValue's before the terminator. FIXME: May want to add
892 // some of them before one or more conditional branches?
893 SmallVector<MachineInstr*, 8> DbgMIs;
895 if (!(*DI)->isInvalidated())
896 if (MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap))
897 DbgMIs.push_back(DbgMI);
901 MachineBasicBlock *InsertBB = Emitter.getBlock();
902 MachineBasicBlock::iterator Pos = InsertBB->getFirstTerminator();
903 InsertBB->insert(Pos, DbgMIs.begin(), DbgMIs.end());
906 InsertPos = Emitter.getInsertPos();
907 return Emitter.getBlock();
910 /// Return the basic block label.
911 std::string ScheduleDAGSDNodes::getDAGName() const {
912 return "sunit-dag." + BB->getFullName();