1 //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAG class, which is a base class used by
11 // scheduling implementation classes.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pre-RA-sched"
16 #include "SDNodeDbgValue.h"
17 #include "ScheduleDAGSDNodes.h"
18 #include "InstrEmitter.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Target/TargetSubtarget.h"
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/ADT/SmallPtrSet.h"
27 #include "llvm/ADT/SmallSet.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
34 STATISTIC(LoadsClustered, "Number of loads clustered together");
36 ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
38 InstrItins(mf.getTarget().getInstrItineraryData()) {}
40 /// Run - perform scheduling.
42 void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb,
43 MachineBasicBlock::iterator insertPos) {
45 ScheduleDAG::Run(bb, insertPos);
48 /// NewSUnit - Creates a new SUnit and return a ptr to it.
50 SUnit *ScheduleDAGSDNodes::NewSUnit(SDNode *N) {
52 const SUnit *Addr = 0;
56 SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
57 assert((Addr == 0 || Addr == &SUnits[0]) &&
58 "SUnits std::vector reallocated on the fly!");
59 SUnits.back().OrigNode = &SUnits.back();
60 SUnit *SU = &SUnits.back();
61 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
63 (N->isMachineOpcode() &&
64 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
65 SU->SchedulingPref = Sched::None;
67 SU->SchedulingPref = TLI.getSchedulingPreference(N);
71 SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
72 SUnit *SU = NewSUnit(Old->getNode());
73 SU->OrigNode = Old->OrigNode;
74 SU->Latency = Old->Latency;
75 SU->isTwoAddress = Old->isTwoAddress;
76 SU->isCommutable = Old->isCommutable;
77 SU->hasPhysRegDefs = Old->hasPhysRegDefs;
78 SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
79 SU->SchedulingPref = Old->SchedulingPref;
84 /// CheckForPhysRegDependency - Check if the dependency between def and use of
85 /// a specified operand is a physical register dependency. If so, returns the
86 /// register and the cost of copying the register.
87 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
88 const TargetRegisterInfo *TRI,
89 const TargetInstrInfo *TII,
90 unsigned &PhysReg, int &Cost) {
91 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
94 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
95 if (TargetRegisterInfo::isVirtualRegister(Reg))
98 unsigned ResNo = User->getOperand(2).getResNo();
99 if (Def->isMachineOpcode()) {
100 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
101 if (ResNo >= II.getNumDefs() &&
102 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
104 const TargetRegisterClass *RC =
105 TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo));
106 Cost = RC->getCopyCost();
111 static void AddFlags(SDNode *N, SDValue Flag, bool AddFlag,
113 SmallVector<EVT, 4> VTs;
114 SDNode *FlagDestNode = Flag.getNode();
116 // Don't add a flag from a node to itself.
117 if (FlagDestNode == N) return;
119 // Don't add a flag to something which already has a flag.
120 if (N->getValueType(N->getNumValues() - 1) == MVT::Flag) return;
122 for (unsigned I = 0, E = N->getNumValues(); I != E; ++I)
123 VTs.push_back(N->getValueType(I));
126 VTs.push_back(MVT::Flag);
128 SmallVector<SDValue, 4> Ops;
129 for (unsigned I = 0, E = N->getNumOperands(); I != E; ++I)
130 Ops.push_back(N->getOperand(I));
135 SDVTList VTList = DAG->getVTList(&VTs[0], VTs.size());
136 MachineSDNode::mmo_iterator Begin = 0, End = 0;
137 MachineSDNode *MN = dyn_cast<MachineSDNode>(N);
139 // Store memory references.
141 Begin = MN->memoperands_begin();
142 End = MN->memoperands_end();
145 DAG->MorphNodeTo(N, N->getOpcode(), VTList, &Ops[0], Ops.size());
147 // Reset the memory references
149 MN->setMemRefs(Begin, End);
152 /// ClusterNeighboringLoads - Force nearby loads together by "flagging" them.
153 /// This function finds loads of the same base and different offsets. If the
154 /// offsets are not far apart (target specific), it add MVT::Flag inputs and
155 /// outputs to ensure they are scheduled together and in order. This
156 /// optimization may benefit some targets by improving cache locality.
157 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
159 unsigned NumOps = Node->getNumOperands();
160 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
161 Chain = Node->getOperand(NumOps-1).getNode();
165 // Look for other loads of the same chain. Find loads that are loading from
166 // the same base pointer and different offsets.
167 SmallPtrSet<SDNode*, 16> Visited;
168 SmallVector<int64_t, 4> Offsets;
169 DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
170 bool Cluster = false;
172 for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
175 if (User == Node || !Visited.insert(User))
177 int64_t Offset1, Offset2;
178 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
180 // FIXME: Should be ok if they addresses are identical. But earlier
181 // optimizations really should have eliminated one of the loads.
183 if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
184 Offsets.push_back(Offset1);
185 O2SMap.insert(std::make_pair(Offset2, User));
186 Offsets.push_back(Offset2);
187 if (Offset2 < Offset1)
195 // Sort them in increasing order.
196 std::sort(Offsets.begin(), Offsets.end());
198 // Check if the loads are close enough.
199 SmallVector<SDNode*, 4> Loads;
200 unsigned NumLoads = 0;
201 int64_t BaseOff = Offsets[0];
202 SDNode *BaseLoad = O2SMap[BaseOff];
203 Loads.push_back(BaseLoad);
204 for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
205 int64_t Offset = Offsets[i];
206 SDNode *Load = O2SMap[Offset];
207 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
208 break; // Stop right here. Ignore loads that are further away.
209 Loads.push_back(Load);
216 // Cluster loads by adding MVT::Flag outputs and inputs. This also
217 // ensure they are scheduled in order of increasing addresses.
218 SDNode *Lead = Loads[0];
219 AddFlags(Lead, SDValue(0, 0), true, DAG);
221 SDValue InFlag = SDValue(Lead, Lead->getNumValues() - 1);
222 for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
223 bool OutFlag = I < E - 1;
224 SDNode *Load = Loads[I];
226 AddFlags(Load, InFlag, OutFlag, DAG);
229 InFlag = SDValue(Load, Load->getNumValues() - 1);
235 /// ClusterNodes - Cluster certain nodes which should be scheduled together.
237 void ScheduleDAGSDNodes::ClusterNodes() {
238 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
239 E = DAG->allnodes_end(); NI != E; ++NI) {
241 if (!Node || !Node->isMachineOpcode())
244 unsigned Opc = Node->getMachineOpcode();
245 const TargetInstrDesc &TID = TII->get(Opc);
247 // Cluster loads from "near" addresses into combined SUnits.
248 ClusterNeighboringLoads(Node);
252 void ScheduleDAGSDNodes::BuildSchedUnits() {
253 // During scheduling, the NodeId field of SDNode is used to map SDNodes
254 // to their associated SUnits by holding SUnits table indices. A value
255 // of -1 means the SDNode does not yet have an associated SUnit.
256 unsigned NumNodes = 0;
257 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
258 E = DAG->allnodes_end(); NI != E; ++NI) {
263 // Reserve entries in the vector for each of the SUnits we are creating. This
264 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
266 // FIXME: Multiply by 2 because we may clone nodes during scheduling.
267 // This is a temporary workaround.
268 SUnits.reserve(NumNodes * 2);
270 // Add all nodes in depth first order.
271 SmallVector<SDNode*, 64> Worklist;
272 SmallPtrSet<SDNode*, 64> Visited;
273 Worklist.push_back(DAG->getRoot().getNode());
274 Visited.insert(DAG->getRoot().getNode());
276 while (!Worklist.empty()) {
277 SDNode *NI = Worklist.pop_back_val();
279 // Add all operands to the worklist unless they've already been added.
280 for (unsigned i = 0, e = NI->getNumOperands(); i != e; ++i)
281 if (Visited.insert(NI->getOperand(i).getNode()))
282 Worklist.push_back(NI->getOperand(i).getNode());
284 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
287 // If this node has already been processed, stop now.
288 if (NI->getNodeId() != -1) continue;
290 SUnit *NodeSUnit = NewSUnit(NI);
292 // See if anything is flagged to this node, if so, add them to flagged
293 // nodes. Nodes can have at most one flag input and one flag output. Flags
294 // are required to be the last operand and result of a node.
296 // Scan up to find flagged preds.
298 while (N->getNumOperands() &&
299 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
300 N = N->getOperand(N->getNumOperands()-1).getNode();
301 assert(N->getNodeId() == -1 && "Node already inserted!");
302 N->setNodeId(NodeSUnit->NodeNum);
305 // Scan down to find any flagged succs.
307 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
308 SDValue FlagVal(N, N->getNumValues()-1);
310 // There are either zero or one users of the Flag result.
311 bool HasFlagUse = false;
312 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
314 if (FlagVal.isOperandOf(*UI)) {
316 assert(N->getNodeId() == -1 && "Node already inserted!");
317 N->setNodeId(NodeSUnit->NodeNum);
321 if (!HasFlagUse) break;
324 // If there are flag operands involved, N is now the bottom-most node
325 // of the sequence of nodes that are flagged together.
327 NodeSUnit->setNode(N);
328 assert(N->getNodeId() == -1 && "Node already inserted!");
329 N->setNodeId(NodeSUnit->NodeNum);
331 // Assign the Latency field of NodeSUnit using target-provided information.
332 ComputeLatency(NodeSUnit);
336 void ScheduleDAGSDNodes::AddSchedEdges() {
337 const TargetSubtarget &ST = TM.getSubtarget<TargetSubtarget>();
339 // Check to see if the scheduler cares about latencies.
340 bool UnitLatencies = ForceUnitLatencies();
342 // Pass 2: add the preds, succs, etc.
343 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
344 SUnit *SU = &SUnits[su];
345 SDNode *MainNode = SU->getNode();
347 if (MainNode->isMachineOpcode()) {
348 unsigned Opc = MainNode->getMachineOpcode();
349 const TargetInstrDesc &TID = TII->get(Opc);
350 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
351 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
352 SU->isTwoAddress = true;
356 if (TID.isCommutable())
357 SU->isCommutable = true;
360 // Find all predecessors and successors of the group.
361 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
362 if (N->isMachineOpcode() &&
363 TII->get(N->getMachineOpcode()).getImplicitDefs()) {
364 SU->hasPhysRegClobbers = true;
365 unsigned NumUsed = InstrEmitter::CountResults(N);
366 while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
367 --NumUsed; // Skip over unused values at the end.
368 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
369 SU->hasPhysRegDefs = true;
372 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
373 SDNode *OpN = N->getOperand(i).getNode();
374 if (isPassiveNode(OpN)) continue; // Not scheduled.
375 SUnit *OpSU = &SUnits[OpN->getNodeId()];
376 assert(OpSU && "Node has no SUnit!");
377 if (OpSU == SU) continue; // In the same group.
379 EVT OpVT = N->getOperand(i).getValueType();
380 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
381 bool isChain = OpVT == MVT::Other;
383 unsigned PhysReg = 0;
385 // Determine if this is a physical register dependency.
386 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
387 assert((PhysReg == 0 || !isChain) &&
388 "Chain dependence via physreg data?");
389 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
390 // emits a copy from the physical register to a virtual register unless
391 // it requires a cross class copy (cost < 0). That means we are only
392 // treating "expensive to copy" register dependency as physical register
393 // dependency. This may change in the future though.
397 // If this is a ctrl dep, latency is 1.
398 unsigned OpLatency = isChain ? 1 : OpSU->Latency;
399 const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
401 if (!isChain && !UnitLatencies) {
402 ComputeOperandLatency(OpN, N, i, const_cast<SDep &>(dep));
403 ST.adjustSchedDependency(OpSU, SU, const_cast<SDep &>(dep));
412 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
413 /// are input. This SUnit graph is similar to the SelectionDAG, but
414 /// excludes nodes that aren't interesting to scheduling, and represents
415 /// flagged together nodes with a single SUnit.
416 void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) {
417 // Cluster certain nodes which should be scheduled together.
419 // Populate the SUnits array.
421 // Compute all the scheduling dependencies between nodes.
425 void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
426 // Check to see if the scheduler cares about latencies.
427 if (ForceUnitLatencies()) {
432 if (!InstrItins || InstrItins->isEmpty()) {
437 // Compute the latency for the node. We use the sum of the latencies for
438 // all nodes flagged together into this SUnit.
440 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
441 if (N->isMachineOpcode()) {
442 SU->Latency += InstrItins->
443 getStageLatency(TII->get(N->getMachineOpcode()).getSchedClass());
447 void ScheduleDAGSDNodes::ComputeOperandLatency(SDNode *Def, SDNode *Use,
448 unsigned OpIdx, SDep& dep) const{
449 // Check to see if the scheduler cares about latencies.
450 if (ForceUnitLatencies())
453 if (!InstrItins || InstrItins->isEmpty())
456 if (dep.getKind() != SDep::Data)
459 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
460 if (Def->isMachineOpcode()) {
461 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
462 if (DefIdx >= II.getNumDefs())
464 int DefCycle = InstrItins->getOperandCycle(II.getSchedClass(), DefIdx);
468 if (Use->isMachineOpcode()) {
469 const unsigned UseClass = TII->get(Use->getMachineOpcode()).getSchedClass();
470 UseCycle = InstrItins->getOperandCycle(UseClass, OpIdx);
473 int Latency = DefCycle - UseCycle + 1;
475 dep.setLatency(Latency);
480 void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
481 if (!SU->getNode()) {
482 dbgs() << "PHYS REG COPY\n";
486 SU->getNode()->dump(DAG);
488 SmallVector<SDNode *, 4> FlaggedNodes;
489 for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
490 FlaggedNodes.push_back(N);
491 while (!FlaggedNodes.empty()) {
493 FlaggedNodes.back()->dump(DAG);
495 FlaggedNodes.pop_back();
501 bool operator()(const std::pair<unsigned, MachineInstr*> &A,
502 const std::pair<unsigned, MachineInstr*> &B) {
503 return A.first < B.first;
508 // ProcessSourceNode - Process nodes with source order numbers. These are added
509 // to a vector which EmitSchedule uses to determine how to insert dbg_value
510 // instructions in the right order.
511 static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
512 InstrEmitter &Emitter,
513 DenseMap<SDValue, unsigned> &VRBaseMap,
514 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
515 SmallSet<unsigned, 8> &Seen) {
516 unsigned Order = DAG->GetOrdering(N);
517 if (!Order || !Seen.insert(Order))
520 MachineBasicBlock *BB = Emitter.getBlock();
521 if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI()) {
522 // Did not insert any instruction.
523 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
527 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
528 if (!N->getHasDebugValue())
530 // Opportunistically insert immediate dbg_value uses, i.e. those with source
531 // order number right after the N.
532 MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
533 SmallVector<SDDbgValue*,2> &DVs = DAG->GetDbgValues(N);
534 for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
535 if (DVs[i]->isInvalidated())
537 unsigned DVOrder = DVs[i]->getOrder();
538 if (DVOrder == ++Order) {
539 MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap);
541 Orders.push_back(std::make_pair(DVOrder, DbgMI));
542 BB->insert(InsertPos, DbgMI);
544 DVs[i]->setIsInvalidated();
550 /// EmitSchedule - Emit the machine code in scheduled order.
551 MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
552 InstrEmitter Emitter(BB, InsertPos);
553 DenseMap<SDValue, unsigned> VRBaseMap;
554 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
555 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
556 SmallSet<unsigned, 8> Seen;
557 bool HasDbg = DAG->hasDebugValues();
559 // If this is the first BB, emit byval parameter dbg_value's.
560 if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
561 SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();
562 SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd();
563 for (; PDI != PDE; ++PDI) {
564 MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
566 BB->insert(InsertPos, DbgMI);
570 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
571 SUnit *SU = Sequence[i];
573 // Null SUnit* is a noop.
578 // For pre-regalloc scheduling, create instructions corresponding to the
579 // SDNode and any flagged SDNodes and append them to the block.
580 if (!SU->getNode()) {
582 EmitPhysRegCopy(SU, CopyVRBaseMap);
586 SmallVector<SDNode *, 4> FlaggedNodes;
587 for (SDNode *N = SU->getNode()->getFlaggedNode(); N;
588 N = N->getFlaggedNode())
589 FlaggedNodes.push_back(N);
590 while (!FlaggedNodes.empty()) {
591 SDNode *N = FlaggedNodes.back();
592 Emitter.EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,
594 // Remember the source order of the inserted instruction.
596 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
597 FlaggedNodes.pop_back();
599 Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
601 // Remember the source order of the inserted instruction.
603 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
607 // Insert all the dbg_values which have not already been inserted in source
610 MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI();
612 // Sort the source order instructions and use the order to insert debug
614 std::sort(Orders.begin(), Orders.end(), OrderSorter());
616 SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
617 SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
618 // Now emit the rest according to source order.
619 unsigned LastOrder = 0;
620 for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
621 unsigned Order = Orders[i].first;
622 MachineInstr *MI = Orders[i].second;
623 // Insert all SDDbgValue's whose order(s) are before "Order".
627 unsigned LastDIOrder = 0;
630 (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
632 assert((*DI)->getOrder() >= LastDIOrder &&
633 "SDDbgValue nodes must be in source order!");
634 LastDIOrder = (*DI)->getOrder();
636 if ((*DI)->isInvalidated())
638 MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap);
641 // Insert to start of the BB (after PHIs).
642 BB->insert(BBBegin, DbgMI);
644 // Insert at the instruction, which may be in a different
645 // block, if the block was split by a custom inserter.
646 MachineBasicBlock::iterator Pos = MI;
647 MI->getParent()->insert(llvm::next(Pos), DbgMI);
653 // Add trailing DbgValue's before the terminator. FIXME: May want to add
654 // some of them before one or more conditional branches?
656 MachineBasicBlock *InsertBB = Emitter.getBlock();
657 MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator();
658 if (!(*DI)->isInvalidated()) {
659 MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, VRBaseMap);
661 InsertBB->insert(Pos, DbgMI);
667 BB = Emitter.getBlock();
668 InsertPos = Emitter.getInsertPos();