1 //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAG class, which is a base class used by
11 // scheduling implementation classes.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pre-RA-sched"
16 #include "SDNodeDbgValue.h"
17 #include "ScheduleDAGSDNodes.h"
18 #include "InstrEmitter.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Target/TargetSubtarget.h"
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/ADT/SmallPtrSet.h"
27 #include "llvm/ADT/SmallSet.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
34 STATISTIC(LoadsClustered, "Number of loads clustered together");
36 ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
40 /// Run - perform scheduling.
42 void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb,
43 MachineBasicBlock::iterator insertPos) {
45 ScheduleDAG::Run(bb, insertPos);
48 /// NewSUnit - Creates a new SUnit and return a ptr to it.
50 SUnit *ScheduleDAGSDNodes::NewSUnit(SDNode *N) {
52 const SUnit *Addr = 0;
56 SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
57 assert((Addr == 0 || Addr == &SUnits[0]) &&
58 "SUnits std::vector reallocated on the fly!");
59 SUnits.back().OrigNode = &SUnits.back();
60 SUnit *SU = &SUnits.back();
61 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
62 if (N->isMachineOpcode() &&
63 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)
64 SU->SchedulingPref = Sched::None;
66 SU->SchedulingPref = TLI.getSchedulingPreference(N);
70 SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
71 SUnit *SU = NewSUnit(Old->getNode());
72 SU->OrigNode = Old->OrigNode;
73 SU->Latency = Old->Latency;
74 SU->isTwoAddress = Old->isTwoAddress;
75 SU->isCommutable = Old->isCommutable;
76 SU->hasPhysRegDefs = Old->hasPhysRegDefs;
77 SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
78 SU->SchedulingPref = Old->SchedulingPref;
83 /// CheckForPhysRegDependency - Check if the dependency between def and use of
84 /// a specified operand is a physical register dependency. If so, returns the
85 /// register and the cost of copying the register.
86 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
87 const TargetRegisterInfo *TRI,
88 const TargetInstrInfo *TII,
89 unsigned &PhysReg, int &Cost) {
90 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
93 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
94 if (TargetRegisterInfo::isVirtualRegister(Reg))
97 unsigned ResNo = User->getOperand(2).getResNo();
98 if (Def->isMachineOpcode()) {
99 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
100 if (ResNo >= II.getNumDefs() &&
101 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
103 const TargetRegisterClass *RC =
104 TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo));
105 Cost = RC->getCopyCost();
110 static void AddFlags(SDNode *N, SDValue Flag, bool AddFlag,
112 SmallVector<EVT, 4> VTs;
113 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i)
114 VTs.push_back(N->getValueType(i));
116 VTs.push_back(MVT::Flag);
117 SmallVector<SDValue, 4> Ops;
118 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
119 Ops.push_back(N->getOperand(i));
122 SDVTList VTList = DAG->getVTList(&VTs[0], VTs.size());
123 DAG->MorphNodeTo(N, N->getOpcode(), VTList, &Ops[0], Ops.size());
126 /// ClusterNeighboringLoads - Force nearby loads together by "flagging" them.
127 /// This function finds loads of the same base and different offsets. If the
128 /// offsets are not far apart (target specific), it add MVT::Flag inputs and
129 /// outputs to ensure they are scheduled together and in order. This
130 /// optimization may benefit some targets by improving cache locality.
131 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
133 unsigned NumOps = Node->getNumOperands();
134 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
135 Chain = Node->getOperand(NumOps-1).getNode();
139 // Look for other loads of the same chain. Find loads that are loading from
140 // the same base pointer and different offsets.
141 SmallPtrSet<SDNode*, 16> Visited;
142 SmallVector<int64_t, 4> Offsets;
143 DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
144 bool Cluster = false;
147 for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
150 if (User == Node || !Visited.insert(User))
152 int64_t Offset1, Offset2;
153 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
155 // FIXME: Should be ok if they addresses are identical. But earlier
156 // optimizations really should have eliminated one of the loads.
158 if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
159 Offsets.push_back(Offset1);
160 O2SMap.insert(std::make_pair(Offset2, User));
161 Offsets.push_back(Offset2);
162 if (Offset2 < Offset1) {
164 BaseOffset = Offset2;
166 BaseOffset = Offset1;
174 // Sort them in increasing order.
175 std::sort(Offsets.begin(), Offsets.end());
177 // Check if the loads are close enough.
178 SmallVector<SDNode*, 4> Loads;
179 unsigned NumLoads = 0;
180 int64_t BaseOff = Offsets[0];
181 SDNode *BaseLoad = O2SMap[BaseOff];
182 Loads.push_back(BaseLoad);
183 for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
184 int64_t Offset = Offsets[i];
185 SDNode *Load = O2SMap[Offset];
186 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
187 break; // Stop right here. Ignore loads that are further away.
188 Loads.push_back(Load);
195 // Cluster loads by adding MVT::Flag outputs and inputs. This also
196 // ensure they are scheduled in order of increasing addresses.
197 SDNode *Lead = Loads[0];
198 AddFlags(Lead, SDValue(0,0), true, DAG);
199 SDValue InFlag = SDValue(Lead, Lead->getNumValues()-1);
200 for (unsigned i = 1, e = Loads.size(); i != e; ++i) {
201 bool OutFlag = i < e-1;
202 SDNode *Load = Loads[i];
203 AddFlags(Load, InFlag, OutFlag, DAG);
205 InFlag = SDValue(Load, Load->getNumValues()-1);
210 /// ClusterNodes - Cluster certain nodes which should be scheduled together.
212 void ScheduleDAGSDNodes::ClusterNodes() {
213 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
214 E = DAG->allnodes_end(); NI != E; ++NI) {
216 if (!Node || !Node->isMachineOpcode())
219 unsigned Opc = Node->getMachineOpcode();
220 const TargetInstrDesc &TID = TII->get(Opc);
222 // Cluster loads from "near" addresses into combined SUnits.
223 ClusterNeighboringLoads(Node);
227 void ScheduleDAGSDNodes::BuildSchedUnits() {
228 // During scheduling, the NodeId field of SDNode is used to map SDNodes
229 // to their associated SUnits by holding SUnits table indices. A value
230 // of -1 means the SDNode does not yet have an associated SUnit.
231 unsigned NumNodes = 0;
232 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
233 E = DAG->allnodes_end(); NI != E; ++NI) {
238 // Reserve entries in the vector for each of the SUnits we are creating. This
239 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
241 // FIXME: Multiply by 2 because we may clone nodes during scheduling.
242 // This is a temporary workaround.
243 SUnits.reserve(NumNodes * 2);
245 // Add all nodes in depth first order.
246 SmallVector<SDNode*, 64> Worklist;
247 SmallPtrSet<SDNode*, 64> Visited;
248 Worklist.push_back(DAG->getRoot().getNode());
249 Visited.insert(DAG->getRoot().getNode());
251 while (!Worklist.empty()) {
252 SDNode *NI = Worklist.pop_back_val();
254 // Add all operands to the worklist unless they've already been added.
255 for (unsigned i = 0, e = NI->getNumOperands(); i != e; ++i)
256 if (Visited.insert(NI->getOperand(i).getNode()))
257 Worklist.push_back(NI->getOperand(i).getNode());
259 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
262 // If this node has already been processed, stop now.
263 if (NI->getNodeId() != -1) continue;
265 SUnit *NodeSUnit = NewSUnit(NI);
267 // See if anything is flagged to this node, if so, add them to flagged
268 // nodes. Nodes can have at most one flag input and one flag output. Flags
269 // are required to be the last operand and result of a node.
271 // Scan up to find flagged preds.
273 while (N->getNumOperands() &&
274 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
275 N = N->getOperand(N->getNumOperands()-1).getNode();
276 assert(N->getNodeId() == -1 && "Node already inserted!");
277 N->setNodeId(NodeSUnit->NodeNum);
280 // Scan down to find any flagged succs.
282 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
283 SDValue FlagVal(N, N->getNumValues()-1);
285 // There are either zero or one users of the Flag result.
286 bool HasFlagUse = false;
287 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
289 if (FlagVal.isOperandOf(*UI)) {
291 assert(N->getNodeId() == -1 && "Node already inserted!");
292 N->setNodeId(NodeSUnit->NodeNum);
296 if (!HasFlagUse) break;
299 // If there are flag operands involved, N is now the bottom-most node
300 // of the sequence of nodes that are flagged together.
302 NodeSUnit->setNode(N);
303 assert(N->getNodeId() == -1 && "Node already inserted!");
304 N->setNodeId(NodeSUnit->NodeNum);
306 // Assign the Latency field of NodeSUnit using target-provided information.
307 ComputeLatency(NodeSUnit);
311 void ScheduleDAGSDNodes::AddSchedEdges() {
312 const TargetSubtarget &ST = TM.getSubtarget<TargetSubtarget>();
314 // Check to see if the scheduler cares about latencies.
315 bool UnitLatencies = ForceUnitLatencies();
317 // Pass 2: add the preds, succs, etc.
318 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
319 SUnit *SU = &SUnits[su];
320 SDNode *MainNode = SU->getNode();
322 if (MainNode->isMachineOpcode()) {
323 unsigned Opc = MainNode->getMachineOpcode();
324 const TargetInstrDesc &TID = TII->get(Opc);
325 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
326 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
327 SU->isTwoAddress = true;
331 if (TID.isCommutable())
332 SU->isCommutable = true;
335 // Find all predecessors and successors of the group.
336 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
337 if (N->isMachineOpcode() &&
338 TII->get(N->getMachineOpcode()).getImplicitDefs()) {
339 SU->hasPhysRegClobbers = true;
340 unsigned NumUsed = InstrEmitter::CountResults(N);
341 while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
342 --NumUsed; // Skip over unused values at the end.
343 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
344 SU->hasPhysRegDefs = true;
347 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
348 SDNode *OpN = N->getOperand(i).getNode();
349 if (isPassiveNode(OpN)) continue; // Not scheduled.
350 SUnit *OpSU = &SUnits[OpN->getNodeId()];
351 assert(OpSU && "Node has no SUnit!");
352 if (OpSU == SU) continue; // In the same group.
354 EVT OpVT = N->getOperand(i).getValueType();
355 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
356 bool isChain = OpVT == MVT::Other;
358 unsigned PhysReg = 0;
360 // Determine if this is a physical register dependency.
361 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
362 assert((PhysReg == 0 || !isChain) &&
363 "Chain dependence via physreg data?");
364 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
365 // emits a copy from the physical register to a virtual register unless
366 // it requires a cross class copy (cost < 0). That means we are only
367 // treating "expensive to copy" register dependency as physical register
368 // dependency. This may change in the future though.
372 // If this is a ctrl dep, latency is 1.
373 unsigned OpLatency = isChain ? 1 : OpSU->Latency;
374 const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
376 if (!isChain && !UnitLatencies) {
377 ComputeOperandLatency(OpN, N, i, const_cast<SDep &>(dep));
378 ST.adjustSchedDependency(OpSU, SU, const_cast<SDep &>(dep));
387 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
388 /// are input. This SUnit graph is similar to the SelectionDAG, but
389 /// excludes nodes that aren't interesting to scheduling, and represents
390 /// flagged together nodes with a single SUnit.
391 void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) {
392 // Cluster certain nodes which should be scheduled together.
394 // Populate the SUnits array.
396 // Compute all the scheduling dependencies between nodes.
400 void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
401 // Check to see if the scheduler cares about latencies.
402 if (ForceUnitLatencies()) {
407 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
408 if (InstrItins.isEmpty()) {
413 // Compute the latency for the node. We use the sum of the latencies for
414 // all nodes flagged together into this SUnit.
416 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
417 if (N->isMachineOpcode()) {
418 SU->Latency += InstrItins.
419 getStageLatency(TII->get(N->getMachineOpcode()).getSchedClass());
423 void ScheduleDAGSDNodes::ComputeOperandLatency(SDNode *Def, SDNode *Use,
424 unsigned OpIdx, SDep& dep) const{
425 // Check to see if the scheduler cares about latencies.
426 if (ForceUnitLatencies())
429 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
430 if (InstrItins.isEmpty())
433 if (dep.getKind() != SDep::Data)
436 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
437 if (Def->isMachineOpcode()) {
438 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
439 if (DefIdx >= II.getNumDefs())
441 int DefCycle = InstrItins.getOperandCycle(II.getSchedClass(), DefIdx);
445 if (Use->isMachineOpcode()) {
446 const unsigned UseClass = TII->get(Use->getMachineOpcode()).getSchedClass();
447 UseCycle = InstrItins.getOperandCycle(UseClass, OpIdx);
450 int Latency = DefCycle - UseCycle + 1;
452 dep.setLatency(Latency);
457 void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
458 if (!SU->getNode()) {
459 dbgs() << "PHYS REG COPY\n";
463 SU->getNode()->dump(DAG);
465 SmallVector<SDNode *, 4> FlaggedNodes;
466 for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
467 FlaggedNodes.push_back(N);
468 while (!FlaggedNodes.empty()) {
470 FlaggedNodes.back()->dump(DAG);
472 FlaggedNodes.pop_back();
478 bool operator()(const std::pair<unsigned, MachineInstr*> &A,
479 const std::pair<unsigned, MachineInstr*> &B) {
480 return A.first < B.first;
485 // ProcessSourceNode - Process nodes with source order numbers. These are added
486 // to a vector which EmitSchedule use to determine how to insert dbg_value
487 // instructions in the right order.
488 static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
489 InstrEmitter &Emitter,
490 DenseMap<SDValue, unsigned> &VRBaseMap,
491 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
492 SmallSet<unsigned, 8> &Seen) {
493 unsigned Order = DAG->GetOrdering(N);
494 if (!Order || !Seen.insert(Order))
497 MachineBasicBlock *BB = Emitter.getBlock();
498 if (BB->empty() || BB->back().isPHI()) {
499 // Did not insert any instruction.
500 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
504 Orders.push_back(std::make_pair(Order, &BB->back()));
505 if (!N->getHasDebugValue())
507 // Opportunistically insert immediate dbg_value uses, i.e. those with source
508 // order number right after the N.
509 MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
510 SmallVector<SDDbgValue*,2> &DVs = DAG->GetDbgValues(N);
511 for (unsigned i = 0, e = DVs.size(); i != e; ++i) {
512 if (DVs[i]->isInvalidated())
514 unsigned DVOrder = DVs[i]->getOrder();
515 if (DVOrder == ++Order) {
516 MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap);
518 Orders.push_back(std::make_pair(DVOrder, DbgMI));
519 BB->insert(InsertPos, DbgMI);
521 DVs[i]->setIsInvalidated();
527 /// EmitSchedule - Emit the machine code in scheduled order.
528 MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
529 InstrEmitter Emitter(BB, InsertPos);
530 DenseMap<SDValue, unsigned> VRBaseMap;
531 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
532 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
533 SmallSet<unsigned, 8> Seen;
534 bool HasDbg = DAG->hasDebugValues();
536 // If this is the first BB, emit byval parameter dbg_value's.
537 if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
538 SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();
539 SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd();
540 for (; PDI != PDE; ++PDI) {
541 MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
543 BB->insert(BB->end(), DbgMI);
547 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
548 SUnit *SU = Sequence[i];
550 // Null SUnit* is a noop.
555 // For pre-regalloc scheduling, create instructions corresponding to the
556 // SDNode and any flagged SDNodes and append them to the block.
557 if (!SU->getNode()) {
559 EmitPhysRegCopy(SU, CopyVRBaseMap);
563 SmallVector<SDNode *, 4> FlaggedNodes;
564 for (SDNode *N = SU->getNode()->getFlaggedNode(); N;
565 N = N->getFlaggedNode())
566 FlaggedNodes.push_back(N);
567 while (!FlaggedNodes.empty()) {
568 SDNode *N = FlaggedNodes.back();
569 Emitter.EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,
571 // Remember the source order of the inserted instruction.
573 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
574 FlaggedNodes.pop_back();
576 Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
578 // Remember the source order of the inserted instruction.
580 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
584 // Insert all the dbg_values which have not already been inserted in source
587 MachineBasicBlock::iterator BBBegin = BB->empty() ? BB->end() : BB->begin();
588 while (BBBegin != BB->end() && BBBegin->isPHI())
591 // Sort the source order instructions and use the order to insert debug
593 std::sort(Orders.begin(), Orders.end(), OrderSorter());
595 SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
596 SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
597 // Now emit the rest according to source order.
598 unsigned LastOrder = 0;
599 MachineInstr *LastMI = 0;
600 for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
601 unsigned Order = Orders[i].first;
602 MachineInstr *MI = Orders[i].second;
603 // Insert all SDDbgValue's whose order(s) are before "Order".
606 MachineBasicBlock *MIBB = MI->getParent();
608 unsigned LastDIOrder = 0;
611 (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) {
613 assert((*DI)->getOrder() >= LastDIOrder &&
614 "SDDbgValue nodes must be in source order!");
615 LastDIOrder = (*DI)->getOrder();
617 if ((*DI)->isInvalidated())
619 MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap);
622 // Insert to start of the BB (after PHIs).
623 BB->insert(BBBegin, DbgMI);
625 MachineBasicBlock::iterator Pos = MI;
626 MIBB->insert(llvm::next(Pos), DbgMI);
633 // Add trailing DbgValue's before the terminator. FIXME: May want to add
634 // some of them before one or more conditional branches?
636 MachineBasicBlock *InsertBB = Emitter.getBlock();
637 MachineBasicBlock::iterator Pos= Emitter.getBlock()->getFirstTerminator();
638 if (!(*DI)->isInvalidated()) {
639 MachineInstr *DbgMI= Emitter.EmitDbgValue(*DI, VRBaseMap);
641 InsertBB->insert(Pos, DbgMI);
647 BB = Emitter.getBlock();
648 InsertPos = Emitter.getInsertPos();