1 //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the ScheduleDAG class, which is a base class used by
11 // scheduling implementation classes.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pre-RA-sched"
16 #include "llvm/CodeGen/ScheduleDAGSDNodes.h"
17 #include "llvm/CodeGen/SelectionDAG.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
25 ScheduleDAGSDNodes::ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb,
26 const TargetMachine &tm)
27 : ScheduleDAG(dag, bb, tm) {
30 SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
31 SUnit *SU = NewSUnit(Old->getNode());
32 SU->OrigNode = Old->OrigNode;
33 SU->Latency = Old->Latency;
34 SU->isTwoAddress = Old->isTwoAddress;
35 SU->isCommutable = Old->isCommutable;
36 SU->hasPhysRegDefs = Old->hasPhysRegDefs;
40 /// CheckForPhysRegDependency - Check if the dependency between def and use of
41 /// a specified operand is a physical register dependency. If so, returns the
42 /// register and the cost of copying the register.
43 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
44 const TargetRegisterInfo *TRI,
45 const TargetInstrInfo *TII,
46 unsigned &PhysReg, int &Cost) {
47 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
50 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
51 if (TargetRegisterInfo::isVirtualRegister(Reg))
54 unsigned ResNo = User->getOperand(2).getResNo();
55 if (Def->isMachineOpcode()) {
56 const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
57 if (ResNo >= II.getNumDefs() &&
58 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
60 const TargetRegisterClass *RC =
61 TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo));
62 Cost = RC->getCopyCost();
67 void ScheduleDAGSDNodes::BuildSchedUnits() {
68 // During scheduling, the NodeId field of SDNode is used to map SDNodes
69 // to their associated SUnits by holding SUnits table indices. A value
70 // of -1 means the SDNode does not yet have an associated SUnit.
71 unsigned NumNodes = 0;
72 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
73 E = DAG->allnodes_end(); NI != E; ++NI) {
78 // Reserve entries in the vector for each of the SUnits we are creating. This
79 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
81 // FIXME: Multiply by 2 because we may clone nodes during scheduling.
82 // This is a temporary workaround.
83 SUnits.reserve(NumNodes * 2);
85 // Check to see if the scheduler cares about latencies.
86 bool UnitLatencies = ForceUnitLatencies();
88 for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
89 E = DAG->allnodes_end(); NI != E; ++NI) {
90 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
93 // If this node has already been processed, stop now.
94 if (NI->getNodeId() != -1) continue;
96 SUnit *NodeSUnit = NewSUnit(NI);
98 // See if anything is flagged to this node, if so, add them to flagged
99 // nodes. Nodes can have at most one flag input and one flag output. Flags
100 // are required the be the last operand and result of a node.
102 // Scan up to find flagged preds.
104 if (N->getNumOperands() &&
105 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
107 N = N->getOperand(N->getNumOperands()-1).getNode();
108 assert(N->getNodeId() == -1 && "Node already inserted!");
109 N->setNodeId(NodeSUnit->NodeNum);
110 } while (N->getNumOperands() &&
111 N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
114 // Scan down to find any flagged succs.
116 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
117 SDValue FlagVal(N, N->getNumValues()-1);
119 // There are either zero or one users of the Flag result.
120 bool HasFlagUse = false;
121 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
123 if (FlagVal.isOperandOf(*UI)) {
125 assert(N->getNodeId() == -1 && "Node already inserted!");
126 N->setNodeId(NodeSUnit->NodeNum);
130 if (!HasFlagUse) break;
133 // If there are flag operands involved, N is now the bottom-most node
134 // of the sequence of nodes that are flagged together.
136 NodeSUnit->setNode(N);
137 assert(N->getNodeId() == -1 && "Node already inserted!");
138 N->setNodeId(NodeSUnit->NodeNum);
140 // Assign the Latency field of NodeSUnit using target-provided information.
142 NodeSUnit->Latency = 1;
144 ComputeLatency(NodeSUnit);
148 void ScheduleDAGSDNodes::AddSchedEdges() {
149 // Pass 2: add the preds, succs, etc.
150 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
151 SUnit *SU = &SUnits[su];
152 SDNode *MainNode = SU->getNode();
154 if (MainNode->isMachineOpcode()) {
155 unsigned Opc = MainNode->getMachineOpcode();
156 const TargetInstrDesc &TID = TII->get(Opc);
157 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
158 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
159 SU->isTwoAddress = true;
163 if (TID.isCommutable())
164 SU->isCommutable = true;
167 // Find all predecessors and successors of the group.
168 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
169 if (N->isMachineOpcode() &&
170 TII->get(N->getMachineOpcode()).getImplicitDefs() &&
171 CountResults(N) > TII->get(N->getMachineOpcode()).getNumDefs())
172 SU->hasPhysRegDefs = true;
174 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
175 SDNode *OpN = N->getOperand(i).getNode();
176 if (isPassiveNode(OpN)) continue; // Not scheduled.
177 SUnit *OpSU = &SUnits[OpN->getNodeId()];
178 assert(OpSU && "Node has no SUnit!");
179 if (OpSU == SU) continue; // In the same group.
181 MVT OpVT = N->getOperand(i).getValueType();
182 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
183 bool isChain = OpVT == MVT::Other;
185 unsigned PhysReg = 0;
187 // Determine if this is a physical register dependency.
188 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
189 assert((PhysReg == 0 || !isChain) &&
190 "Chain dependence via physreg data?");
191 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
192 // emits a copy from the physical register to a virtual register unless
193 // it requires a cross class copy (cost < 0). That means we are only
194 // treating "expensive to copy" register dependency as physical register
195 // dependency. This may change in the future though.
198 SU->addPred(SDep(OpSU, isChain ? SDep::Order : SDep::Data,
199 OpSU->Latency, PhysReg));
205 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
206 /// are input. This SUnit graph is similar to the SelectionDAG, but
207 /// excludes nodes that aren't interesting to scheduling, and represents
208 /// flagged together nodes with a single SUnit.
209 void ScheduleDAGSDNodes::BuildSchedGraph() {
210 // Populate the SUnits array.
212 // Compute all the scheduling dependencies between nodes.
216 void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
217 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
219 // Compute the latency for the node. We use the sum of the latencies for
220 // all nodes flagged together into this SUnit.
222 bool SawMachineOpcode = false;
223 for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
224 if (N->isMachineOpcode()) {
225 SawMachineOpcode = true;
227 InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass());
231 /// CountResults - The results of target nodes have register or immediate
232 /// operands first, then an optional chain, and optional flag operands (which do
233 /// not go into the resulting MachineInstr).
234 unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
235 unsigned N = Node->getNumValues();
236 while (N && Node->getValueType(N - 1) == MVT::Flag)
238 if (N && Node->getValueType(N - 1) == MVT::Other)
239 --N; // Skip over chain result.
243 /// CountOperands - The inputs to target nodes have any actual inputs first,
244 /// followed by special operands that describe memory references, then an
245 /// optional chain operand, then an optional flag operand. Compute the number
246 /// of actual operands that will go into the resulting MachineInstr.
247 unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) {
248 unsigned N = ComputeMemOperandsEnd(Node);
249 while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode()))
250 --N; // Ignore MEMOPERAND nodes
254 /// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode
256 unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
257 unsigned N = Node->getNumOperands();
258 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
260 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
261 --N; // Ignore chain if it exists.
266 void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
267 if (!SU->getNode()) {
268 cerr << "PHYS REG COPY\n";
272 SU->getNode()->dump(DAG);
274 SmallVector<SDNode *, 4> FlaggedNodes;
275 for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
276 FlaggedNodes.push_back(N);
277 while (!FlaggedNodes.empty()) {
279 FlaggedNodes.back()->dump(DAG);
281 FlaggedNodes.pop_back();