1 //===---- ScheduleDAGSDNodes.h - SDNode Scheduling --------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGSDNodes class, which implements
11 // scheduling for an SDNode-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H
16 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/ScheduleDAG.h"
22 /// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
24 /// Edges between SUnits are initially based on edges in the SelectionDAG,
25 /// and additional edges can be added by the schedulers as heuristics.
26 /// SDNodes such as Constants, Registers, and a few others that are not
27 /// interesting to schedulers are not allocated SUnits.
29 /// SDNodes with MVT::Glue operands are grouped along with the flagged
30 /// nodes into a single SUnit so that they are scheduled together.
32 /// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
33 /// edges. Physical register dependence information is not carried in
34 /// the DAG and must be handled explicitly by schedulers.
36 class ScheduleDAGSDNodes : public ScheduleDAG {
38 MachineBasicBlock *BB;
39 SelectionDAG *DAG; // DAG of the current basic block
40 const InstrItineraryData *InstrItins;
42 /// The schedule. Null SUnit*'s represent noop instructions.
43 std::vector<SUnit*> Sequence;
45 explicit ScheduleDAGSDNodes(MachineFunction &mf);
47 ~ScheduleDAGSDNodes() override {}
49 /// Run - perform scheduling.
51 void Run(SelectionDAG *dag, MachineBasicBlock *bb);
53 /// isPassiveNode - Return true if the node is a non-scheduled leaf.
55 static bool isPassiveNode(SDNode *Node) {
56 if (isa<ConstantSDNode>(Node)) return true;
57 if (isa<ConstantFPSDNode>(Node)) return true;
58 if (isa<RegisterSDNode>(Node)) return true;
59 if (isa<RegisterMaskSDNode>(Node)) return true;
60 if (isa<GlobalAddressSDNode>(Node)) return true;
61 if (isa<BasicBlockSDNode>(Node)) return true;
62 if (isa<FrameIndexSDNode>(Node)) return true;
63 if (isa<ConstantPoolSDNode>(Node)) return true;
64 if (isa<TargetIndexSDNode>(Node)) return true;
65 if (isa<JumpTableSDNode>(Node)) return true;
66 if (isa<ExternalSymbolSDNode>(Node)) return true;
67 if (isa<MCSymbolSDNode>(Node)) return true;
68 if (isa<BlockAddressSDNode>(Node)) return true;
69 if (Node->getOpcode() == ISD::EntryToken ||
70 isa<MDNodeSDNode>(Node)) return true;
74 /// NewSUnit - Creates a new SUnit and return a ptr to it.
76 SUnit *newSUnit(SDNode *N);
78 /// Clone - Creates a clone of the specified SUnit. It does not copy the
79 /// predecessors / successors info nor the temporary scheduling states.
81 SUnit *Clone(SUnit *N);
83 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
84 /// are input. This SUnit graph is similar to the SelectionDAG, but
85 /// excludes nodes that aren't interesting to scheduling, and represents
86 /// flagged together nodes with a single SUnit.
87 void BuildSchedGraph(AliasAnalysis *AA);
89 /// InitVRegCycleFlag - Set isVRegCycle if this node's single use is
90 /// CopyToReg and its only active data operands are CopyFromReg within a
91 /// single block loop.
93 void InitVRegCycleFlag(SUnit *SU);
95 /// InitNumRegDefsLeft - Determine the # of regs defined by this node.
97 void InitNumRegDefsLeft(SUnit *SU);
99 /// computeLatency - Compute node latency.
101 virtual void computeLatency(SUnit *SU);
103 virtual void computeOperandLatency(SDNode *Def, SDNode *Use,
104 unsigned OpIdx, SDep& dep) const;
106 /// Schedule - Order nodes according to selected style, filling
107 /// in the Sequence member.
109 virtual void Schedule() = 0;
111 /// VerifyScheduledSequence - Verify that all SUnits are scheduled and
112 /// consistent with the Sequence of scheduled instructions.
113 void VerifyScheduledSequence(bool isBottomUp);
115 /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
116 /// according to the order specified in Sequence.
118 virtual MachineBasicBlock*
119 EmitSchedule(MachineBasicBlock::iterator &InsertPos);
121 void dumpNode(const SUnit *SU) const override;
123 void dumpSchedule() const;
125 std::string getGraphNodeLabel(const SUnit *SU) const override;
127 std::string getDAGName() const override;
129 virtual void getCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const;
131 /// RegDefIter - In place iteration over the values defined by an
132 /// SUnit. This does not need copies of the iterator or any other STLisms.
133 /// The iterator creates itself, rather than being provided by the SchedDAG.
135 const ScheduleDAGSDNodes *SchedDAG;
138 unsigned NodeNumDefs;
141 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
143 bool IsValid() const { return Node != nullptr; }
145 MVT GetValue() const {
146 assert(IsValid() && "bad iterator");
150 const SDNode *GetNode() const {
154 unsigned GetIdx() const {
160 void InitNodeNumDefs();
164 /// ForceUnitLatencies - Return true if all scheduling edges should be given
165 /// a latency value of one. The default is to return false; schedulers may
166 /// override this as needed.
167 virtual bool forceUnitLatencies() const { return false; }
170 /// ClusterNeighboringLoads - Cluster loads from "near" addresses into
172 void ClusterNeighboringLoads(SDNode *Node);
173 /// ClusterNodes - Cluster certain nodes which should be scheduled together.
177 /// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.
178 void BuildSchedUnits();
179 void AddSchedEdges();
181 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
182 MachineBasicBlock::iterator InsertPos);