1 //===---- ScheduleDAGSDNodes.h - SDNode Scheduling --------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAGSDNodes class, which implements
11 // scheduling for an SDNode-based dependency graph.
13 //===----------------------------------------------------------------------===//
15 #ifndef SCHEDULEDAGSDNODES_H
16 #define SCHEDULEDAGSDNODES_H
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
22 /// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
24 /// Edges between SUnits are initially based on edges in the SelectionDAG,
25 /// and additional edges can be added by the schedulers as heuristics.
26 /// SDNodes such as Constants, Registers, and a few others that are not
27 /// interesting to schedulers are not allocated SUnits.
29 /// SDNodes with MVT::Flag operands are grouped along with the flagged
30 /// nodes into a single SUnit so that they are scheduled together.
32 /// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
33 /// edges. Physical register dependence information is not carried in
34 /// the DAG and must be handled explicitly by schedulers.
36 class ScheduleDAGSDNodes : public ScheduleDAG {
38 explicit ScheduleDAGSDNodes(MachineFunction &mf);
40 virtual ~ScheduleDAGSDNodes() {}
42 /// isPassiveNode - Return true if the node is a non-scheduled leaf.
44 static bool isPassiveNode(SDNode *Node) {
45 if (isa<ConstantSDNode>(Node)) return true;
46 if (isa<ConstantFPSDNode>(Node)) return true;
47 if (isa<RegisterSDNode>(Node)) return true;
48 if (isa<GlobalAddressSDNode>(Node)) return true;
49 if (isa<BasicBlockSDNode>(Node)) return true;
50 if (isa<FrameIndexSDNode>(Node)) return true;
51 if (isa<ConstantPoolSDNode>(Node)) return true;
52 if (isa<JumpTableSDNode>(Node)) return true;
53 if (isa<ExternalSymbolSDNode>(Node)) return true;
54 if (isa<MemOperandSDNode>(Node)) return true;
55 if (Node->getOpcode() == ISD::EntryToken) return true;
59 /// NewSUnit - Creates a new SUnit and return a ptr to it.
61 SUnit *NewSUnit(SDNode *N) {
63 const SUnit *Addr = 0;
67 SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
68 assert((Addr == 0 || Addr == &SUnits[0]) &&
69 "SUnits std::vector reallocated on the fly!");
70 SUnits.back().OrigNode = &SUnits.back();
71 return &SUnits.back();
74 /// Clone - Creates a clone of the specified SUnit. It does not copy the
75 /// predecessors / successors info nor the temporary scheduling states.
77 SUnit *Clone(SUnit *N);
79 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
80 /// are input. This SUnit graph is similar to the SelectionDAG, but
81 /// excludes nodes that aren't interesting to scheduling, and represents
82 /// flagged together nodes with a single SUnit.
83 virtual void BuildSchedGraph();
85 /// ComputeLatency - Compute node latency.
87 virtual void ComputeLatency(SUnit *SU);
89 /// CountResults - The results of target nodes have register or immediate
90 /// operands first, then an optional chain, and optional flag operands
91 /// (which do not go into the machine instrs.)
92 static unsigned CountResults(SDNode *Node);
94 /// CountOperands - The inputs to target nodes have any actual inputs first,
95 /// followed by special operands that describe memory references, then an
96 /// optional chain operand, then flag operands. Compute the number of
97 /// actual operands that will go into the resulting MachineInstr.
98 static unsigned CountOperands(SDNode *Node);
100 /// ComputeMemOperandsEnd - Find the index one past the last
101 /// MemOperandSDNode operand
102 static unsigned ComputeMemOperandsEnd(SDNode *Node);
104 /// EmitNode - Generate machine code for an node and needed dependencies.
105 /// VRBaseMap contains, for each already emitted node, the first virtual
106 /// register number for the results of the node.
108 void EmitNode(SDNode *Node, bool IsClone, bool HasClone,
109 DenseMap<SDValue, unsigned> &VRBaseMap);
111 virtual MachineBasicBlock *EmitSchedule();
113 /// Schedule - Order nodes according to selected style, filling
114 /// in the Sequence member.
116 virtual void Schedule() = 0;
118 virtual void dumpNode(const SUnit *SU) const;
120 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
122 virtual void getCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const;
125 /// EmitSubregNode - Generate machine code for subreg nodes.
127 void EmitSubregNode(SDNode *Node,
128 DenseMap<SDValue, unsigned> &VRBaseMap);
130 /// getVR - Return the virtual register corresponding to the specified result
131 /// of the specified node.
132 unsigned getVR(SDValue Op, DenseMap<SDValue, unsigned> &VRBaseMap);
134 /// getDstOfCopyToRegUse - If the only use of the specified result number of
135 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
136 unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
138 void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum,
139 const TargetInstrDesc *II,
140 DenseMap<SDValue, unsigned> &VRBaseMap);
142 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
143 /// implicit physical register output.
144 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
145 bool IsCloned, unsigned SrcReg,
146 DenseMap<SDValue, unsigned> &VRBaseMap);
148 void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
149 const TargetInstrDesc &II, bool IsClone,
151 DenseMap<SDValue, unsigned> &VRBaseMap);
153 /// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.
154 void BuildSchedUnits();
155 void AddSchedEdges();