1 //===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the ScheduleDAG class, which creates
11 // MachineInstrs according to the computed schedule.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pre-RA-sched"
16 #include "ScheduleDAGSDNodes.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
31 /// getInstrOperandRegClass - Return register class of the operand of an
32 /// instruction of the specified TargetInstrDesc.
33 static const TargetRegisterClass*
34 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
35 const TargetInstrDesc &II, unsigned Op) {
36 if (Op >= II.getNumOperands()) {
37 assert(II.isVariadic() && "Invalid operand # of instruction");
40 if (II.OpInfo[Op].isLookupPtrRegClass())
41 return TRI->getPointerRegClass();
42 return TRI->getRegClass(II.OpInfo[Op].RegClass);
45 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
46 /// implicit physical register output.
47 void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
48 bool IsClone, bool IsCloned,
50 DenseMap<SDValue, unsigned> &VRBaseMap) {
52 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
53 // Just use the input register directly!
54 SDValue Op(Node, ResNo);
57 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
58 isNew = isNew; // Silence compiler warning.
59 assert(isNew && "Node emitted out of order - early");
63 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
64 // the CopyToReg'd destination register instead of creating a new vreg.
66 const TargetRegisterClass *UseRC = NULL;
67 if (!IsClone && !IsCloned)
68 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
72 if (User->getOpcode() == ISD::CopyToReg &&
73 User->getOperand(2).getNode() == Node &&
74 User->getOperand(2).getResNo() == ResNo) {
75 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
76 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
79 } else if (DestReg != SrcReg)
82 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
83 SDValue Op = User->getOperand(i);
84 if (Op.getNode() != Node || Op.getResNo() != ResNo)
86 MVT VT = Node->getValueType(Op.getResNo());
87 if (VT == MVT::Other || VT == MVT::Flag)
90 if (User->isMachineOpcode()) {
91 const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
92 const TargetRegisterClass *RC =
93 getInstrOperandRegClass(TRI, II, i+II.getNumDefs());
97 if (UseRC->hasSuperClass(RC))
100 assert((UseRC == RC || RC->hasSuperClass(UseRC)) &&
101 "Multiple uses expecting different register classes!");
111 MVT VT = Node->getValueType(ResNo);
112 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
113 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
115 // Figure out the register class to create for the destreg.
117 DstRC = MRI.getRegClass(VRBase);
119 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
122 DstRC = TLI->getRegClassFor(VT);
125 // If all uses are reading from the src physical register and copying the
126 // register is either impossible or very expensive, then don't create a copy.
127 if (MatchReg && SrcRC->getCopyCost() < 0) {
130 // Create the reg, emit the copy.
131 VRBase = MRI.createVirtualRegister(DstRC);
132 bool Emitted = TII->copyRegToReg(*BB, InsertPos, VRBase, SrcReg,
134 // If the target didn't handle the copy with different register
135 // classes and the destination is a subset of the source,
136 // try a normal same-RC copy.
137 if (!Emitted && DstRC->hasSuperClass(SrcRC))
138 Emitted = TII->copyRegToReg(*BB, InsertPos, VRBase, SrcReg,
141 assert(Emitted && "Unable to issue a copy instruction!\n");
144 SDValue Op(Node, ResNo);
147 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
148 isNew = isNew; // Silence compiler warning.
149 assert(isNew && "Node emitted out of order - early");
152 /// getDstOfCopyToRegUse - If the only use of the specified result number of
153 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
154 unsigned ScheduleDAGSDNodes::getDstOfOnlyCopyToRegUse(SDNode *Node,
155 unsigned ResNo) const {
156 if (!Node->hasOneUse())
159 SDNode *User = *Node->use_begin();
160 if (User->getOpcode() == ISD::CopyToReg &&
161 User->getOperand(2).getNode() == Node &&
162 User->getOperand(2).getResNo() == ResNo) {
163 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
164 if (TargetRegisterInfo::isVirtualRegister(Reg))
170 void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
171 const TargetInstrDesc &II,
172 bool IsClone, bool IsCloned,
173 DenseMap<SDValue, unsigned> &VRBaseMap) {
174 assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
175 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
177 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
178 // If the specific node value is only used by a CopyToReg and the dest reg
179 // is a vreg in the same register class, use the CopyToReg'd destination
180 // register instead of creating a new vreg.
182 const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, II, i);
184 if (!IsClone && !IsCloned)
185 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
188 if (User->getOpcode() == ISD::CopyToReg &&
189 User->getOperand(2).getNode() == Node &&
190 User->getOperand(2).getResNo() == i) {
191 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
192 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
193 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
196 MI->addOperand(MachineOperand::CreateReg(Reg, true));
203 // Create the result registers for this node and add the result regs to
204 // the machine instruction.
206 assert(RC && "Isn't a register operand!");
207 VRBase = MRI.createVirtualRegister(RC);
208 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
214 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
215 isNew = isNew; // Silence compiler warning.
216 assert(isNew && "Node emitted out of order - early");
220 /// getVR - Return the virtual register corresponding to the specified result
221 /// of the specified node.
222 unsigned ScheduleDAGSDNodes::getVR(SDValue Op,
223 DenseMap<SDValue, unsigned> &VRBaseMap) {
224 if (Op.isMachineOpcode() &&
225 Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
226 // Add an IMPLICIT_DEF instruction before every use.
227 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
228 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
229 // does not include operand register class info.
231 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
232 VReg = MRI.createVirtualRegister(RC);
234 BuildMI(BB, Op.getDebugLoc(), TII->get(TargetInstrInfo::IMPLICIT_DEF),VReg);
238 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
239 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
244 /// AddRegisterOperand - Add the specified register as an operand to the
245 /// specified machine instr. Insert register copies if the register is
246 /// not in the required register class.
248 ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op,
250 const TargetInstrDesc *II,
251 DenseMap<SDValue, unsigned> &VRBaseMap) {
252 assert(Op.getValueType() != MVT::Other &&
253 Op.getValueType() != MVT::Flag &&
254 "Chain and flag operands should occur at end of operand list!");
255 // Get/emit the operand.
256 unsigned VReg = getVR(Op, VRBaseMap);
257 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
259 const TargetInstrDesc &TID = MI->getDesc();
260 bool isOptDef = IIOpNum < TID.getNumOperands() &&
261 TID.OpInfo[IIOpNum].isOptionalDef();
263 // If the instruction requires a register in a different class, create
264 // a new virtual register and copy the value into it.
266 const TargetRegisterClass *SrcRC =
267 MRI.getRegClass(VReg);
268 const TargetRegisterClass *DstRC =
269 getInstrOperandRegClass(TRI, *II, IIOpNum);
270 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
271 "Don't have operand info for this instruction!");
272 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
273 unsigned NewVReg = MRI.createVirtualRegister(DstRC);
274 bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
276 // If the target didn't handle the copy with different register
277 // classes and the destination is a subset of the source,
278 // try a normal same-RC copy.
279 if (!Emitted && DstRC->hasSuperClass(SrcRC))
280 Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
282 assert(Emitted && "Unable to issue a copy instruction!\n");
287 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
290 /// AddOperand - Add the specified operand to the specified machine instr. II
291 /// specifies the instruction information for the node, and IIOpNum is the
292 /// operand number (in the II) that we are adding. IIOpNum and II are used for
294 void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
296 const TargetInstrDesc *II,
297 DenseMap<SDValue, unsigned> &VRBaseMap) {
298 if (Op.isMachineOpcode()) {
299 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
300 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
301 MI->addOperand(MachineOperand::CreateImm(C->getZExtValue()));
302 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
303 const ConstantFP *CFP = F->getConstantFPValue();
304 MI->addOperand(MachineOperand::CreateFPImm(CFP));
305 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
306 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
307 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
308 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
309 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
310 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
311 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
312 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
313 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
314 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex()));
315 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
316 int Offset = CP->getOffset();
317 unsigned Align = CP->getAlignment();
318 const Type *Type = CP->getType();
319 // MachineConstantPool wants an explicit alignment.
321 Align = TM.getTargetData()->getPrefTypeAlignment(Type);
323 // Alignment of vector types. FIXME!
324 Align = TM.getTargetData()->getTypePaddedSize(Type);
329 if (CP->isMachineConstantPoolEntry())
330 Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
332 Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
333 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
334 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
335 MI->addOperand(MachineOperand::CreateES(ES->getSymbol()));
337 assert(Op.getValueType() != MVT::Other &&
338 Op.getValueType() != MVT::Flag &&
339 "Chain and flag operands should occur at end of operand list!");
340 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
344 /// getSubRegisterRegClass - Returns the register class of specified register
345 /// class' "SubIdx"'th sub-register class.
346 static const TargetRegisterClass*
347 getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx) {
348 // Pick the register class of the subregister
349 TargetRegisterInfo::regclass_iterator I =
350 TRC->subregclasses_begin() + SubIdx-1;
351 assert(I < TRC->subregclasses_end() &&
352 "Invalid subregister index for register class");
356 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
357 /// "SubIdx"'th sub-register class is the specified register class and whose
358 /// type matches the specified type.
359 static const TargetRegisterClass*
360 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
361 unsigned SubIdx, MVT VT) {
362 // Pick the register class of the superegister for this type
363 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
364 E = TRC->superregclasses_end(); I != E; ++I)
365 if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
367 assert(false && "Couldn't find the register class");
371 /// EmitSubregNode - Generate machine code for subreg nodes.
373 void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
374 DenseMap<SDValue, unsigned> &VRBaseMap) {
376 unsigned Opc = Node->getMachineOpcode();
378 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
379 // the CopyToReg'd destination register instead of creating a new vreg.
380 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
383 if (User->getOpcode() == ISD::CopyToReg &&
384 User->getOperand(2).getNode() == Node) {
385 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
386 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
393 if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
394 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
396 // Create the extract_subreg machine instruction.
397 MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(),
398 TII->get(TargetInstrInfo::EXTRACT_SUBREG));
400 // Figure out the register class to create for the destreg.
401 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
402 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
403 const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
405 // Figure out the register class to create for the destreg.
406 // Note that if we're going to directly use an existing register,
407 // it must be precisely the required class, and not a subclass
409 if (VRBase == 0 || SRC != MRI.getRegClass(VRBase)) {
411 assert(SRC && "Couldn't find source register class");
412 VRBase = MRI.createVirtualRegister(SRC);
415 // Add def, source, and subreg index
416 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
417 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
418 MI->addOperand(MachineOperand::CreateImm(SubIdx));
419 BB->insert(InsertPos, MI);
420 } else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
421 Opc == TargetInstrInfo::SUBREG_TO_REG) {
422 SDValue N0 = Node->getOperand(0);
423 SDValue N1 = Node->getOperand(1);
424 SDValue N2 = Node->getOperand(2);
425 unsigned SubReg = getVR(N1, VRBaseMap);
426 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
427 const TargetRegisterClass *TRC = MRI.getRegClass(SubReg);
428 const TargetRegisterClass *SRC =
429 getSuperRegisterRegClass(TRC, SubIdx,
430 Node->getValueType(0));
432 // Figure out the register class to create for the destreg.
433 // Note that if we're going to directly use an existing register,
434 // it must be precisely the required class, and not a subclass
436 if (VRBase == 0 || SRC != MRI.getRegClass(VRBase)) {
438 assert(SRC && "Couldn't find source register class");
439 VRBase = MRI.createVirtualRegister(SRC);
442 // Create the insert_subreg or subreg_to_reg machine instruction.
443 MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), TII->get(Opc));
444 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
446 // If creating a subreg_to_reg, then the first input operand
447 // is an implicit value immediate, otherwise it's a register
448 if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
449 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
450 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
452 AddOperand(MI, N0, 0, 0, VRBaseMap);
453 // Add the subregster being inserted
454 AddOperand(MI, N1, 0, 0, VRBaseMap);
455 MI->addOperand(MachineOperand::CreateImm(SubIdx));
456 BB->insert(InsertPos, MI);
458 assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
461 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
462 isNew = isNew; // Silence compiler warning.
463 assert(isNew && "Node emitted out of order - early");
466 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
467 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
468 /// register is constrained to be in a particular register class.
471 ScheduleDAGSDNodes::EmitCopyToRegClassNode(SDNode *Node,
472 DenseMap<SDValue, unsigned> &VRBaseMap) {
473 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
474 const TargetRegisterClass *SrcRC = MRI.getRegClass(VReg);
476 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
477 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
479 // Create the new VReg in the destination class and emit a copy.
480 unsigned NewVReg = MRI.createVirtualRegister(DstRC);
481 bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
483 // If the target didn't handle the copy with different register
484 // classes and the destination is a subset of the source,
485 // try a normal same-RC copy.
486 if (!Emitted && SrcRC->hasSubClass(DstRC))
487 Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
490 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
493 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
494 isNew = isNew; // Silence compiler warning.
495 assert(isNew && "Node emitted out of order - early");
498 /// EmitNode - Generate machine code for an node and needed dependencies.
500 void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
501 DenseMap<SDValue, unsigned> &VRBaseMap) {
502 // If machine instruction
503 if (Node->isMachineOpcode()) {
504 unsigned Opc = Node->getMachineOpcode();
506 // Handle subreg insert/extract specially
507 if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
508 Opc == TargetInstrInfo::INSERT_SUBREG ||
509 Opc == TargetInstrInfo::SUBREG_TO_REG) {
510 EmitSubregNode(Node, VRBaseMap);
514 // Handle COPY_TO_REGCLASS specially.
515 if (Opc == TargetInstrInfo::COPY_TO_REGCLASS) {
516 EmitCopyToRegClassNode(Node, VRBaseMap);
520 if (Opc == TargetInstrInfo::IMPLICIT_DEF)
521 // We want a unique VR for each IMPLICIT_DEF use.
524 const TargetInstrDesc &II = TII->get(Opc);
525 unsigned NumResults = CountResults(Node);
526 unsigned NodeOperands = CountOperands(Node);
527 unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
528 bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
529 II.getImplicitDefs() != 0;
531 unsigned NumMIOperands = NodeOperands + NumResults;
532 assert((II.getNumOperands() == NumMIOperands ||
533 HasPhysRegOuts || II.isVariadic()) &&
534 "#operands for dag node doesn't match .td file!");
537 // Create the new machine instruction.
538 MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), II);
540 // Add result register values for things that are defined by this
543 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
545 // Emit all of the actual operands of this instruction, adding them to the
546 // instruction as appropriate.
547 for (unsigned i = 0; i != NodeOperands; ++i)
548 AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
550 // Emit all of the memory operands of this instruction
551 for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
552 AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO);
554 if (II.usesCustomDAGSchedInsertionHook()) {
555 // Insert this instruction into the basic block using a target
556 // specific inserter which may returns a new basic block.
557 BB = TLI->EmitInstrWithCustomInserter(MI, BB);
558 InsertPos = BB->end();
560 BB->insert(InsertPos, MI);
563 // Additional results must be an physical register def.
564 if (HasPhysRegOuts) {
565 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
566 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
567 if (Node->hasAnyUseOfValue(i))
568 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
574 switch (Node->getOpcode()) {
579 assert(0 && "This target-independent node should have been selected!");
581 case ISD::EntryToken:
582 assert(0 && "EntryToken should have been excluded from the schedule!");
584 case ISD::TokenFactor: // fall thru
586 case ISD::CopyToReg: {
588 SDValue SrcVal = Node->getOperand(2);
589 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
590 SrcReg = R->getReg();
592 SrcReg = getVR(SrcVal, VRBaseMap);
594 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
595 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
598 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
599 // Get the register classes of the src/dst.
600 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
601 SrcTRC = MRI.getRegClass(SrcReg);
603 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
605 if (TargetRegisterInfo::isVirtualRegister(DestReg))
606 DstTRC = MRI.getRegClass(DestReg);
608 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
609 Node->getOperand(1).getValueType());
611 bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg,
613 // If the target didn't handle the copy with different register
614 // classes and the destination is a subset of the source,
615 // try a normal same-RC copy.
616 if (!Emitted && DstTRC->hasSubClass(SrcTRC))
617 Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg,
620 assert(Emitted && "Unable to issue a copy instruction!\n");
623 case ISD::CopyFromReg: {
624 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
625 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
628 case ISD::INLINEASM: {
629 unsigned NumOps = Node->getNumOperands();
630 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
631 --NumOps; // Ignore the flag operand.
633 // Create the inline asm machine instruction.
634 MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(),
635 TII->get(TargetInstrInfo::INLINEASM));
637 // Add the asm string as an external symbol operand.
639 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
640 MI->addOperand(MachineOperand::CreateES(AsmStr));
642 // Add all of the operand registers to the instruction.
643 for (unsigned i = 2; i != NumOps;) {
645 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
646 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
648 MI->addOperand(MachineOperand::CreateImm(Flags));
649 ++i; // Skip the ID value.
652 default: assert(0 && "Bad flags!");
653 case 2: // Def of register.
654 for (; NumVals; --NumVals, ++i) {
655 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
656 MI->addOperand(MachineOperand::CreateReg(Reg, true));
659 case 6: // Def of earlyclobber register.
660 for (; NumVals; --NumVals, ++i) {
661 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
662 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
666 case 1: // Use of register.
667 case 3: // Immediate.
668 case 4: // Addressing mode.
669 // The addressing mode has been selected, just add all of the
670 // operands to the machine instruction.
671 for (; NumVals; --NumVals, ++i)
672 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
676 BB->insert(InsertPos, MI);
682 /// EmitSchedule - Emit the machine code in scheduled order.
683 MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
684 DenseMap<SDValue, unsigned> VRBaseMap;
685 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
686 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
687 SUnit *SU = Sequence[i];
689 // Null SUnit* is a noop.
694 // For pre-regalloc scheduling, create instructions corresponding to the
695 // SDNode and any flagged SDNodes and append them to the block.
696 if (!SU->getNode()) {
698 EmitPhysRegCopy(SU, CopyVRBaseMap);
702 SmallVector<SDNode *, 4> FlaggedNodes;
703 for (SDNode *N = SU->getNode()->getFlaggedNode(); N;
704 N = N->getFlaggedNode())
705 FlaggedNodes.push_back(N);
706 while (!FlaggedNodes.empty()) {
707 EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,VRBaseMap);
708 FlaggedNodes.pop_back();
710 EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap);