1 //===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the ScheduleDAG class, which creates
11 // MachineInstrs according to the computed schedule.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pre-RA-sched"
16 #include "llvm/CodeGen/ScheduleDAGSDNodes.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
31 /// getInstrOperandRegClass - Return register class of the operand of an
32 /// instruction of the specified TargetInstrDesc.
33 static const TargetRegisterClass*
34 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
35 const TargetInstrInfo *TII, const TargetInstrDesc &II,
37 if (Op >= II.getNumOperands()) {
38 assert(II.isVariadic() && "Invalid operand # of instruction");
41 if (II.OpInfo[Op].isLookupPtrRegClass())
42 return TII->getPointerRegClass();
43 return TRI->getRegClass(II.OpInfo[Op].RegClass);
46 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
47 /// implicit physical register output.
48 void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
49 bool IsClone, unsigned SrcReg,
50 DenseMap<SDValue, unsigned> &VRBaseMap) {
52 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
53 // Just use the input register directly!
54 SDValue Op(Node, ResNo);
57 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
58 isNew = isNew; // Silence compiler warning.
59 assert(isNew && "Node emitted out of order - early");
63 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
64 // the CopyToReg'd destination register instead of creating a new vreg.
66 const TargetRegisterClass *UseRC = NULL;
67 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
71 if (User->getOpcode() == ISD::CopyToReg &&
72 User->getOperand(2).getNode() == Node &&
73 User->getOperand(2).getResNo() == ResNo) {
74 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
75 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
78 } else if (DestReg != SrcReg)
81 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
82 SDValue Op = User->getOperand(i);
83 if (Op.getNode() != Node || Op.getResNo() != ResNo)
85 MVT VT = Node->getValueType(Op.getResNo());
86 if (VT == MVT::Other || VT == MVT::Flag)
89 if (User->isMachineOpcode()) {
90 const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
91 const TargetRegisterClass *RC =
92 getInstrOperandRegClass(TRI,TII,II,i+II.getNumDefs());
97 "Multiple uses expecting different register classes!");
106 MVT VT = Node->getValueType(ResNo);
107 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
108 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
110 // Figure out the register class to create for the destreg.
112 DstRC = MRI.getRegClass(VRBase);
114 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
117 DstRC = TLI->getRegClassFor(VT);
120 // If all uses are reading from the src physical register and copying the
121 // register is either impossible or very expensive, then don't create a copy.
122 if (MatchReg && SrcRC->getCopyCost() < 0) {
125 // Create the reg, emit the copy.
126 VRBase = MRI.createVirtualRegister(DstRC);
128 TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
129 Emitted = Emitted; // Silence compiler warning.
130 assert(Emitted && "Unable to issue a copy instruction!");
133 SDValue Op(Node, ResNo);
136 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
137 isNew = isNew; // Silence compiler warning.
138 assert(isNew && "Node emitted out of order - early");
141 /// getDstOfCopyToRegUse - If the only use of the specified result number of
142 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
143 unsigned ScheduleDAGSDNodes::getDstOfOnlyCopyToRegUse(SDNode *Node,
144 unsigned ResNo) const {
145 if (!Node->hasOneUse())
148 SDNode *User = *Node->use_begin();
149 if (User->getOpcode() == ISD::CopyToReg &&
150 User->getOperand(2).getNode() == Node &&
151 User->getOperand(2).getResNo() == ResNo) {
152 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
153 if (TargetRegisterInfo::isVirtualRegister(Reg))
159 void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
160 const TargetInstrDesc &II, bool IsClone,
161 DenseMap<SDValue, unsigned> &VRBaseMap) {
162 assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
163 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
165 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
166 // If the specific node value is only used by a CopyToReg and the dest reg
167 // is a vreg, use the CopyToReg'd destination register instead of creating
170 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
173 if (User->getOpcode() == ISD::CopyToReg &&
174 User->getOperand(2).getNode() == Node &&
175 User->getOperand(2).getResNo() == i) {
176 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
177 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
179 MI->addOperand(MachineOperand::CreateReg(Reg, true));
185 // Create the result registers for this node and add the result regs to
186 // the machine instruction.
188 const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
189 assert(RC && "Isn't a register operand!");
190 VRBase = MRI.createVirtualRegister(RC);
191 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
197 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
198 isNew = isNew; // Silence compiler warning.
199 assert(isNew && "Node emitted out of order - early");
203 /// getVR - Return the virtual register corresponding to the specified result
204 /// of the specified node.
205 unsigned ScheduleDAGSDNodes::getVR(SDValue Op,
206 DenseMap<SDValue, unsigned> &VRBaseMap) {
207 if (Op.isMachineOpcode() &&
208 Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
209 // Add an IMPLICIT_DEF instruction before every use.
210 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
211 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
212 // does not include operand register class info.
214 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
215 VReg = MRI.createVirtualRegister(RC);
217 BuildMI(BB, TII->get(TargetInstrInfo::IMPLICIT_DEF), VReg);
221 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
222 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
227 /// AddOperand - Add the specified operand to the specified machine instr. II
228 /// specifies the instruction information for the node, and IIOpNum is the
229 /// operand number (in the II) that we are adding. IIOpNum and II are used for
231 void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
233 const TargetInstrDesc *II,
234 DenseMap<SDValue, unsigned> &VRBaseMap) {
235 if (Op.isMachineOpcode()) {
236 // Note that this case is redundant with the final else block, but we
237 // include it because it is the most common and it makes the logic
239 assert(Op.getValueType() != MVT::Other &&
240 Op.getValueType() != MVT::Flag &&
241 "Chain and flag operands should occur at end of operand list!");
242 // Get/emit the operand.
243 unsigned VReg = getVR(Op, VRBaseMap);
244 const TargetInstrDesc &TID = MI->getDesc();
245 bool isOptDef = IIOpNum < TID.getNumOperands() &&
246 TID.OpInfo[IIOpNum].isOptionalDef();
247 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
249 // Verify that it is right.
250 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
253 // There may be no register class for this operand if it is a variadic
254 // argument (RC will be NULL in this case). In this case, we just assume
255 // the regclass is ok.
256 const TargetRegisterClass *RC =
257 getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
258 assert((RC || II->isVariadic()) && "Expected reg class info!");
259 const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
260 if (RC && VRC != RC) {
261 cerr << "Register class of operand and regclass of use don't agree!\n";
262 cerr << "Operand = " << IIOpNum << "\n";
263 cerr << "Op->Val = "; Op.getNode()->dump(DAG); cerr << "\n";
264 cerr << "MI = "; MI->print(cerr);
265 cerr << "VReg = " << VReg << "\n";
266 cerr << "VReg RegClass size = " << VRC->getSize()
267 << ", align = " << VRC->getAlignment() << "\n";
268 cerr << "Expected RegClass size = " << RC->getSize()
269 << ", align = " << RC->getAlignment() << "\n";
270 cerr << "Fatal error, aborting.\n";
275 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
276 MI->addOperand(MachineOperand::CreateImm(C->getZExtValue()));
277 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
278 const ConstantFP *CFP = F->getConstantFPValue();
279 MI->addOperand(MachineOperand::CreateFPImm(CFP));
280 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
281 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
282 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
283 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
284 } else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
285 MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
286 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
287 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
288 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
289 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex()));
290 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
291 int Offset = CP->getOffset();
292 unsigned Align = CP->getAlignment();
293 const Type *Type = CP->getType();
294 // MachineConstantPool wants an explicit alignment.
296 Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
298 // Alignment of vector types. FIXME!
299 Align = TM.getTargetData()->getABITypeSize(Type);
300 Align = Log2_64(Align);
305 if (CP->isMachineConstantPoolEntry())
306 Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
308 Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
309 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
310 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
311 MI->addOperand(MachineOperand::CreateES(ES->getSymbol()));
313 assert(Op.getValueType() != MVT::Other &&
314 Op.getValueType() != MVT::Flag &&
315 "Chain and flag operands should occur at end of operand list!");
316 unsigned VReg = getVR(Op, VRBaseMap);
317 MI->addOperand(MachineOperand::CreateReg(VReg, false));
319 // Verify that it is right. Note that the reg class of the physreg and the
320 // vreg don't necessarily need to match, but the target copy insertion has
321 // to be able to handle it. This handles things like copies from ST(0) to
322 // an FP vreg on x86.
323 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
324 if (II && !II->isVariadic()) {
325 assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
326 "Don't have operand info for this instruction!");
331 /// getSubRegisterRegClass - Returns the register class of specified register
332 /// class' "SubIdx"'th sub-register class.
333 static const TargetRegisterClass*
334 getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx) {
335 // Pick the register class of the subregister
336 TargetRegisterInfo::regclass_iterator I =
337 TRC->subregclasses_begin() + SubIdx-1;
338 assert(I < TRC->subregclasses_end() &&
339 "Invalid subregister index for register class");
343 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
344 /// "SubIdx"'th sub-register class is the specified register class and whose
345 /// type matches the specified type.
346 static const TargetRegisterClass*
347 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
348 unsigned SubIdx, MVT VT) {
349 // Pick the register class of the superegister for this type
350 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
351 E = TRC->superregclasses_end(); I != E; ++I)
352 if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
354 assert(false && "Couldn't find the register class");
358 /// EmitSubregNode - Generate machine code for subreg nodes.
360 void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
361 DenseMap<SDValue, unsigned> &VRBaseMap) {
363 unsigned Opc = Node->getMachineOpcode();
365 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
366 // the CopyToReg'd destination register instead of creating a new vreg.
367 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
370 if (User->getOpcode() == ISD::CopyToReg &&
371 User->getOperand(2).getNode() == Node) {
372 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
373 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
380 if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
381 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
383 // Create the extract_subreg machine instruction.
384 MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
386 // Figure out the register class to create for the destreg.
387 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
388 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
389 const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
392 // Grab the destination register
394 const TargetRegisterClass *DRC = MRI.getRegClass(VRBase);
395 assert(SRC && DRC && SRC == DRC &&
396 "Source subregister and destination must have the same class");
400 assert(SRC && "Couldn't find source register class");
401 VRBase = MRI.createVirtualRegister(SRC);
404 // Add def, source, and subreg index
405 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
406 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
407 MI->addOperand(MachineOperand::CreateImm(SubIdx));
409 } else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
410 Opc == TargetInstrInfo::SUBREG_TO_REG) {
411 SDValue N0 = Node->getOperand(0);
412 SDValue N1 = Node->getOperand(1);
413 SDValue N2 = Node->getOperand(2);
414 unsigned SubReg = getVR(N1, VRBaseMap);
415 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
418 // Figure out the register class to create for the destreg.
419 const TargetRegisterClass *TRC = 0;
421 TRC = MRI.getRegClass(VRBase);
423 TRC = getSuperRegisterRegClass(MRI.getRegClass(SubReg), SubIdx,
424 Node->getValueType(0));
425 assert(TRC && "Couldn't determine register class for insert_subreg");
426 VRBase = MRI.createVirtualRegister(TRC); // Create the reg
429 // Create the insert_subreg or subreg_to_reg machine instruction.
430 MachineInstr *MI = BuildMI(*MF, TII->get(Opc));
431 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
433 // If creating a subreg_to_reg, then the first input operand
434 // is an implicit value immediate, otherwise it's a register
435 if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
436 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
437 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
439 AddOperand(MI, N0, 0, 0, VRBaseMap);
440 // Add the subregster being inserted
441 AddOperand(MI, N1, 0, 0, VRBaseMap);
442 MI->addOperand(MachineOperand::CreateImm(SubIdx));
445 assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
448 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
449 isNew = isNew; // Silence compiler warning.
450 assert(isNew && "Node emitted out of order - early");
453 /// EmitNode - Generate machine code for an node and needed dependencies.
455 void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone,
456 DenseMap<SDValue, unsigned> &VRBaseMap) {
457 // If machine instruction
458 if (Node->isMachineOpcode()) {
459 unsigned Opc = Node->getMachineOpcode();
461 // Handle subreg insert/extract specially
462 if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
463 Opc == TargetInstrInfo::INSERT_SUBREG ||
464 Opc == TargetInstrInfo::SUBREG_TO_REG) {
465 EmitSubregNode(Node, VRBaseMap);
469 if (Opc == TargetInstrInfo::IMPLICIT_DEF)
470 // We want a unique VR for each IMPLICIT_DEF use.
473 const TargetInstrDesc &II = TII->get(Opc);
474 unsigned NumResults = CountResults(Node);
475 unsigned NodeOperands = CountOperands(Node);
476 unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
477 bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
478 II.getImplicitDefs() != 0;
480 unsigned NumMIOperands = NodeOperands + NumResults;
481 assert((II.getNumOperands() == NumMIOperands ||
482 HasPhysRegOuts || II.isVariadic()) &&
483 "#operands for dag node doesn't match .td file!");
486 // Create the new machine instruction.
487 MachineInstr *MI = BuildMI(*MF, II);
489 // Add result register values for things that are defined by this
492 CreateVirtualRegisters(Node, MI, II, IsClone, VRBaseMap);
494 // Emit all of the actual operands of this instruction, adding them to the
495 // instruction as appropriate.
496 for (unsigned i = 0; i != NodeOperands; ++i)
497 AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
499 // Emit all of the memory operands of this instruction
500 for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
501 AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO);
503 if (II.usesCustomDAGSchedInsertionHook())
504 // Insert this instruction into the basic block using a target
505 // specific inserter which may returns a new basic block.
506 BB = TLI->EmitInstrWithCustomInserter(MI, BB);
510 // Additional results must be an physical register def.
511 if (HasPhysRegOuts) {
512 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
513 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
514 if (Node->hasAnyUseOfValue(i))
515 EmitCopyFromReg(Node, i, IsClone, Reg, VRBaseMap);
521 switch (Node->getOpcode()) {
526 assert(0 && "This target-independent node should have been selected!");
528 case ISD::EntryToken:
529 assert(0 && "EntryToken should have been excluded from the schedule!");
531 case ISD::TokenFactor: // fall thru
533 case ISD::CopyToReg: {
535 SDValue SrcVal = Node->getOperand(2);
536 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
537 SrcReg = R->getReg();
539 SrcReg = getVR(SrcVal, VRBaseMap);
541 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
542 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
545 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
546 // Get the register classes of the src/dst.
547 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
548 SrcTRC = MRI.getRegClass(SrcReg);
550 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
552 if (TargetRegisterInfo::isVirtualRegister(DestReg))
553 DstTRC = MRI.getRegClass(DestReg);
555 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
556 Node->getOperand(1).getValueType());
557 TII->copyRegToReg(*BB, BB->end(), DestReg, SrcReg, DstTRC, SrcTRC);
560 case ISD::CopyFromReg: {
561 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
562 EmitCopyFromReg(Node, 0, IsClone, SrcReg, VRBaseMap);
565 case ISD::INLINEASM: {
566 unsigned NumOps = Node->getNumOperands();
567 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
568 --NumOps; // Ignore the flag operand.
570 // Create the inline asm machine instruction.
571 MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::INLINEASM));
573 // Add the asm string as an external symbol operand.
575 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
576 MI->addOperand(MachineOperand::CreateES(AsmStr));
578 // Add all of the operand registers to the instruction.
579 for (unsigned i = 2; i != NumOps;) {
581 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
582 unsigned NumVals = Flags >> 3;
584 MI->addOperand(MachineOperand::CreateImm(Flags));
585 ++i; // Skip the ID value.
588 default: assert(0 && "Bad flags!");
589 case 2: // Def of register.
590 for (; NumVals; --NumVals, ++i) {
591 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
592 MI->addOperand(MachineOperand::CreateReg(Reg, true));
595 case 6: // Def of earlyclobber register.
596 for (; NumVals; --NumVals, ++i) {
597 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
598 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
602 case 1: // Use of register.
603 case 3: // Immediate.
604 case 4: // Addressing mode.
605 // The addressing mode has been selected, just add all of the
606 // operands to the machine instruction.
607 for (; NumVals; --NumVals, ++i)
608 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
618 /// EmitSchedule - Emit the machine code in scheduled order.
619 MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
620 DenseMap<SDValue, unsigned> VRBaseMap;
621 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
622 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
623 SUnit *SU = Sequence[i];
625 // Null SUnit* is a noop.
630 // For pre-regalloc scheduling, create instructions corresponding to the
631 // SDNode and any flagged SDNodes and append them to the block.
632 if (!SU->getNode()) {
634 EmitPhysRegCopy(SU, CopyVRBaseMap);
638 SmallVector<SDNode *, 4> FlaggedNodes;
639 for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
640 FlaggedNodes.push_back(N);
641 while (!FlaggedNodes.empty()) {
642 EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, VRBaseMap);
643 FlaggedNodes.pop_back();
645 EmitNode(SU->getNode(), SU->OrigNode != SU, VRBaseMap);