1 //===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the ScheduleDAG class, which creates
11 // MachineInstrs according to the computed schedule.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pre-RA-sched"
16 #include "llvm/CodeGen/ScheduleDAGSDNodes.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
31 /// getInstrOperandRegClass - Return register class of the operand of an
32 /// instruction of the specified TargetInstrDesc.
33 static const TargetRegisterClass*
34 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
35 const TargetInstrInfo *TII, const TargetInstrDesc &II,
37 if (Op >= II.getNumOperands()) {
38 assert(II.isVariadic() && "Invalid operand # of instruction");
41 if (II.OpInfo[Op].isLookupPtrRegClass())
42 return TII->getPointerRegClass();
43 return TRI->getRegClass(II.OpInfo[Op].RegClass);
46 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
47 /// implicit physical register output.
48 void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
49 bool IsClone, bool IsCloned,
51 DenseMap<SDValue, unsigned> &VRBaseMap) {
53 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
54 // Just use the input register directly!
55 SDValue Op(Node, ResNo);
58 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
59 isNew = isNew; // Silence compiler warning.
60 assert(isNew && "Node emitted out of order - early");
64 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
65 // the CopyToReg'd destination register instead of creating a new vreg.
67 const TargetRegisterClass *UseRC = NULL;
68 if (!IsClone && !IsCloned)
69 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
73 if (User->getOpcode() == ISD::CopyToReg &&
74 User->getOperand(2).getNode() == Node &&
75 User->getOperand(2).getResNo() == ResNo) {
76 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
77 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
80 } else if (DestReg != SrcReg)
83 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
84 SDValue Op = User->getOperand(i);
85 if (Op.getNode() != Node || Op.getResNo() != ResNo)
87 MVT VT = Node->getValueType(Op.getResNo());
88 if (VT == MVT::Other || VT == MVT::Flag)
91 if (User->isMachineOpcode()) {
92 const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
93 const TargetRegisterClass *RC =
94 getInstrOperandRegClass(TRI,TII,II,i+II.getNumDefs());
99 "Multiple uses expecting different register classes!");
108 MVT VT = Node->getValueType(ResNo);
109 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
110 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
112 // Figure out the register class to create for the destreg.
114 DstRC = MRI.getRegClass(VRBase);
116 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
119 DstRC = TLI->getRegClassFor(VT);
122 // If all uses are reading from the src physical register and copying the
123 // register is either impossible or very expensive, then don't create a copy.
124 if (MatchReg && SrcRC->getCopyCost() < 0) {
127 // Create the reg, emit the copy.
128 VRBase = MRI.createVirtualRegister(DstRC);
130 TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
131 Emitted = Emitted; // Silence compiler warning.
132 assert(Emitted && "Unable to issue a copy instruction!");
135 SDValue Op(Node, ResNo);
138 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
139 isNew = isNew; // Silence compiler warning.
140 assert(isNew && "Node emitted out of order - early");
143 /// getDstOfCopyToRegUse - If the only use of the specified result number of
144 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
145 unsigned ScheduleDAGSDNodes::getDstOfOnlyCopyToRegUse(SDNode *Node,
146 unsigned ResNo) const {
147 if (!Node->hasOneUse())
150 SDNode *User = *Node->use_begin();
151 if (User->getOpcode() == ISD::CopyToReg &&
152 User->getOperand(2).getNode() == Node &&
153 User->getOperand(2).getResNo() == ResNo) {
154 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
155 if (TargetRegisterInfo::isVirtualRegister(Reg))
161 void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
162 const TargetInstrDesc &II,
163 bool IsClone, bool IsCloned,
164 DenseMap<SDValue, unsigned> &VRBaseMap) {
165 assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
166 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
168 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
169 // If the specific node value is only used by a CopyToReg and the dest reg
170 // is a vreg, use the CopyToReg'd destination register instead of creating
174 if (!IsClone && !IsCloned)
175 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
178 if (User->getOpcode() == ISD::CopyToReg &&
179 User->getOperand(2).getNode() == Node &&
180 User->getOperand(2).getResNo() == i) {
181 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
182 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
184 MI->addOperand(MachineOperand::CreateReg(Reg, true));
190 // Create the result registers for this node and add the result regs to
191 // the machine instruction.
193 const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
194 assert(RC && "Isn't a register operand!");
195 VRBase = MRI.createVirtualRegister(RC);
196 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
202 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
203 isNew = isNew; // Silence compiler warning.
204 assert(isNew && "Node emitted out of order - early");
208 /// getVR - Return the virtual register corresponding to the specified result
209 /// of the specified node.
210 unsigned ScheduleDAGSDNodes::getVR(SDValue Op,
211 DenseMap<SDValue, unsigned> &VRBaseMap) {
212 if (Op.isMachineOpcode() &&
213 Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
214 // Add an IMPLICIT_DEF instruction before every use.
215 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
216 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
217 // does not include operand register class info.
219 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
220 VReg = MRI.createVirtualRegister(RC);
222 BuildMI(BB, TII->get(TargetInstrInfo::IMPLICIT_DEF), VReg);
226 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
227 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
232 /// AddOperand - Add the specified operand to the specified machine instr. II
233 /// specifies the instruction information for the node, and IIOpNum is the
234 /// operand number (in the II) that we are adding. IIOpNum and II are used for
236 void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
238 const TargetInstrDesc *II,
239 DenseMap<SDValue, unsigned> &VRBaseMap) {
240 if (Op.isMachineOpcode()) {
241 // Note that this case is redundant with the final else block, but we
242 // include it because it is the most common and it makes the logic
244 assert(Op.getValueType() != MVT::Other &&
245 Op.getValueType() != MVT::Flag &&
246 "Chain and flag operands should occur at end of operand list!");
247 // Get/emit the operand.
248 unsigned VReg = getVR(Op, VRBaseMap);
249 const TargetInstrDesc &TID = MI->getDesc();
250 bool isOptDef = IIOpNum < TID.getNumOperands() &&
251 TID.OpInfo[IIOpNum].isOptionalDef();
252 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
254 // Verify that it is right.
255 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
258 // There may be no register class for this operand if it is a variadic
259 // argument (RC will be NULL in this case). In this case, we just assume
260 // the regclass is ok.
261 const TargetRegisterClass *RC =
262 getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
263 assert((RC || II->isVariadic()) && "Expected reg class info!");
264 const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
265 if (RC && VRC != RC) {
266 cerr << "Register class of operand and regclass of use don't agree!\n";
267 cerr << "Operand = " << IIOpNum << "\n";
268 cerr << "Op->Val = "; Op.getNode()->dump(DAG); cerr << "\n";
269 cerr << "MI = "; MI->print(cerr);
270 cerr << "VReg = " << VReg << "\n";
271 cerr << "VReg RegClass size = " << VRC->getSize()
272 << ", align = " << VRC->getAlignment() << "\n";
273 cerr << "Expected RegClass size = " << RC->getSize()
274 << ", align = " << RC->getAlignment() << "\n";
275 cerr << "Fatal error, aborting.\n";
280 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
281 MI->addOperand(MachineOperand::CreateImm(C->getZExtValue()));
282 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
283 const ConstantFP *CFP = F->getConstantFPValue();
284 MI->addOperand(MachineOperand::CreateFPImm(CFP));
285 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
286 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
287 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
288 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
289 } else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
290 MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
291 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
292 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
293 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
294 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex()));
295 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
296 int Offset = CP->getOffset();
297 unsigned Align = CP->getAlignment();
298 const Type *Type = CP->getType();
299 // MachineConstantPool wants an explicit alignment.
301 Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
303 // Alignment of vector types. FIXME!
304 Align = TM.getTargetData()->getTypePaddedSize(Type);
305 Align = Log2_64(Align);
310 if (CP->isMachineConstantPoolEntry())
311 Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
313 Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
314 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
315 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
316 MI->addOperand(MachineOperand::CreateES(ES->getSymbol()));
318 assert(Op.getValueType() != MVT::Other &&
319 Op.getValueType() != MVT::Flag &&
320 "Chain and flag operands should occur at end of operand list!");
321 unsigned VReg = getVR(Op, VRBaseMap);
322 MI->addOperand(MachineOperand::CreateReg(VReg, false));
324 // Verify that it is right. Note that the reg class of the physreg and the
325 // vreg don't necessarily need to match, but the target copy insertion has
326 // to be able to handle it. This handles things like copies from ST(0) to
327 // an FP vreg on x86.
328 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
329 if (II && !II->isVariadic()) {
330 assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
331 "Don't have operand info for this instruction!");
336 /// getSubRegisterRegClass - Returns the register class of specified register
337 /// class' "SubIdx"'th sub-register class.
338 static const TargetRegisterClass*
339 getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx) {
340 // Pick the register class of the subregister
341 TargetRegisterInfo::regclass_iterator I =
342 TRC->subregclasses_begin() + SubIdx-1;
343 assert(I < TRC->subregclasses_end() &&
344 "Invalid subregister index for register class");
348 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
349 /// "SubIdx"'th sub-register class is the specified register class and whose
350 /// type matches the specified type.
351 static const TargetRegisterClass*
352 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
353 unsigned SubIdx, MVT VT) {
354 // Pick the register class of the superegister for this type
355 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
356 E = TRC->superregclasses_end(); I != E; ++I)
357 if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
359 assert(false && "Couldn't find the register class");
363 /// EmitSubregNode - Generate machine code for subreg nodes.
365 void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
366 DenseMap<SDValue, unsigned> &VRBaseMap) {
368 unsigned Opc = Node->getMachineOpcode();
370 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
371 // the CopyToReg'd destination register instead of creating a new vreg.
372 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
375 if (User->getOpcode() == ISD::CopyToReg &&
376 User->getOperand(2).getNode() == Node) {
377 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
378 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
385 if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
386 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
388 // Create the extract_subreg machine instruction.
389 MachineInstr *MI = BuildMI(MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
391 // Figure out the register class to create for the destreg.
392 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
393 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
394 const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
397 // Grab the destination register
399 const TargetRegisterClass *DRC = MRI.getRegClass(VRBase);
400 assert(SRC && DRC && SRC == DRC &&
401 "Source subregister and destination must have the same class");
405 assert(SRC && "Couldn't find source register class");
406 VRBase = MRI.createVirtualRegister(SRC);
409 // Add def, source, and subreg index
410 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
411 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
412 MI->addOperand(MachineOperand::CreateImm(SubIdx));
414 } else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
415 Opc == TargetInstrInfo::SUBREG_TO_REG) {
416 SDValue N0 = Node->getOperand(0);
417 SDValue N1 = Node->getOperand(1);
418 SDValue N2 = Node->getOperand(2);
419 unsigned SubReg = getVR(N1, VRBaseMap);
420 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
423 // Figure out the register class to create for the destreg.
424 const TargetRegisterClass *TRC = 0;
426 TRC = MRI.getRegClass(VRBase);
428 TRC = getSuperRegisterRegClass(MRI.getRegClass(SubReg), SubIdx,
429 Node->getValueType(0));
430 assert(TRC && "Couldn't determine register class for insert_subreg");
431 VRBase = MRI.createVirtualRegister(TRC); // Create the reg
434 // Create the insert_subreg or subreg_to_reg machine instruction.
435 MachineInstr *MI = BuildMI(MF, TII->get(Opc));
436 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
438 // If creating a subreg_to_reg, then the first input operand
439 // is an implicit value immediate, otherwise it's a register
440 if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
441 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
442 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
444 AddOperand(MI, N0, 0, 0, VRBaseMap);
445 // Add the subregster being inserted
446 AddOperand(MI, N1, 0, 0, VRBaseMap);
447 MI->addOperand(MachineOperand::CreateImm(SubIdx));
450 assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
453 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
454 isNew = isNew; // Silence compiler warning.
455 assert(isNew && "Node emitted out of order - early");
458 /// EmitNode - Generate machine code for an node and needed dependencies.
460 void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
461 DenseMap<SDValue, unsigned> &VRBaseMap) {
462 // If machine instruction
463 if (Node->isMachineOpcode()) {
464 unsigned Opc = Node->getMachineOpcode();
466 // Handle subreg insert/extract specially
467 if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
468 Opc == TargetInstrInfo::INSERT_SUBREG ||
469 Opc == TargetInstrInfo::SUBREG_TO_REG) {
470 EmitSubregNode(Node, VRBaseMap);
474 if (Opc == TargetInstrInfo::IMPLICIT_DEF)
475 // We want a unique VR for each IMPLICIT_DEF use.
478 const TargetInstrDesc &II = TII->get(Opc);
479 unsigned NumResults = CountResults(Node);
480 unsigned NodeOperands = CountOperands(Node);
481 unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
482 bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
483 II.getImplicitDefs() != 0;
485 unsigned NumMIOperands = NodeOperands + NumResults;
486 assert((II.getNumOperands() == NumMIOperands ||
487 HasPhysRegOuts || II.isVariadic()) &&
488 "#operands for dag node doesn't match .td file!");
491 // Create the new machine instruction.
492 MachineInstr *MI = BuildMI(MF, II);
494 // Add result register values for things that are defined by this
497 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
499 // Emit all of the actual operands of this instruction, adding them to the
500 // instruction as appropriate.
501 for (unsigned i = 0; i != NodeOperands; ++i)
502 AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
504 // Emit all of the memory operands of this instruction
505 for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
506 AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO);
508 if (II.usesCustomDAGSchedInsertionHook())
509 // Insert this instruction into the basic block using a target
510 // specific inserter which may returns a new basic block.
511 BB = TLI->EmitInstrWithCustomInserter(MI, BB);
515 // Additional results must be an physical register def.
516 if (HasPhysRegOuts) {
517 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
518 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
519 if (Node->hasAnyUseOfValue(i))
520 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
526 switch (Node->getOpcode()) {
531 assert(0 && "This target-independent node should have been selected!");
533 case ISD::EntryToken:
534 assert(0 && "EntryToken should have been excluded from the schedule!");
536 case ISD::TokenFactor: // fall thru
538 case ISD::CopyToReg: {
540 SDValue SrcVal = Node->getOperand(2);
541 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
542 SrcReg = R->getReg();
544 SrcReg = getVR(SrcVal, VRBaseMap);
546 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
547 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
550 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
551 // Get the register classes of the src/dst.
552 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
553 SrcTRC = MRI.getRegClass(SrcReg);
555 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
557 if (TargetRegisterInfo::isVirtualRegister(DestReg))
558 DstTRC = MRI.getRegClass(DestReg);
560 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
561 Node->getOperand(1).getValueType());
562 TII->copyRegToReg(*BB, BB->end(), DestReg, SrcReg, DstTRC, SrcTRC);
565 case ISD::CopyFromReg: {
566 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
567 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
570 case ISD::INLINEASM: {
571 unsigned NumOps = Node->getNumOperands();
572 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
573 --NumOps; // Ignore the flag operand.
575 // Create the inline asm machine instruction.
576 MachineInstr *MI = BuildMI(MF, TII->get(TargetInstrInfo::INLINEASM));
578 // Add the asm string as an external symbol operand.
580 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
581 MI->addOperand(MachineOperand::CreateES(AsmStr));
583 // Add all of the operand registers to the instruction.
584 for (unsigned i = 2; i != NumOps;) {
586 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
587 unsigned NumVals = Flags >> 3;
589 MI->addOperand(MachineOperand::CreateImm(Flags));
590 ++i; // Skip the ID value.
593 default: assert(0 && "Bad flags!");
594 case 2: // Def of register.
595 for (; NumVals; --NumVals, ++i) {
596 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
597 MI->addOperand(MachineOperand::CreateReg(Reg, true));
600 case 6: // Def of earlyclobber register.
601 for (; NumVals; --NumVals, ++i) {
602 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
603 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
607 case 1: // Use of register.
608 case 3: // Immediate.
609 case 4: // Addressing mode.
610 // The addressing mode has been selected, just add all of the
611 // operands to the machine instruction.
612 for (; NumVals; --NumVals, ++i)
613 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
623 /// EmitSchedule - Emit the machine code in scheduled order.
624 MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
625 DenseMap<SDValue, unsigned> VRBaseMap;
626 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
627 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
628 SUnit *SU = Sequence[i];
630 // Null SUnit* is a noop.
635 // For pre-regalloc scheduling, create instructions corresponding to the
636 // SDNode and any flagged SDNodes and append them to the block.
637 if (!SU->getNode()) {
639 EmitPhysRegCopy(SU, CopyVRBaseMap);
643 SmallVector<SDNode *, 4> FlaggedNodes;
644 for (SDNode *N = SU->getNode()->getFlaggedNode(); N;
645 N = N->getFlaggedNode())
646 FlaggedNodes.push_back(N);
647 while (!FlaggedNodes.empty()) {
648 EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,VRBaseMap);
649 FlaggedNodes.pop_back();
651 EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap);