1 //===-- ScheduleDAGSimple.cpp - Implement a trivial DAG scheduler ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by James M. Laskey and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple two pass scheduler. The first pass attempts to push
11 // backward any lengthy instructions and critical paths. The second pass packs
12 // instructions into semi-optimal time slots.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "sched"
17 #include "llvm/CodeGen/ScheduleDAG.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 #include "llvm/Support/Debug.h"
27 //===----------------------------------------------------------------------===//
29 /// BitsIterator - Provides iteration through individual bits in a bit vector.
34 T Bits; // Bits left to iterate through
38 BitsIterator(T Initial) : Bits(Initial) {}
40 /// Next - Returns the next bit set or zero if exhausted.
42 // Get the rightmost bit set
43 T Result = Bits & -Bits;
46 // Return single bit or zero
51 //===----------------------------------------------------------------------===//
54 //===----------------------------------------------------------------------===//
56 /// ResourceTally - Manages the use of resources over time intervals. Each
57 /// item (slot) in the tally vector represents the resources used at a given
58 /// moment. A bit set to 1 indicates that a resource is in use, otherwise
59 /// available. An assumption is made that the tally is large enough to schedule
60 /// all current instructions (asserts otherwise.)
65 std::vector<T> Tally; // Resources used per slot
66 typedef typename std::vector<T>::iterator Iter;
69 /// SlotsAvailable - Returns true if all units are available.
71 bool SlotsAvailable(Iter Begin, unsigned N, unsigned ResourceSet,
73 assert(N && "Must check availability with N != 0");
74 // Determine end of interval
76 assert(End <= Tally.end() && "Tally is not large enough for schedule");
78 // Iterate thru each resource
79 BitsIterator<T> Resources(ResourceSet & ~*Begin);
80 while (unsigned Res = Resources.Next()) {
81 // Check if resource is available for next N slots
85 if (*Interval & Res) break;
86 } while (Interval != Begin);
89 if (Interval == Begin) {
101 /// RetrySlot - Finds a good candidate slot to retry search.
102 Iter RetrySlot(Iter Begin, unsigned N, unsigned ResourceSet) {
103 assert(N && "Must check availability with N != 0");
104 // Determine end of interval
105 Iter End = Begin + N;
106 assert(End <= Tally.end() && "Tally is not large enough for schedule");
108 while (Begin != End--) {
109 // Clear units in use
110 ResourceSet &= ~*End;
111 // If no units left then we should go no further
112 if (!ResourceSet) return End + 1;
114 // Made it all the way through
118 /// FindAndReserveStages - Return true if the stages can be completed. If
120 bool FindAndReserveStages(Iter Begin,
121 InstrStage *Stage, InstrStage *StageEnd) {
122 // If at last stage then we're done
123 if (Stage == StageEnd) return true;
124 // Get number of cycles for current stage
125 unsigned N = Stage->Cycles;
126 // Check to see if N slots are available, if not fail
128 if (!SlotsAvailable(Begin, N, Stage->Units, Resource)) return false;
129 // Check to see if remaining stages are available, if not fail
130 if (!FindAndReserveStages(Begin + N, Stage + 1, StageEnd)) return false;
132 Reserve(Begin, N, Resource);
137 /// Reserve - Mark busy (set) the specified N slots.
138 void Reserve(Iter Begin, unsigned N, unsigned Resource) {
139 // Determine end of interval
140 Iter End = Begin + N;
141 assert(End <= Tally.end() && "Tally is not large enough for schedule");
143 // Set resource bit in each slot
144 for (; Begin < End; Begin++)
148 /// FindSlots - Starting from Begin, locate consecutive slots where all stages
149 /// can be completed. Returns the address of first slot.
150 Iter FindSlots(Iter Begin, InstrStage *StageBegin, InstrStage *StageEnd) {
154 // Try all possible slots forward
156 // Try at cursor, if successful return position.
157 if (FindAndReserveStages(Cursor, StageBegin, StageEnd)) return Cursor;
158 // Locate a better position
159 Cursor = RetrySlot(Cursor + 1, StageBegin->Cycles, StageBegin->Units);
164 /// Initialize - Resize and zero the tally to the specified number of time
166 inline void Initialize(unsigned N) {
167 Tally.assign(N, 0); // Initialize tally to all zeros.
170 // FindAndReserve - Locate an ideal slot for the specified stages and mark
172 unsigned FindAndReserve(unsigned Slot, InstrStage *StageBegin,
173 InstrStage *StageEnd) {
175 Iter Begin = Tally.begin() + Slot;
177 Iter Where = FindSlots(Begin, StageBegin, StageEnd);
178 // Distance is slot number
179 unsigned Final = Where - Tally.begin();
185 //===----------------------------------------------------------------------===//
187 /// ScheduleDAGSimple - Simple two pass scheduler.
189 class ScheduleDAGSimple : public ScheduleDAG {
191 bool NoSched; // Just do a BFS schedule, nothing fancy
192 bool NoItins; // Don't use itineraries?
193 ResourceTally<unsigned> Tally; // Resource usage tally
194 unsigned NSlots; // Total latency
195 static const unsigned NotFound = ~0U; // Search marker
197 unsigned NodeCount; // Number of nodes in DAG
198 std::map<SDNode *, NodeInfo *> Map; // Map nodes to info
199 bool HasGroups; // True if there are any groups
200 NodeInfo *Info; // Info for nodes being scheduled
201 NIVector Ordering; // Emit ordering of nodes
202 NodeGroup *HeadNG, *TailNG; // Keep track of allocated NodeGroups
207 ScheduleDAGSimple(bool noSched, bool noItins, SelectionDAG &dag,
208 MachineBasicBlock *bb, const TargetMachine &tm)
209 : ScheduleDAG(dag, bb, tm), NoSched(noSched), NoItins(noItins), NSlots(0),
210 NodeCount(0), HasGroups(false), Info(NULL), HeadNG(NULL), TailNG(NULL) {
211 assert(&TII && "Target doesn't provide instr info?");
212 assert(&MRI && "Target doesn't provide register info?");
215 virtual ~ScheduleDAGSimple() {
219 NodeGroup *NG = HeadNG;
221 NodeGroup *NextSU = NG->Next;
229 /// getNI - Returns the node info for the specified node.
231 NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
234 static bool isDefiner(NodeInfo *A, NodeInfo *B);
235 void IncludeNode(NodeInfo *NI);
237 void GatherSchedulingInfo();
238 void FakeGroupDominators();
239 bool isStrongDependency(NodeInfo *A, NodeInfo *B);
240 bool isWeakDependency(NodeInfo *A, NodeInfo *B);
241 void ScheduleBackward();
242 void ScheduleForward();
244 void AddToGroup(NodeInfo *D, NodeInfo *U);
245 /// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
247 void PrepareNodeInfo();
249 /// IdentifyGroups - Put flagged nodes into groups.
251 void IdentifyGroups();
253 /// print - Print ordering to specified output stream.
255 void print(std::ostream &O) const;
257 void dump(const char *tag) const;
259 virtual void dump() const;
261 /// EmitAll - Emit all nodes in schedule sorted order.
265 /// printNI - Print node info.
267 void printNI(std::ostream &O, NodeInfo *NI) const;
269 /// printChanges - Hilight changes in order caused by scheduling.
271 void printChanges(unsigned Index) const;
274 //===----------------------------------------------------------------------===//
275 /// Special case itineraries.
278 CallLatency = 40, // To push calls back in time
280 RSInteger = 0xC0000000, // Two integer units
281 RSFloat = 0x30000000, // Two float units
282 RSLoadStore = 0x0C000000, // Two load store units
283 RSBranch = 0x02000000 // One branch unit
285 static InstrStage CallStage = { CallLatency, RSBranch };
286 static InstrStage LoadStage = { 5, RSLoadStore };
287 static InstrStage StoreStage = { 2, RSLoadStore };
288 static InstrStage IntStage = { 2, RSInteger };
289 static InstrStage FloatStage = { 3, RSFloat };
290 //===----------------------------------------------------------------------===//
294 //===----------------------------------------------------------------------===//
296 /// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
298 void ScheduleDAGSimple::PrepareNodeInfo() {
299 // Allocate node information
300 Info = new NodeInfo[NodeCount];
303 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
304 E = DAG.allnodes_end(); I != E; ++I, ++i) {
305 // Fast reference to node schedule info
306 NodeInfo* NI = &Info[i];
311 // Set pending visit count
312 NI->setPending(I->use_size());
316 /// IdentifyGroups - Put flagged nodes into groups.
318 void ScheduleDAGSimple::IdentifyGroups() {
319 for (unsigned i = 0, N = NodeCount; i < N; i++) {
320 NodeInfo* NI = &Info[i];
321 SDNode *Node = NI->Node;
323 // For each operand (in reverse to only look at flags)
324 for (unsigned N = Node->getNumOperands(); 0 < N--;) {
326 SDOperand Op = Node->getOperand(N);
327 // No more flags to walk
328 if (Op.getValueType() != MVT::Flag) break;
330 AddToGroup(getNI(Op.Val), NI);
331 // Let everyone else know
337 /// CountInternalUses - Returns the number of edges between the two nodes.
339 static unsigned CountInternalUses(NodeInfo *D, NodeInfo *U) {
341 for (unsigned M = U->Node->getNumOperands(); 0 < M--;) {
342 SDOperand Op = U->Node->getOperand(M);
343 if (Op.Val == D->Node) N++;
349 //===----------------------------------------------------------------------===//
350 /// Add - Adds a definer and user pair to a node group.
352 void ScheduleDAGSimple::AddToGroup(NodeInfo *D, NodeInfo *U) {
353 // Get current groups
354 NodeGroup *DGroup = D->Group;
355 NodeGroup *UGroup = U->Group;
356 // If both are members of groups
357 if (DGroup && UGroup) {
358 // There may have been another edge connecting
359 if (DGroup == UGroup) return;
360 // Add the pending users count
361 DGroup->addPending(UGroup->getPending());
362 // For each member of the users group
363 NodeGroupIterator UNGI(U);
364 while (NodeInfo *UNI = UNGI.next() ) {
367 // For each member of the definers group
368 NodeGroupIterator DNGI(D);
369 while (NodeInfo *DNI = DNGI.next() ) {
370 // Remove internal edges
371 DGroup->addPending(-CountInternalUses(DNI, UNI));
374 // Merge the two lists
375 DGroup->group_insert(DGroup->group_end(),
376 UGroup->group_begin(), UGroup->group_end());
378 // Make user member of definers group
380 // Add users uses to definers group pending
381 DGroup->addPending(U->Node->use_size());
382 // For each member of the definers group
383 NodeGroupIterator DNGI(D);
384 while (NodeInfo *DNI = DNGI.next() ) {
385 // Remove internal edges
386 DGroup->addPending(-CountInternalUses(DNI, U));
388 DGroup->group_push_back(U);
390 // Make definer member of users group
392 // Add definers uses to users group pending
393 UGroup->addPending(D->Node->use_size());
394 // For each member of the users group
395 NodeGroupIterator UNGI(U);
396 while (NodeInfo *UNI = UNGI.next() ) {
397 // Remove internal edges
398 UGroup->addPending(-CountInternalUses(D, UNI));
400 UGroup->group_insert(UGroup->group_begin(), D);
402 D->Group = U->Group = DGroup = new NodeGroup();
403 DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
404 CountInternalUses(D, U));
405 DGroup->group_push_back(D);
406 DGroup->group_push_back(U);
411 TailNG->Next = DGroup;
417 /// print - Print ordering to specified output stream.
419 void ScheduleDAGSimple::print(std::ostream &O) const {
422 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
423 NodeInfo *NI = Ordering[i];
426 if (NI->isGroupDominator()) {
427 NodeGroup *Group = NI->Group;
428 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
439 void ScheduleDAGSimple::dump(const char *tag) const {
440 std::cerr << tag; dump();
443 void ScheduleDAGSimple::dump() const {
448 /// EmitAll - Emit all nodes in schedule sorted order.
450 void ScheduleDAGSimple::EmitAll() {
451 std::map<SDNode*, unsigned> VRBaseMap;
453 // For each node in the ordering
454 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
455 // Get the scheduling info
456 NodeInfo *NI = Ordering[i];
457 if (NI->isInGroup()) {
458 NodeGroupIterator NGI(Ordering[i]);
459 while (NodeInfo *NI = NGI.next()) EmitNode(NI->Node, VRBaseMap);
461 EmitNode(NI->Node, VRBaseMap);
466 /// isFlagDefiner - Returns true if the node defines a flag result.
467 static bool isFlagDefiner(SDNode *A) {
468 unsigned N = A->getNumValues();
469 return N && A->getValueType(N - 1) == MVT::Flag;
472 /// isFlagUser - Returns true if the node uses a flag result.
474 static bool isFlagUser(SDNode *A) {
475 unsigned N = A->getNumOperands();
476 return N && A->getOperand(N - 1).getValueType() == MVT::Flag;
479 /// printNI - Print node info.
481 void ScheduleDAGSimple::printNI(std::ostream &O, NodeInfo *NI) const {
483 SDNode *Node = NI->Node;
485 << std::hex << Node << std::dec
486 << ", Lat=" << NI->Latency
487 << ", Slot=" << NI->Slot
488 << ", ARITY=(" << Node->getNumOperands() << ","
489 << Node->getNumValues() << ")"
490 << " " << Node->getOperationName(&DAG);
491 if (isFlagDefiner(Node)) O << "<#";
492 if (isFlagUser(Node)) O << ">#";
496 /// printChanges - Hilight changes in order caused by scheduling.
498 void ScheduleDAGSimple::printChanges(unsigned Index) const {
500 // Get the ordered node count
501 unsigned N = Ordering.size();
502 // Determine if any changes
505 NodeInfo *NI = Ordering[i];
506 if (NI->Preorder != i) break;
510 std::cerr << Index << ". New Ordering\n";
512 for (i = 0; i < N; i++) {
513 NodeInfo *NI = Ordering[i];
514 std::cerr << " " << NI->Preorder << ". ";
515 printNI(std::cerr, NI);
517 if (NI->isGroupDominator()) {
518 NodeGroup *Group = NI->Group;
519 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
522 printNI(std::cerr, *NII);
528 std::cerr << Index << ". No Changes\n";
533 //===----------------------------------------------------------------------===//
534 /// isDefiner - Return true if node A is a definer for B.
536 bool ScheduleDAGSimple::isDefiner(NodeInfo *A, NodeInfo *B) {
537 // While there are A nodes
538 NodeGroupIterator NII(A);
539 while (NodeInfo *NI = NII.next()) {
541 SDNode *Node = NI->Node;
542 // While there operands in nodes of B
543 NodeGroupOpIterator NGOI(B);
544 while (!NGOI.isEnd()) {
545 SDOperand Op = NGOI.next();
546 // If node from A defines a node in B
547 if (Node == Op.Val) return true;
553 /// IncludeNode - Add node to NodeInfo vector.
555 void ScheduleDAGSimple::IncludeNode(NodeInfo *NI) {
557 SDNode *Node = NI->Node;
559 if (Node->getOpcode() == ISD::EntryToken) return;
560 // Check current count for node
561 int Count = NI->getPending();
562 // If the node is already in list
563 if (Count < 0) return;
564 // Decrement count to indicate a visit
566 // If count has gone to zero then add node to list
569 if (NI->isInGroup()) {
570 Ordering.push_back(NI->Group->getDominator());
572 Ordering.push_back(NI);
574 // indicate node has been added
577 // Mark as visited with new count
578 NI->setPending(Count);
581 /// GatherSchedulingInfo - Get latency and resource information about each node.
583 void ScheduleDAGSimple::GatherSchedulingInfo() {
584 // Get instruction itineraries for the target
585 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
588 for (unsigned i = 0, N = NodeCount; i < N; i++) {
590 NodeInfo* NI = &Info[i];
591 SDNode *Node = NI->Node;
593 // If there are itineraries and it is a machine instruction
594 if (InstrItins.isEmpty() || NoItins) {
596 if (Node->isTargetOpcode()) {
597 // Get return type to guess which processing unit
598 MVT::ValueType VT = Node->getValueType(0);
599 // Get machine opcode
600 MachineOpCode TOpc = Node->getTargetOpcode();
601 NI->IsCall = TII->isCall(TOpc);
602 NI->IsLoad = TII->isLoad(TOpc);
603 NI->IsStore = TII->isStore(TOpc);
605 if (TII->isLoad(TOpc)) NI->StageBegin = &LoadStage;
606 else if (TII->isStore(TOpc)) NI->StageBegin = &StoreStage;
607 else if (MVT::isInteger(VT)) NI->StageBegin = &IntStage;
608 else if (MVT::isFloatingPoint(VT)) NI->StageBegin = &FloatStage;
609 if (NI->StageBegin) NI->StageEnd = NI->StageBegin + 1;
611 } else if (Node->isTargetOpcode()) {
612 // get machine opcode
613 MachineOpCode TOpc = Node->getTargetOpcode();
614 // Check to see if it is a call
615 NI->IsCall = TII->isCall(TOpc);
616 // Get itinerary stages for instruction
617 unsigned II = TII->getSchedClass(TOpc);
618 NI->StageBegin = InstrItins.begin(II);
619 NI->StageEnd = InstrItins.end(II);
622 // One slot for the instruction itself
625 // Add long latency for a call to push it back in time
626 if (NI->IsCall) NI->Latency += CallLatency;
628 // Sum up all the latencies
629 for (InstrStage *Stage = NI->StageBegin, *E = NI->StageEnd;
630 Stage != E; Stage++) {
631 NI->Latency += Stage->Cycles;
634 // Sum up all the latencies for max tally size
635 NSlots += NI->Latency;
638 // Unify metrics if in a group
640 for (unsigned i = 0, N = NodeCount; i < N; i++) {
641 NodeInfo* NI = &Info[i];
643 if (NI->isInGroup()) {
644 NodeGroup *Group = NI->Group;
646 if (!Group->getDominator()) {
647 NIIterator NGI = Group->group_begin(), NGE = Group->group_end();
648 NodeInfo *Dominator = *NGI;
649 unsigned Latency = 0;
651 for (NGI++; NGI != NGE; NGI++) {
652 NodeInfo* NGNI = *NGI;
653 Latency += NGNI->Latency;
654 if (Dominator->Latency < NGNI->Latency) Dominator = NGNI;
657 Dominator->Latency = Latency;
658 Group->setDominator(Dominator);
665 /// VisitAll - Visit each node breadth-wise to produce an initial ordering.
666 /// Note that the ordering in the Nodes vector is reversed.
667 void ScheduleDAGSimple::VisitAll() {
668 // Add first element to list
669 NodeInfo *NI = getNI(DAG.getRoot().Val);
670 if (NI->isInGroup()) {
671 Ordering.push_back(NI->Group->getDominator());
673 Ordering.push_back(NI);
676 // Iterate through all nodes that have been added
677 for (unsigned i = 0; i < Ordering.size(); i++) { // note: size() varies
678 // Visit all operands
679 NodeGroupOpIterator NGI(Ordering[i]);
680 while (!NGI.isEnd()) {
682 SDOperand Op = NGI.next();
684 SDNode *Node = Op.Val;
685 // Ignore passive nodes
686 if (isPassiveNode(Node)) continue;
688 IncludeNode(getNI(Node));
692 // Add entry node last (IncludeNode filters entry nodes)
693 if (DAG.getEntryNode().Val != DAG.getRoot().Val)
694 Ordering.push_back(getNI(DAG.getEntryNode().Val));
697 std::reverse(Ordering.begin(), Ordering.end());
700 /// FakeGroupDominators - Set dominators for non-scheduling.
702 void ScheduleDAGSimple::FakeGroupDominators() {
703 for (unsigned i = 0, N = NodeCount; i < N; i++) {
704 NodeInfo* NI = &Info[i];
706 if (NI->isInGroup()) {
707 NodeGroup *Group = NI->Group;
709 if (!Group->getDominator()) {
710 Group->setDominator(NI);
716 /// isStrongDependency - Return true if node A has results used by node B.
717 /// I.E., B must wait for latency of A.
718 bool ScheduleDAGSimple::isStrongDependency(NodeInfo *A, NodeInfo *B) {
719 // If A defines for B then it's a strong dependency or
720 // if a load follows a store (may be dependent but why take a chance.)
721 return isDefiner(A, B) || (A->IsStore && B->IsLoad);
724 /// isWeakDependency Return true if node A produces a result that will
725 /// conflict with operands of B. It is assumed that we have called
726 /// isStrongDependency prior.
727 bool ScheduleDAGSimple::isWeakDependency(NodeInfo *A, NodeInfo *B) {
728 // TODO check for conflicting real registers and aliases
729 #if 0 // FIXME - Since we are in SSA form and not checking register aliasing
730 return A->Node->getOpcode() == ISD::EntryToken || isStrongDependency(B, A);
732 return A->Node->getOpcode() == ISD::EntryToken;
736 /// ScheduleBackward - Schedule instructions so that any long latency
737 /// instructions and the critical path get pushed back in time. Time is run in
738 /// reverse to allow code reuse of the Tally and eliminate the overhead of
739 /// biasing every slot indices against NSlots.
740 void ScheduleDAGSimple::ScheduleBackward() {
741 // Size and clear the resource tally
742 Tally.Initialize(NSlots);
743 // Get number of nodes to schedule
744 unsigned N = Ordering.size();
746 // For each node being scheduled
747 for (unsigned i = N; 0 < i--;) {
748 NodeInfo *NI = Ordering[i];
750 unsigned Slot = NotFound;
752 // Compare against those previously scheduled nodes
755 // Get following instruction
756 NodeInfo *Other = Ordering[j];
758 // Check dependency against previously inserted nodes
759 if (isStrongDependency(NI, Other)) {
760 Slot = Other->Slot + Other->Latency;
762 } else if (isWeakDependency(NI, Other)) {
768 // If independent of others (or first entry)
769 if (Slot == NotFound) Slot = 0;
771 #if 0 // FIXME - measure later
772 // Find a slot where the needed resources are available
773 if (NI->StageBegin != NI->StageEnd)
774 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
780 // Insert sort based on slot
783 // Get following instruction
784 NodeInfo *Other = Ordering[j];
785 // Should we look further (remember slots are in reverse time)
786 if (Slot >= Other->Slot) break;
787 // Shuffle other into ordering
788 Ordering[j - 1] = Other;
790 // Insert node in proper slot
791 if (j != i + 1) Ordering[j - 1] = NI;
795 /// ScheduleForward - Schedule instructions to maximize packing.
797 void ScheduleDAGSimple::ScheduleForward() {
798 // Size and clear the resource tally
799 Tally.Initialize(NSlots);
800 // Get number of nodes to schedule
801 unsigned N = Ordering.size();
803 // For each node being scheduled
804 for (unsigned i = 0; i < N; i++) {
805 NodeInfo *NI = Ordering[i];
807 unsigned Slot = NotFound;
809 // Compare against those previously scheduled nodes
812 // Get following instruction
813 NodeInfo *Other = Ordering[j];
815 // Check dependency against previously inserted nodes
816 if (isStrongDependency(Other, NI)) {
817 Slot = Other->Slot + Other->Latency;
819 } else if (Other->IsCall || isWeakDependency(Other, NI)) {
825 // If independent of others (or first entry)
826 if (Slot == NotFound) Slot = 0;
828 // Find a slot where the needed resources are available
829 if (NI->StageBegin != NI->StageEnd)
830 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
835 // Insert sort based on slot
838 // Get prior instruction
839 NodeInfo *Other = Ordering[j];
840 // Should we look further
841 if (Slot >= Other->Slot) break;
842 // Shuffle other into ordering
843 Ordering[j + 1] = Other;
845 // Insert node in proper slot
846 if (j != i) Ordering[j + 1] = NI;
850 /// Schedule - Order nodes according to selected style.
852 void ScheduleDAGSimple::Schedule() {
854 NodeCount = std::distance(DAG.allnodes_begin(), DAG.allnodes_end());
856 // Set up minimum info for scheduling
858 // Construct node groups for flagged nodes
861 // Test to see if scheduling should occur
862 bool ShouldSchedule = NodeCount > 3 && !NoSched;
863 // Don't waste time if is only entry and return
864 if (ShouldSchedule) {
865 // Get latency and resource requirements
866 GatherSchedulingInfo();
867 } else if (HasGroups) {
868 // Make sure all the groups have dominators
869 FakeGroupDominators();
872 // Breadth first walk of DAG
876 static unsigned Count = 0;
878 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
879 NodeInfo *NI = Ordering[i];
884 // Don't waste time if is only entry and return
885 if (ShouldSchedule) {
886 // Push back long instructions and critical path
889 // Pack instructions to maximize resource utilization
893 DEBUG(printChanges(Count));
895 // Emit in scheduled order
900 /// createSimpleDAGScheduler - This creates a simple two pass instruction
902 llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(bool NoItins,
904 MachineBasicBlock *BB) {
905 return new ScheduleDAGSimple(false, NoItins, DAG, BB, DAG.getTarget());
908 llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAG &DAG,
909 MachineBasicBlock *BB) {
910 return new ScheduleDAGSimple(true, false, DAG, BB, DAG.getTarget());