1 //===-- ScheduleDAGSimple.cpp - Implement a trivial DAG scheduler ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by James M. Laskey and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple two pass scheduler. The first pass attempts to push
11 // backward any lengthy instructions and critical paths. The second pass packs
12 // instructions into semi-optimal time slots.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "sched"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/CodeGen/SchedulerRegistry.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/Compiler.h"
34 static RegisterScheduler
35 bfsDAGScheduler("none", " No scheduling: breadth first sequencing",
36 createBFS_DAGScheduler);
37 static RegisterScheduler
38 simpleDAGScheduler("simple",
39 " Simple two pass scheduling: minimize critical path "
40 "and maximize processor utilization",
41 createSimpleDAGScheduler);
42 static RegisterScheduler
43 noitinDAGScheduler("simple-noitin",
44 " Simple two pass scheduling: Same as simple "
45 "except using generic latency",
46 createNoItinsDAGScheduler);
49 typedef NodeInfo *NodeInfoPtr;
50 typedef std::vector<NodeInfoPtr> NIVector;
51 typedef std::vector<NodeInfoPtr>::iterator NIIterator;
53 //===--------------------------------------------------------------------===//
55 /// Node group - This struct is used to manage flagged node groups.
61 NIVector Members; // Group member nodes
62 NodeInfo *Dominator; // Node with highest latency
63 unsigned Latency; // Total latency of the group
64 int Pending; // Number of visits pending before
69 NodeGroup() : Next(NULL), Dominator(NULL), Pending(0) {}
72 inline void setDominator(NodeInfo *D) { Dominator = D; }
73 inline NodeInfo *getTop() { return Members.front(); }
74 inline NodeInfo *getBottom() { return Members.back(); }
75 inline NodeInfo *getDominator() { return Dominator; }
76 inline void setLatency(unsigned L) { Latency = L; }
77 inline unsigned getLatency() { return Latency; }
78 inline int getPending() const { return Pending; }
79 inline void setPending(int P) { Pending = P; }
80 inline int addPending(int I) { return Pending += I; }
83 inline bool group_empty() { return Members.empty(); }
84 inline NIIterator group_begin() { return Members.begin(); }
85 inline NIIterator group_end() { return Members.end(); }
86 inline void group_push_back(const NodeInfoPtr &NI) {
87 Members.push_back(NI);
89 inline NIIterator group_insert(NIIterator Pos, const NodeInfoPtr &NI) {
90 return Members.insert(Pos, NI);
92 inline void group_insert(NIIterator Pos, NIIterator First,
94 Members.insert(Pos, First, Last);
97 static void Add(NodeInfo *D, NodeInfo *U);
100 //===--------------------------------------------------------------------===//
102 /// NodeInfo - This struct tracks information used to schedule the a node.
106 int Pending; // Number of visits pending before
109 SDNode *Node; // DAG node
110 InstrStage *StageBegin; // First stage in itinerary
111 InstrStage *StageEnd; // Last+1 stage in itinerary
112 unsigned Latency; // Total cycles to complete instr
113 bool IsCall : 1; // Is function call
114 bool IsLoad : 1; // Is memory load
115 bool IsStore : 1; // Is memory store
116 unsigned Slot; // Node's time slot
117 NodeGroup *Group; // Grouping information
119 unsigned Preorder; // Index before scheduling
123 NodeInfo(SDNode *N = NULL)
138 inline bool isInGroup() const {
139 assert(!Group || !Group->group_empty() && "Group with no members");
140 return Group != NULL;
142 inline bool isGroupDominator() const {
143 return isInGroup() && Group->getDominator() == this;
145 inline int getPending() const {
146 return Group ? Group->getPending() : Pending;
148 inline void setPending(int P) {
149 if (Group) Group->setPending(P);
152 inline int addPending(int I) {
153 if (Group) return Group->addPending(I);
154 else return Pending += I;
158 //===--------------------------------------------------------------------===//
160 /// NodeGroupIterator - Iterates over all the nodes indicated by the node
161 /// info. If the node is in a group then iterate over the members of the
162 /// group, otherwise just the node info.
164 class NodeGroupIterator {
166 NodeInfo *NI; // Node info
167 NIIterator NGI; // Node group iterator
168 NIIterator NGE; // Node group iterator end
172 NodeGroupIterator(NodeInfo *N) : NI(N) {
173 // If the node is in a group then set up the group iterator. Otherwise
174 // the group iterators will trip first time out.
175 if (N->isInGroup()) {
177 NodeGroup *Group = NI->Group;
178 NGI = Group->group_begin();
179 NGE = Group->group_end();
180 // Prevent this node from being used (will be in members list
185 /// next - Return the next node info, otherwise NULL.
189 if (NGI != NGE) return *NGI++;
190 // Use node as the result (may be NULL)
191 NodeInfo *Result = NI;
194 // Return node or NULL
198 //===--------------------------------------------------------------------===//
201 //===--------------------------------------------------------------------===//
203 /// NodeGroupOpIterator - Iterates over all the operands of a node. If the
204 /// node is a member of a group, this iterates over all the operands of all
205 /// the members of the group.
207 class NodeGroupOpIterator {
209 NodeInfo *NI; // Node containing operands
210 NodeGroupIterator GI; // Node group iterator
211 SDNode::op_iterator OI; // Operand iterator
212 SDNode::op_iterator OE; // Operand iterator end
214 /// CheckNode - Test if node has more operands. If not get the next node
215 /// skipping over nodes that have no operands.
217 // Only if operands are exhausted first
219 // Get next node info
220 NodeInfo *NI = GI.next();
221 // Exit if nodes are exhausted
224 SDNode *Node = NI->Node;
225 // Set up the operand iterators
226 OI = Node->op_begin();
233 NodeGroupOpIterator(NodeInfo *N)
234 : NI(N), GI(N), OI(SDNode::op_iterator()), OE(SDNode::op_iterator()) {}
236 /// isEnd - Returns true when not more operands are available.
238 inline bool isEnd() { CheckNode(); return OI == OE; }
240 /// next - Returns the next available operand.
242 inline SDOperand next() {
244 "Not checking for end of NodeGroupOpIterator correctly");
250 //===----------------------------------------------------------------------===//
252 /// BitsIterator - Provides iteration through individual bits in a bit vector.
257 T Bits; // Bits left to iterate through
261 BitsIterator(T Initial) : Bits(Initial) {}
263 /// Next - Returns the next bit set or zero if exhausted.
265 // Get the rightmost bit set
266 T Result = Bits & -Bits;
269 // Return single bit or zero
274 //===----------------------------------------------------------------------===//
277 //===----------------------------------------------------------------------===//
279 /// ResourceTally - Manages the use of resources over time intervals. Each
280 /// item (slot) in the tally vector represents the resources used at a given
281 /// moment. A bit set to 1 indicates that a resource is in use, otherwise
282 /// available. An assumption is made that the tally is large enough to schedule
283 /// all current instructions (asserts otherwise.)
286 class ResourceTally {
288 std::vector<T> Tally; // Resources used per slot
289 typedef typename std::vector<T>::iterator Iter;
292 /// SlotsAvailable - Returns true if all units are available.
294 bool SlotsAvailable(Iter Begin, unsigned N, unsigned ResourceSet,
295 unsigned &Resource) {
296 assert(N && "Must check availability with N != 0");
297 // Determine end of interval
298 Iter End = Begin + N;
299 assert(End <= Tally.end() && "Tally is not large enough for schedule");
301 // Iterate thru each resource
302 BitsIterator<T> Resources(ResourceSet & ~*Begin);
303 while (unsigned Res = Resources.Next()) {
304 // Check if resource is available for next N slots
308 if (*Interval & Res) break;
309 } while (Interval != Begin);
311 // If available for N
312 if (Interval == Begin) {
324 /// RetrySlot - Finds a good candidate slot to retry search.
325 Iter RetrySlot(Iter Begin, unsigned N, unsigned ResourceSet) {
326 assert(N && "Must check availability with N != 0");
327 // Determine end of interval
328 Iter End = Begin + N;
329 assert(End <= Tally.end() && "Tally is not large enough for schedule");
331 while (Begin != End--) {
332 // Clear units in use
333 ResourceSet &= ~*End;
334 // If no units left then we should go no further
335 if (!ResourceSet) return End + 1;
337 // Made it all the way through
341 /// FindAndReserveStages - Return true if the stages can be completed. If
343 bool FindAndReserveStages(Iter Begin,
344 InstrStage *Stage, InstrStage *StageEnd) {
345 // If at last stage then we're done
346 if (Stage == StageEnd) return true;
347 // Get number of cycles for current stage
348 unsigned N = Stage->Cycles;
349 // Check to see if N slots are available, if not fail
351 if (!SlotsAvailable(Begin, N, Stage->Units, Resource)) return false;
352 // Check to see if remaining stages are available, if not fail
353 if (!FindAndReserveStages(Begin + N, Stage + 1, StageEnd)) return false;
355 Reserve(Begin, N, Resource);
360 /// Reserve - Mark busy (set) the specified N slots.
361 void Reserve(Iter Begin, unsigned N, unsigned Resource) {
362 // Determine end of interval
363 Iter End = Begin + N;
364 assert(End <= Tally.end() && "Tally is not large enough for schedule");
366 // Set resource bit in each slot
367 for (; Begin < End; Begin++)
371 /// FindSlots - Starting from Begin, locate consecutive slots where all stages
372 /// can be completed. Returns the address of first slot.
373 Iter FindSlots(Iter Begin, InstrStage *StageBegin, InstrStage *StageEnd) {
377 // Try all possible slots forward
379 // Try at cursor, if successful return position.
380 if (FindAndReserveStages(Cursor, StageBegin, StageEnd)) return Cursor;
381 // Locate a better position
382 Cursor = RetrySlot(Cursor + 1, StageBegin->Cycles, StageBegin->Units);
387 /// Initialize - Resize and zero the tally to the specified number of time
389 inline void Initialize(unsigned N) {
390 Tally.assign(N, 0); // Initialize tally to all zeros.
393 // FindAndReserve - Locate an ideal slot for the specified stages and mark
395 unsigned FindAndReserve(unsigned Slot, InstrStage *StageBegin,
396 InstrStage *StageEnd) {
398 Iter Begin = Tally.begin() + Slot;
400 Iter Where = FindSlots(Begin, StageBegin, StageEnd);
401 // Distance is slot number
402 unsigned Final = Where - Tally.begin();
408 //===----------------------------------------------------------------------===//
410 /// ScheduleDAGSimple - Simple two pass scheduler.
412 class VISIBILITY_HIDDEN ScheduleDAGSimple : public ScheduleDAG {
414 bool NoSched; // Just do a BFS schedule, nothing fancy
415 bool NoItins; // Don't use itineraries?
416 ResourceTally<unsigned> Tally; // Resource usage tally
417 unsigned NSlots; // Total latency
418 static const unsigned NotFound = ~0U; // Search marker
420 unsigned NodeCount; // Number of nodes in DAG
421 std::map<SDNode *, NodeInfo *> Map; // Map nodes to info
422 bool HasGroups; // True if there are any groups
423 NodeInfo *Info; // Info for nodes being scheduled
424 NIVector Ordering; // Emit ordering of nodes
425 NodeGroup *HeadNG, *TailNG; // Keep track of allocated NodeGroups
430 ScheduleDAGSimple(bool noSched, bool noItins, SelectionDAG &dag,
431 MachineBasicBlock *bb, const TargetMachine &tm)
432 : ScheduleDAG(dag, bb, tm), NoSched(noSched), NoItins(noItins), NSlots(0),
433 NodeCount(0), HasGroups(false), Info(NULL), HeadNG(NULL), TailNG(NULL) {
434 assert(&TII && "Target doesn't provide instr info?");
435 assert(&MRI && "Target doesn't provide register info?");
438 virtual ~ScheduleDAGSimple() {
442 NodeGroup *NG = HeadNG;
444 NodeGroup *NextSU = NG->Next;
452 /// getNI - Returns the node info for the specified node.
454 NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
457 static bool isDefiner(NodeInfo *A, NodeInfo *B);
458 void IncludeNode(NodeInfo *NI);
460 void GatherSchedulingInfo();
461 void FakeGroupDominators();
462 bool isStrongDependency(NodeInfo *A, NodeInfo *B);
463 bool isWeakDependency(NodeInfo *A, NodeInfo *B);
464 void ScheduleBackward();
465 void ScheduleForward();
467 void AddToGroup(NodeInfo *D, NodeInfo *U);
468 /// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
470 void PrepareNodeInfo();
472 /// IdentifyGroups - Put flagged nodes into groups.
474 void IdentifyGroups();
476 /// print - Print ordering to specified output stream.
478 void print(std::ostream &O) const;
480 void dump(const char *tag) const;
482 virtual void dump() const;
484 /// EmitAll - Emit all nodes in schedule sorted order.
488 /// printNI - Print node info.
490 void printNI(std::ostream &O, NodeInfo *NI) const;
492 /// printChanges - Hilight changes in order caused by scheduling.
494 void printChanges(unsigned Index) const;
497 //===----------------------------------------------------------------------===//
498 /// Special case itineraries.
501 CallLatency = 40, // To push calls back in time
503 RSInteger = 0xC0000000, // Two integer units
504 RSFloat = 0x30000000, // Two float units
505 RSLoadStore = 0x0C000000, // Two load store units
506 RSBranch = 0x02000000 // One branch unit
508 static InstrStage LoadStage = { 5, RSLoadStore };
509 static InstrStage StoreStage = { 2, RSLoadStore };
510 static InstrStage IntStage = { 2, RSInteger };
511 static InstrStage FloatStage = { 3, RSFloat };
512 //===----------------------------------------------------------------------===//
516 //===----------------------------------------------------------------------===//
518 /// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
520 void ScheduleDAGSimple::PrepareNodeInfo() {
521 // Allocate node information
522 Info = new NodeInfo[NodeCount];
525 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
526 E = DAG.allnodes_end(); I != E; ++I, ++i) {
527 // Fast reference to node schedule info
528 NodeInfo* NI = &Info[i];
533 // Set pending visit count
534 NI->setPending(I->use_size());
538 /// IdentifyGroups - Put flagged nodes into groups.
540 void ScheduleDAGSimple::IdentifyGroups() {
541 for (unsigned i = 0, N = NodeCount; i < N; i++) {
542 NodeInfo* NI = &Info[i];
543 SDNode *Node = NI->Node;
545 // For each operand (in reverse to only look at flags)
546 for (unsigned N = Node->getNumOperands(); 0 < N--;) {
548 SDOperand Op = Node->getOperand(N);
549 // No more flags to walk
550 if (Op.getValueType() != MVT::Flag) break;
552 AddToGroup(getNI(Op.Val), NI);
553 // Let everyone else know
559 /// CountInternalUses - Returns the number of edges between the two nodes.
561 static unsigned CountInternalUses(NodeInfo *D, NodeInfo *U) {
563 for (unsigned M = U->Node->getNumOperands(); 0 < M--;) {
564 SDOperand Op = U->Node->getOperand(M);
565 if (Op.Val == D->Node) N++;
571 //===----------------------------------------------------------------------===//
572 /// Add - Adds a definer and user pair to a node group.
574 void ScheduleDAGSimple::AddToGroup(NodeInfo *D, NodeInfo *U) {
575 // Get current groups
576 NodeGroup *DGroup = D->Group;
577 NodeGroup *UGroup = U->Group;
578 // If both are members of groups
579 if (DGroup && UGroup) {
580 // There may have been another edge connecting
581 if (DGroup == UGroup) return;
582 // Add the pending users count
583 DGroup->addPending(UGroup->getPending());
584 // For each member of the users group
585 NodeGroupIterator UNGI(U);
586 while (NodeInfo *UNI = UNGI.next() ) {
589 // For each member of the definers group
590 NodeGroupIterator DNGI(D);
591 while (NodeInfo *DNI = DNGI.next() ) {
592 // Remove internal edges
593 DGroup->addPending(-CountInternalUses(DNI, UNI));
596 // Merge the two lists
597 DGroup->group_insert(DGroup->group_end(),
598 UGroup->group_begin(), UGroup->group_end());
600 // Make user member of definers group
602 // Add users uses to definers group pending
603 DGroup->addPending(U->Node->use_size());
604 // For each member of the definers group
605 NodeGroupIterator DNGI(D);
606 while (NodeInfo *DNI = DNGI.next() ) {
607 // Remove internal edges
608 DGroup->addPending(-CountInternalUses(DNI, U));
610 DGroup->group_push_back(U);
612 // Make definer member of users group
614 // Add definers uses to users group pending
615 UGroup->addPending(D->Node->use_size());
616 // For each member of the users group
617 NodeGroupIterator UNGI(U);
618 while (NodeInfo *UNI = UNGI.next() ) {
619 // Remove internal edges
620 UGroup->addPending(-CountInternalUses(D, UNI));
622 UGroup->group_insert(UGroup->group_begin(), D);
624 D->Group = U->Group = DGroup = new NodeGroup();
625 DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
626 CountInternalUses(D, U));
627 DGroup->group_push_back(D);
628 DGroup->group_push_back(U);
633 TailNG->Next = DGroup;
639 /// print - Print ordering to specified output stream.
641 void ScheduleDAGSimple::print(std::ostream &O) const {
644 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
645 NodeInfo *NI = Ordering[i];
648 if (NI->isGroupDominator()) {
649 NodeGroup *Group = NI->Group;
650 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
661 void ScheduleDAGSimple::dump(const char *tag) const {
662 std::cerr << tag; dump();
665 void ScheduleDAGSimple::dump() const {
670 /// EmitAll - Emit all nodes in schedule sorted order.
672 void ScheduleDAGSimple::EmitAll() {
673 // If this is the first basic block in the function, and if it has live ins
674 // that need to be copied into vregs, emit the copies into the top of the
675 // block before emitting the code for the block.
676 MachineFunction &MF = DAG.getMachineFunction();
677 if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) {
678 for (MachineFunction::livein_iterator LI = MF.livein_begin(),
679 E = MF.livein_end(); LI != E; ++LI)
681 MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
682 LI->first, RegMap->getRegClass(LI->second));
685 std::map<SDNode*, unsigned> VRBaseMap;
687 // For each node in the ordering
688 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
689 // Get the scheduling info
690 NodeInfo *NI = Ordering[i];
691 if (NI->isInGroup()) {
692 NodeGroupIterator NGI(Ordering[i]);
693 while (NodeInfo *NI = NGI.next()) EmitNode(NI->Node, VRBaseMap);
695 EmitNode(NI->Node, VRBaseMap);
700 /// isFlagDefiner - Returns true if the node defines a flag result.
701 static bool isFlagDefiner(SDNode *A) {
702 unsigned N = A->getNumValues();
703 return N && A->getValueType(N - 1) == MVT::Flag;
706 /// isFlagUser - Returns true if the node uses a flag result.
708 static bool isFlagUser(SDNode *A) {
709 unsigned N = A->getNumOperands();
710 return N && A->getOperand(N - 1).getValueType() == MVT::Flag;
713 /// printNI - Print node info.
715 void ScheduleDAGSimple::printNI(std::ostream &O, NodeInfo *NI) const {
717 SDNode *Node = NI->Node;
719 << std::hex << Node << std::dec
720 << ", Lat=" << NI->Latency
721 << ", Slot=" << NI->Slot
722 << ", ARITY=(" << Node->getNumOperands() << ","
723 << Node->getNumValues() << ")"
724 << " " << Node->getOperationName(&DAG);
725 if (isFlagDefiner(Node)) O << "<#";
726 if (isFlagUser(Node)) O << ">#";
730 /// printChanges - Hilight changes in order caused by scheduling.
732 void ScheduleDAGSimple::printChanges(unsigned Index) const {
734 // Get the ordered node count
735 unsigned N = Ordering.size();
736 // Determine if any changes
739 NodeInfo *NI = Ordering[i];
740 if (NI->Preorder != i) break;
744 std::cerr << Index << ". New Ordering\n";
746 for (i = 0; i < N; i++) {
747 NodeInfo *NI = Ordering[i];
748 std::cerr << " " << NI->Preorder << ". ";
749 printNI(std::cerr, NI);
751 if (NI->isGroupDominator()) {
752 NodeGroup *Group = NI->Group;
753 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
756 printNI(std::cerr, *NII);
762 std::cerr << Index << ". No Changes\n";
767 //===----------------------------------------------------------------------===//
768 /// isDefiner - Return true if node A is a definer for B.
770 bool ScheduleDAGSimple::isDefiner(NodeInfo *A, NodeInfo *B) {
771 // While there are A nodes
772 NodeGroupIterator NII(A);
773 while (NodeInfo *NI = NII.next()) {
775 SDNode *Node = NI->Node;
776 // While there operands in nodes of B
777 NodeGroupOpIterator NGOI(B);
778 while (!NGOI.isEnd()) {
779 SDOperand Op = NGOI.next();
780 // If node from A defines a node in B
781 if (Node == Op.Val) return true;
787 /// IncludeNode - Add node to NodeInfo vector.
789 void ScheduleDAGSimple::IncludeNode(NodeInfo *NI) {
791 SDNode *Node = NI->Node;
793 if (Node->getOpcode() == ISD::EntryToken) return;
794 // Check current count for node
795 int Count = NI->getPending();
796 // If the node is already in list
797 if (Count < 0) return;
798 // Decrement count to indicate a visit
800 // If count has gone to zero then add node to list
803 if (NI->isInGroup()) {
804 Ordering.push_back(NI->Group->getDominator());
806 Ordering.push_back(NI);
808 // indicate node has been added
811 // Mark as visited with new count
812 NI->setPending(Count);
815 /// GatherSchedulingInfo - Get latency and resource information about each node.
817 void ScheduleDAGSimple::GatherSchedulingInfo() {
818 // Get instruction itineraries for the target
819 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
822 for (unsigned i = 0, N = NodeCount; i < N; i++) {
824 NodeInfo* NI = &Info[i];
825 SDNode *Node = NI->Node;
827 // If there are itineraries and it is a machine instruction
828 if (InstrItins.isEmpty() || NoItins) {
830 if (Node->isTargetOpcode()) {
831 // Get return type to guess which processing unit
832 MVT::ValueType VT = Node->getValueType(0);
833 // Get machine opcode
834 MachineOpCode TOpc = Node->getTargetOpcode();
835 NI->IsCall = TII->isCall(TOpc);
836 NI->IsLoad = TII->isLoad(TOpc);
837 NI->IsStore = TII->isStore(TOpc);
839 if (TII->isLoad(TOpc)) NI->StageBegin = &LoadStage;
840 else if (TII->isStore(TOpc)) NI->StageBegin = &StoreStage;
841 else if (MVT::isInteger(VT)) NI->StageBegin = &IntStage;
842 else if (MVT::isFloatingPoint(VT)) NI->StageBegin = &FloatStage;
843 if (NI->StageBegin) NI->StageEnd = NI->StageBegin + 1;
845 } else if (Node->isTargetOpcode()) {
846 // get machine opcode
847 MachineOpCode TOpc = Node->getTargetOpcode();
848 // Check to see if it is a call
849 NI->IsCall = TII->isCall(TOpc);
850 // Get itinerary stages for instruction
851 unsigned II = TII->getSchedClass(TOpc);
852 NI->StageBegin = InstrItins.begin(II);
853 NI->StageEnd = InstrItins.end(II);
856 // One slot for the instruction itself
859 // Add long latency for a call to push it back in time
860 if (NI->IsCall) NI->Latency += CallLatency;
862 // Sum up all the latencies
863 for (InstrStage *Stage = NI->StageBegin, *E = NI->StageEnd;
864 Stage != E; Stage++) {
865 NI->Latency += Stage->Cycles;
868 // Sum up all the latencies for max tally size
869 NSlots += NI->Latency;
872 // Unify metrics if in a group
874 for (unsigned i = 0, N = NodeCount; i < N; i++) {
875 NodeInfo* NI = &Info[i];
877 if (NI->isInGroup()) {
878 NodeGroup *Group = NI->Group;
880 if (!Group->getDominator()) {
881 NIIterator NGI = Group->group_begin(), NGE = Group->group_end();
882 NodeInfo *Dominator = *NGI;
883 unsigned Latency = 0;
885 for (NGI++; NGI != NGE; NGI++) {
886 NodeInfo* NGNI = *NGI;
887 Latency += NGNI->Latency;
888 if (Dominator->Latency < NGNI->Latency) Dominator = NGNI;
891 Dominator->Latency = Latency;
892 Group->setDominator(Dominator);
899 /// VisitAll - Visit each node breadth-wise to produce an initial ordering.
900 /// Note that the ordering in the Nodes vector is reversed.
901 void ScheduleDAGSimple::VisitAll() {
902 // Add first element to list
903 NodeInfo *NI = getNI(DAG.getRoot().Val);
904 if (NI->isInGroup()) {
905 Ordering.push_back(NI->Group->getDominator());
907 Ordering.push_back(NI);
910 // Iterate through all nodes that have been added
911 for (unsigned i = 0; i < Ordering.size(); i++) { // note: size() varies
912 // Visit all operands
913 NodeGroupOpIterator NGI(Ordering[i]);
914 while (!NGI.isEnd()) {
916 SDOperand Op = NGI.next();
918 SDNode *Node = Op.Val;
919 // Ignore passive nodes
920 if (isPassiveNode(Node)) continue;
922 IncludeNode(getNI(Node));
926 // Add entry node last (IncludeNode filters entry nodes)
927 if (DAG.getEntryNode().Val != DAG.getRoot().Val)
928 Ordering.push_back(getNI(DAG.getEntryNode().Val));
931 std::reverse(Ordering.begin(), Ordering.end());
934 /// FakeGroupDominators - Set dominators for non-scheduling.
936 void ScheduleDAGSimple::FakeGroupDominators() {
937 for (unsigned i = 0, N = NodeCount; i < N; i++) {
938 NodeInfo* NI = &Info[i];
940 if (NI->isInGroup()) {
941 NodeGroup *Group = NI->Group;
943 if (!Group->getDominator()) {
944 Group->setDominator(NI);
950 /// isStrongDependency - Return true if node A has results used by node B.
951 /// I.E., B must wait for latency of A.
952 bool ScheduleDAGSimple::isStrongDependency(NodeInfo *A, NodeInfo *B) {
953 // If A defines for B then it's a strong dependency or
954 // if a load follows a store (may be dependent but why take a chance.)
955 return isDefiner(A, B) || (A->IsStore && B->IsLoad);
958 /// isWeakDependency Return true if node A produces a result that will
959 /// conflict with operands of B. It is assumed that we have called
960 /// isStrongDependency prior.
961 bool ScheduleDAGSimple::isWeakDependency(NodeInfo *A, NodeInfo *B) {
962 // TODO check for conflicting real registers and aliases
963 #if 0 // FIXME - Since we are in SSA form and not checking register aliasing
964 return A->Node->getOpcode() == ISD::EntryToken || isStrongDependency(B, A);
966 return A->Node->getOpcode() == ISD::EntryToken;
970 /// ScheduleBackward - Schedule instructions so that any long latency
971 /// instructions and the critical path get pushed back in time. Time is run in
972 /// reverse to allow code reuse of the Tally and eliminate the overhead of
973 /// biasing every slot indices against NSlots.
974 void ScheduleDAGSimple::ScheduleBackward() {
975 // Size and clear the resource tally
976 Tally.Initialize(NSlots);
977 // Get number of nodes to schedule
978 unsigned N = Ordering.size();
980 // For each node being scheduled
981 for (unsigned i = N; 0 < i--;) {
982 NodeInfo *NI = Ordering[i];
984 unsigned Slot = NotFound;
986 // Compare against those previously scheduled nodes
989 // Get following instruction
990 NodeInfo *Other = Ordering[j];
992 // Check dependency against previously inserted nodes
993 if (isStrongDependency(NI, Other)) {
994 Slot = Other->Slot + Other->Latency;
996 } else if (isWeakDependency(NI, Other)) {
1002 // If independent of others (or first entry)
1003 if (Slot == NotFound) Slot = 0;
1005 #if 0 // FIXME - measure later
1006 // Find a slot where the needed resources are available
1007 if (NI->StageBegin != NI->StageEnd)
1008 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
1014 // Insert sort based on slot
1016 for (; j < N; j++) {
1017 // Get following instruction
1018 NodeInfo *Other = Ordering[j];
1019 // Should we look further (remember slots are in reverse time)
1020 if (Slot >= Other->Slot) break;
1021 // Shuffle other into ordering
1022 Ordering[j - 1] = Other;
1024 // Insert node in proper slot
1025 if (j != i + 1) Ordering[j - 1] = NI;
1029 /// ScheduleForward - Schedule instructions to maximize packing.
1031 void ScheduleDAGSimple::ScheduleForward() {
1032 // Size and clear the resource tally
1033 Tally.Initialize(NSlots);
1034 // Get number of nodes to schedule
1035 unsigned N = Ordering.size();
1037 // For each node being scheduled
1038 for (unsigned i = 0; i < N; i++) {
1039 NodeInfo *NI = Ordering[i];
1041 unsigned Slot = NotFound;
1043 // Compare against those previously scheduled nodes
1046 // Get following instruction
1047 NodeInfo *Other = Ordering[j];
1049 // Check dependency against previously inserted nodes
1050 if (isStrongDependency(Other, NI)) {
1051 Slot = Other->Slot + Other->Latency;
1053 } else if (Other->IsCall || isWeakDependency(Other, NI)) {
1059 // If independent of others (or first entry)
1060 if (Slot == NotFound) Slot = 0;
1062 // Find a slot where the needed resources are available
1063 if (NI->StageBegin != NI->StageEnd)
1064 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
1069 // Insert sort based on slot
1072 // Get prior instruction
1073 NodeInfo *Other = Ordering[j];
1074 // Should we look further
1075 if (Slot >= Other->Slot) break;
1076 // Shuffle other into ordering
1077 Ordering[j + 1] = Other;
1079 // Insert node in proper slot
1080 if (j != i) Ordering[j + 1] = NI;
1084 /// Schedule - Order nodes according to selected style.
1086 void ScheduleDAGSimple::Schedule() {
1088 NodeCount = std::distance(DAG.allnodes_begin(), DAG.allnodes_end());
1090 // Set up minimum info for scheduling
1092 // Construct node groups for flagged nodes
1095 // Test to see if scheduling should occur
1096 bool ShouldSchedule = NodeCount > 3 && !NoSched;
1097 // Don't waste time if is only entry and return
1098 if (ShouldSchedule) {
1099 // Get latency and resource requirements
1100 GatherSchedulingInfo();
1101 } else if (HasGroups) {
1102 // Make sure all the groups have dominators
1103 FakeGroupDominators();
1106 // Breadth first walk of DAG
1110 static unsigned Count = 0;
1112 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
1113 NodeInfo *NI = Ordering[i];
1118 // Don't waste time if is only entry and return
1119 if (ShouldSchedule) {
1120 // Push back long instructions and critical path
1123 // Pack instructions to maximize resource utilization
1127 DEBUG(printChanges(Count));
1129 // Emit in scheduled order
1134 /// createSimpleDAGScheduler - This creates a simple two pass instruction
1135 /// scheduler using instruction itinerary.
1136 llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SelectionDAGISel *IS,
1138 MachineBasicBlock *BB) {
1139 return new ScheduleDAGSimple(false, false, *DAG, BB, DAG->getTarget());
1142 /// createNoItinsDAGScheduler - This creates a simple two pass instruction
1143 /// scheduler without using instruction itinerary.
1144 llvm::ScheduleDAG* llvm::createNoItinsDAGScheduler(SelectionDAGISel *IS,
1146 MachineBasicBlock *BB) {
1147 return new ScheduleDAGSimple(false, true, *DAG, BB, DAG->getTarget());
1150 /// createBFS_DAGScheduler - This creates a simple breadth first instruction
1152 llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAGISel *IS,
1154 MachineBasicBlock *BB) {
1155 return new ScheduleDAGSimple(true, false, *DAG, BB, DAG->getTarget());